xref: /OK3568_Linux_fs/kernel/drivers/net/ethernet/arc/emac.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2004-2013 Synopsys, Inc. (www.synopsys.com)
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Registers and bits definitions of ARC EMAC
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #ifndef ARC_EMAC_H
9*4882a593Smuzhiyun #define ARC_EMAC_H
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <linux/device.h>
12*4882a593Smuzhiyun #include <linux/dma-mapping.h>
13*4882a593Smuzhiyun #include <linux/netdevice.h>
14*4882a593Smuzhiyun #include <linux/phy.h>
15*4882a593Smuzhiyun #include <linux/clk.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun /* STATUS and ENABLE Register bit masks */
18*4882a593Smuzhiyun #define TXINT_MASK	(1 << 0)	/* Transmit interrupt */
19*4882a593Smuzhiyun #define RXINT_MASK	(1 << 1)	/* Receive interrupt */
20*4882a593Smuzhiyun #define ERR_MASK	(1 << 2)	/* Error interrupt */
21*4882a593Smuzhiyun #define TXCH_MASK	(1 << 3)	/* Transmit chaining error interrupt */
22*4882a593Smuzhiyun #define MSER_MASK	(1 << 4)	/* Missed packet counter error */
23*4882a593Smuzhiyun #define RXCR_MASK	(1 << 8)	/* RXCRCERR counter rolled over  */
24*4882a593Smuzhiyun #define RXFR_MASK	(1 << 9)	/* RXFRAMEERR counter rolled over */
25*4882a593Smuzhiyun #define RXFL_MASK	(1 << 10)	/* RXOFLOWERR counter rolled over */
26*4882a593Smuzhiyun #define MDIO_MASK	(1 << 12)	/* MDIO complete interrupt */
27*4882a593Smuzhiyun #define TXPL_MASK	(1 << 31)	/* Force polling of BD by EMAC */
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun /* CONTROL Register bit masks */
30*4882a593Smuzhiyun #define EN_MASK		(1 << 0)	/* VMAC enable */
31*4882a593Smuzhiyun #define TXRN_MASK	(1 << 3)	/* TX enable */
32*4882a593Smuzhiyun #define RXRN_MASK	(1 << 4)	/* RX enable */
33*4882a593Smuzhiyun #define DSBC_MASK	(1 << 8)	/* Disable receive broadcast */
34*4882a593Smuzhiyun #define ENFL_MASK	(1 << 10)	/* Enable Full-duplex */
35*4882a593Smuzhiyun #define PROM_MASK	(1 << 11)	/* Promiscuous mode */
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun /* Buffer descriptor INFO bit masks */
38*4882a593Smuzhiyun #define OWN_MASK	(1 << 31)	/* 0-CPU or 1-EMAC owns buffer */
39*4882a593Smuzhiyun #define FIRST_MASK	(1 << 16)	/* First buffer in chain */
40*4882a593Smuzhiyun #define LAST_MASK	(1 << 17)	/* Last buffer in chain */
41*4882a593Smuzhiyun #define LEN_MASK	0x000007FF	/* last 11 bits */
42*4882a593Smuzhiyun #define CRLS		(1 << 21)
43*4882a593Smuzhiyun #define DEFR		(1 << 22)
44*4882a593Smuzhiyun #define DROP		(1 << 23)
45*4882a593Smuzhiyun #define RTRY		(1 << 24)
46*4882a593Smuzhiyun #define LTCL		(1 << 28)
47*4882a593Smuzhiyun #define UFLO		(1 << 29)
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun #define FOR_EMAC	OWN_MASK
50*4882a593Smuzhiyun #define FOR_CPU		0
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun /* ARC EMAC register set combines entries for MAC and MDIO */
53*4882a593Smuzhiyun enum {
54*4882a593Smuzhiyun 	R_ID = 0,
55*4882a593Smuzhiyun 	R_STATUS,
56*4882a593Smuzhiyun 	R_ENABLE,
57*4882a593Smuzhiyun 	R_CTRL,
58*4882a593Smuzhiyun 	R_POLLRATE,
59*4882a593Smuzhiyun 	R_RXERR,
60*4882a593Smuzhiyun 	R_MISS,
61*4882a593Smuzhiyun 	R_TX_RING,
62*4882a593Smuzhiyun 	R_RX_RING,
63*4882a593Smuzhiyun 	R_ADDRL,
64*4882a593Smuzhiyun 	R_ADDRH,
65*4882a593Smuzhiyun 	R_LAFL,
66*4882a593Smuzhiyun 	R_LAFH,
67*4882a593Smuzhiyun 	R_MDIO,
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun #define TX_TIMEOUT		(400 * HZ / 1000) /* Transmission timeout */
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun #define ARC_EMAC_NAPI_WEIGHT	40		/* Workload for NAPI */
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun #define EMAC_BUFFER_SIZE	1536		/* EMAC buffer size */
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun /**
77*4882a593Smuzhiyun  * struct arc_emac_bd - EMAC buffer descriptor (BD).
78*4882a593Smuzhiyun  *
79*4882a593Smuzhiyun  * @info:	Contains status information on the buffer itself.
80*4882a593Smuzhiyun  * @data:	32-bit byte addressable pointer to the packet data.
81*4882a593Smuzhiyun  */
82*4882a593Smuzhiyun struct arc_emac_bd {
83*4882a593Smuzhiyun 	__le32 info;
84*4882a593Smuzhiyun 	dma_addr_t data;
85*4882a593Smuzhiyun };
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun /* Number of Rx/Tx BD's */
88*4882a593Smuzhiyun #define RX_BD_NUM	128
89*4882a593Smuzhiyun #define TX_BD_NUM	128
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun #define RX_RING_SZ	(RX_BD_NUM * sizeof(struct arc_emac_bd))
92*4882a593Smuzhiyun #define TX_RING_SZ	(TX_BD_NUM * sizeof(struct arc_emac_bd))
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun /**
95*4882a593Smuzhiyun  * struct buffer_state - Stores Rx/Tx buffer state.
96*4882a593Smuzhiyun  * @sk_buff:	Pointer to socket buffer.
97*4882a593Smuzhiyun  * @addr:	Start address of DMA-mapped memory region.
98*4882a593Smuzhiyun  * @len:	Length of DMA-mapped memory region.
99*4882a593Smuzhiyun  */
100*4882a593Smuzhiyun struct buffer_state {
101*4882a593Smuzhiyun 	struct sk_buff *skb;
102*4882a593Smuzhiyun 	DEFINE_DMA_UNMAP_ADDR(addr);
103*4882a593Smuzhiyun 	DEFINE_DMA_UNMAP_LEN(len);
104*4882a593Smuzhiyun };
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun struct arc_emac_mdio_bus_data {
107*4882a593Smuzhiyun 	struct gpio_desc *reset_gpio;
108*4882a593Smuzhiyun 	int msec;
109*4882a593Smuzhiyun };
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun /**
112*4882a593Smuzhiyun  * struct arc_emac_priv - Storage of EMAC's private information.
113*4882a593Smuzhiyun  * @dev:	Pointer to the current device.
114*4882a593Smuzhiyun  * @phy_dev:	Pointer to attached PHY device.
115*4882a593Smuzhiyun  * @bus:	Pointer to the current MII bus.
116*4882a593Smuzhiyun  * @regs:	Base address of EMAC memory-mapped control registers.
117*4882a593Smuzhiyun  * @napi:	Structure for NAPI.
118*4882a593Smuzhiyun  * @rxbd:	Pointer to Rx BD ring.
119*4882a593Smuzhiyun  * @txbd:	Pointer to Tx BD ring.
120*4882a593Smuzhiyun  * @rxbd_dma:	DMA handle for Rx BD ring.
121*4882a593Smuzhiyun  * @txbd_dma:	DMA handle for Tx BD ring.
122*4882a593Smuzhiyun  * @rx_buff:	Storage for Rx buffers states.
123*4882a593Smuzhiyun  * @tx_buff:	Storage for Tx buffers states.
124*4882a593Smuzhiyun  * @txbd_curr:	Index of Tx BD to use on the next "ndo_start_xmit".
125*4882a593Smuzhiyun  * @txbd_dirty:	Index of Tx BD to free on the next Tx interrupt.
126*4882a593Smuzhiyun  * @last_rx_bd:	Index of the last Rx BD we've got from EMAC.
127*4882a593Smuzhiyun  * @link:	PHY's last seen link state.
128*4882a593Smuzhiyun  * @duplex:	PHY's last set duplex mode.
129*4882a593Smuzhiyun  * @speed:	PHY's last set speed.
130*4882a593Smuzhiyun  */
131*4882a593Smuzhiyun struct arc_emac_priv {
132*4882a593Smuzhiyun 	const char *drv_name;
133*4882a593Smuzhiyun 	void (*set_mac_speed)(void *priv, unsigned int speed);
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	/* Devices */
136*4882a593Smuzhiyun 	struct device *dev;
137*4882a593Smuzhiyun 	struct mii_bus *bus;
138*4882a593Smuzhiyun 	struct arc_emac_mdio_bus_data bus_data;
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	void __iomem *regs;
141*4882a593Smuzhiyun 	struct clk *clk;
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	struct napi_struct napi;
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	struct arc_emac_bd *rxbd;
146*4882a593Smuzhiyun 	struct arc_emac_bd *txbd;
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	dma_addr_t rxbd_dma;
149*4882a593Smuzhiyun 	dma_addr_t txbd_dma;
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	struct buffer_state rx_buff[RX_BD_NUM];
152*4882a593Smuzhiyun 	struct buffer_state tx_buff[TX_BD_NUM];
153*4882a593Smuzhiyun 	unsigned int txbd_curr;
154*4882a593Smuzhiyun 	unsigned int txbd_dirty;
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	unsigned int last_rx_bd;
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	unsigned int link;
159*4882a593Smuzhiyun 	unsigned int duplex;
160*4882a593Smuzhiyun 	unsigned int speed;
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	unsigned int rx_missed_errors;
163*4882a593Smuzhiyun };
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun /**
166*4882a593Smuzhiyun  * arc_reg_set - Sets EMAC register with provided value.
167*4882a593Smuzhiyun  * @priv:	Pointer to ARC EMAC private data structure.
168*4882a593Smuzhiyun  * @reg:	Register offset from base address.
169*4882a593Smuzhiyun  * @value:	Value to set in register.
170*4882a593Smuzhiyun  */
arc_reg_set(struct arc_emac_priv * priv,int reg,int value)171*4882a593Smuzhiyun static inline void arc_reg_set(struct arc_emac_priv *priv, int reg, int value)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun 	iowrite32(value, priv->regs + reg * sizeof(int));
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun /**
177*4882a593Smuzhiyun  * arc_reg_get - Gets value of specified EMAC register.
178*4882a593Smuzhiyun  * @priv:	Pointer to ARC EMAC private data structure.
179*4882a593Smuzhiyun  * @reg:	Register offset from base address.
180*4882a593Smuzhiyun  *
181*4882a593Smuzhiyun  * returns:	Value of requested register.
182*4882a593Smuzhiyun  */
arc_reg_get(struct arc_emac_priv * priv,int reg)183*4882a593Smuzhiyun static inline unsigned int arc_reg_get(struct arc_emac_priv *priv, int reg)
184*4882a593Smuzhiyun {
185*4882a593Smuzhiyun 	return ioread32(priv->regs + reg * sizeof(int));
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun /**
189*4882a593Smuzhiyun  * arc_reg_or - Applies mask to specified EMAC register - ("reg" | "mask").
190*4882a593Smuzhiyun  * @priv:	Pointer to ARC EMAC private data structure.
191*4882a593Smuzhiyun  * @reg:	Register offset from base address.
192*4882a593Smuzhiyun  * @mask:	Mask to apply to specified register.
193*4882a593Smuzhiyun  *
194*4882a593Smuzhiyun  * This function reads initial register value, then applies provided mask
195*4882a593Smuzhiyun  * to it and then writes register back.
196*4882a593Smuzhiyun  */
arc_reg_or(struct arc_emac_priv * priv,int reg,int mask)197*4882a593Smuzhiyun static inline void arc_reg_or(struct arc_emac_priv *priv, int reg, int mask)
198*4882a593Smuzhiyun {
199*4882a593Smuzhiyun 	unsigned int value = arc_reg_get(priv, reg);
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 	arc_reg_set(priv, reg, value | mask);
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun /**
205*4882a593Smuzhiyun  * arc_reg_clr - Applies mask to specified EMAC register - ("reg" & ~"mask").
206*4882a593Smuzhiyun  * @priv:	Pointer to ARC EMAC private data structure.
207*4882a593Smuzhiyun  * @reg:	Register offset from base address.
208*4882a593Smuzhiyun  * @mask:	Mask to apply to specified register.
209*4882a593Smuzhiyun  *
210*4882a593Smuzhiyun  * This function reads initial register value, then applies provided mask
211*4882a593Smuzhiyun  * to it and then writes register back.
212*4882a593Smuzhiyun  */
arc_reg_clr(struct arc_emac_priv * priv,int reg,int mask)213*4882a593Smuzhiyun static inline void arc_reg_clr(struct arc_emac_priv *priv, int reg, int mask)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun 	unsigned int value = arc_reg_get(priv, reg);
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 	arc_reg_set(priv, reg, value & ~mask);
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun int arc_mdio_probe(struct arc_emac_priv *priv);
221*4882a593Smuzhiyun int arc_mdio_remove(struct arc_emac_priv *priv);
222*4882a593Smuzhiyun int arc_emac_probe(struct net_device *ndev, int interface);
223*4882a593Smuzhiyun int arc_emac_remove(struct net_device *ndev);
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun #endif /* ARC_EMAC_H */
226