1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* Atlantic Network Driver 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2018-2019 aQuantia Corporation 5*4882a593Smuzhiyun * Copyright (C) 2019-2020 Marvell International Ltd. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef AQ_PHY_H 9*4882a593Smuzhiyun #define AQ_PHY_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/mdio.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include "hw_atl/hw_atl_llh.h" 14*4882a593Smuzhiyun #include "hw_atl/hw_atl_llh_internal.h" 15*4882a593Smuzhiyun #include "aq_hw_utils.h" 16*4882a593Smuzhiyun #include "aq_hw.h" 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define HW_ATL_PHY_ID_MAX 32U 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun bool aq_mdio_busy_wait(struct aq_hw_s *aq_hw); 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun u16 aq_mdio_read_word(struct aq_hw_s *aq_hw, u16 mmd, u16 addr); 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun void aq_mdio_write_word(struct aq_hw_s *aq_hw, u16 mmd, u16 addr, u16 data); 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun u16 aq_phy_read_reg(struct aq_hw_s *aq_hw, u16 mmd, u16 address); 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun void aq_phy_write_reg(struct aq_hw_s *aq_hw, u16 mmd, u16 address, u16 data); 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun bool aq_phy_init_phy_id(struct aq_hw_s *aq_hw); 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun bool aq_phy_init(struct aq_hw_s *aq_hw); 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun void aq_phy_disable_ptp(struct aq_hw_s *aq_hw); 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #endif /* AQ_PHY_H */ 37