1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * aQuantia Corporation Network Driver 4*4882a593Smuzhiyun * Copyright (C) 2014-2019 aQuantia Corporation. All rights reserved 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* File aq_cfg.h: Definition of configuration parameters and constants. */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef AQ_CFG_H 10*4882a593Smuzhiyun #define AQ_CFG_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define AQ_CFG_VECS_DEF 8U 13*4882a593Smuzhiyun #define AQ_CFG_TCS_DEF 1U 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define AQ_CFG_TXDS_DEF 4096U 16*4882a593Smuzhiyun #define AQ_CFG_RXDS_DEF 2048U 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define AQ_CFG_IS_POLLING_DEF 0U 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define AQ_CFG_FORCE_LEGACY_INT 0U 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define AQ_CFG_INTERRUPT_MODERATION_OFF 0 23*4882a593Smuzhiyun #define AQ_CFG_INTERRUPT_MODERATION_ON 1 24*4882a593Smuzhiyun #define AQ_CFG_INTERRUPT_MODERATION_AUTO 0xFFFFU 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define AQ_CFG_INTERRUPT_MODERATION_USEC_MAX (0x1FF * 2) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define AQ_CFG_IRQ_MASK 0x3FFU 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define AQ_CFG_VECS_MAX 8U 31*4882a593Smuzhiyun #define AQ_CFG_TCS_MAX 8U 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define AQ_CFG_TX_FRAME_MAX (16U * 1024U) 34*4882a593Smuzhiyun #define AQ_CFG_RX_FRAME_MAX (2U * 1024U) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define AQ_CFG_TX_CLEAN_BUDGET 256U 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define AQ_CFG_RX_REFILL_THRES 32U 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define AQ_CFG_RX_HDR_SIZE 256U 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define AQ_CFG_RX_PAGEORDER 0U 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* LRO */ 45*4882a593Smuzhiyun #define AQ_CFG_IS_LRO_DEF 1U 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* RSS */ 48*4882a593Smuzhiyun #define AQ_CFG_RSS_INDIRECTION_TABLE_MAX 64U 49*4882a593Smuzhiyun #define AQ_CFG_RSS_HASHKEY_SIZE 40U 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define AQ_CFG_IS_RSS_DEF 1U 52*4882a593Smuzhiyun #define AQ_CFG_NUM_RSS_QUEUES_DEF AQ_CFG_VECS_DEF 53*4882a593Smuzhiyun #define AQ_CFG_RSS_BASE_CPU_NUM_DEF 0U 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define AQ_CFG_PCI_FUNC_MSIX_IRQS 9U 56*4882a593Smuzhiyun #define AQ_CFG_PCI_FUNC_PORTS 2U 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define AQ_CFG_SERVICE_TIMER_INTERVAL (1 * HZ) 59*4882a593Smuzhiyun #define AQ_CFG_POLLING_TIMER_INTERVAL ((unsigned int)(2 * HZ)) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define AQ_CFG_SKB_FRAGS_MAX 32U 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* Number of descriptors available in one ring to resume this ring queue 64*4882a593Smuzhiyun */ 65*4882a593Smuzhiyun #define AQ_CFG_RESTART_DESC_THRES (AQ_CFG_SKB_FRAGS_MAX * 2) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define AQ_CFG_NAPI_WEIGHT 64U 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /*#define AQ_CFG_MAC_ADDR_PERMANENT {0x30, 0x0E, 0xE3, 0x12, 0x34, 0x56}*/ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define AQ_CFG_FC_MODE AQ_NIC_FC_FULL 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* Default WOL modes used on initialization */ 74*4882a593Smuzhiyun #define AQ_CFG_WOL_MODES WAKE_MAGIC 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define AQ_CFG_SPEED_MSK 0xFFFFU /* 0xFFFFU==auto_neg */ 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define AQ_CFG_IS_AUTONEG_DEF 1U 79*4882a593Smuzhiyun #define AQ_CFG_MTU_DEF 1514U 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define AQ_CFG_LOCK_TRYS 100U 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define AQ_CFG_DRV_AUTHOR "Marvell" 84*4882a593Smuzhiyun #define AQ_CFG_DRV_DESC "Marvell (Aquantia) Corporation(R) Network Driver" 85*4882a593Smuzhiyun #define AQ_CFG_DRV_NAME "atlantic" 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #endif /* AQ_CFG_H */ 88