xref: /OK3568_Linux_fs/kernel/drivers/net/ethernet/apm/xgene-v2/ring.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Applied Micro X-Gene SoC Ethernet v2 Driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2017, Applied Micro Circuits Corporation
6*4882a593Smuzhiyun  * Author(s): Iyappan Subramanian <isubramanian@apm.com>
7*4882a593Smuzhiyun  *	      Keyur Chudgar <kchudgar@apm.com>
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include "main.h"
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun /* create circular linked list of descriptors */
xge_setup_desc(struct xge_desc_ring * ring)13*4882a593Smuzhiyun void xge_setup_desc(struct xge_desc_ring *ring)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun 	struct xge_raw_desc *raw_desc;
16*4882a593Smuzhiyun 	dma_addr_t dma_h, next_dma;
17*4882a593Smuzhiyun 	u16 offset;
18*4882a593Smuzhiyun 	int i;
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun 	for (i = 0; i < XGENE_ENET_NUM_DESC; i++) {
21*4882a593Smuzhiyun 		raw_desc = &ring->raw_desc[i];
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun 		offset = (i + 1) & (XGENE_ENET_NUM_DESC - 1);
24*4882a593Smuzhiyun 		next_dma = ring->dma_addr + (offset * XGENE_ENET_DESC_SIZE);
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun 		raw_desc->m0 = cpu_to_le64(SET_BITS(E, 1) |
27*4882a593Smuzhiyun 					   SET_BITS(PKT_SIZE, SLOT_EMPTY));
28*4882a593Smuzhiyun 		dma_h = upper_32_bits(next_dma);
29*4882a593Smuzhiyun 		raw_desc->m1 = cpu_to_le64(SET_BITS(NEXT_DESC_ADDRL, next_dma) |
30*4882a593Smuzhiyun 					   SET_BITS(NEXT_DESC_ADDRH, dma_h));
31*4882a593Smuzhiyun 	}
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun 
xge_update_tx_desc_addr(struct xge_pdata * pdata)34*4882a593Smuzhiyun void xge_update_tx_desc_addr(struct xge_pdata *pdata)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun 	struct xge_desc_ring *ring = pdata->tx_ring;
37*4882a593Smuzhiyun 	dma_addr_t dma_addr = ring->dma_addr;
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun 	xge_wr_csr(pdata, DMATXDESCL, dma_addr);
40*4882a593Smuzhiyun 	xge_wr_csr(pdata, DMATXDESCH, upper_32_bits(dma_addr));
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun 	ring->head = 0;
43*4882a593Smuzhiyun 	ring->tail = 0;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun 
xge_update_rx_desc_addr(struct xge_pdata * pdata)46*4882a593Smuzhiyun void xge_update_rx_desc_addr(struct xge_pdata *pdata)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun 	struct xge_desc_ring *ring = pdata->rx_ring;
49*4882a593Smuzhiyun 	dma_addr_t dma_addr = ring->dma_addr;
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun 	xge_wr_csr(pdata, DMARXDESCL, dma_addr);
52*4882a593Smuzhiyun 	xge_wr_csr(pdata, DMARXDESCH, upper_32_bits(dma_addr));
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 	ring->head = 0;
55*4882a593Smuzhiyun 	ring->tail = 0;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun 
xge_intr_enable(struct xge_pdata * pdata)58*4882a593Smuzhiyun void xge_intr_enable(struct xge_pdata *pdata)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun 	u32 data;
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	data = RX_PKT_RCVD | TX_PKT_SENT;
63*4882a593Smuzhiyun 	xge_wr_csr(pdata, DMAINTRMASK, data);
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun 
xge_intr_disable(struct xge_pdata * pdata)66*4882a593Smuzhiyun void xge_intr_disable(struct xge_pdata *pdata)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun 	xge_wr_csr(pdata, DMAINTRMASK, 0);
69*4882a593Smuzhiyun }
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