1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Applied Micro X-Gene SoC Ethernet v2 Driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2017, Applied Micro Circuits Corporation
6*4882a593Smuzhiyun * Author(s): Iyappan Subramanian <isubramanian@apm.com>
7*4882a593Smuzhiyun * Keyur Chudgar <kchudgar@apm.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #ifndef __XGENE_ENET_V2_MAC_H__
11*4882a593Smuzhiyun #define __XGENE_ENET_V2_MAC_H__
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun /* Register offsets */
14*4882a593Smuzhiyun #define MAC_CONFIG_1 0xa000
15*4882a593Smuzhiyun #define MAC_CONFIG_2 0xa004
16*4882a593Smuzhiyun #define MII_MGMT_CONFIG 0xa020
17*4882a593Smuzhiyun #define MII_MGMT_COMMAND 0xa024
18*4882a593Smuzhiyun #define MII_MGMT_ADDRESS 0xa028
19*4882a593Smuzhiyun #define MII_MGMT_CONTROL 0xa02c
20*4882a593Smuzhiyun #define MII_MGMT_STATUS 0xa030
21*4882a593Smuzhiyun #define MII_MGMT_INDICATORS 0xa034
22*4882a593Smuzhiyun #define INTERFACE_CONTROL 0xa038
23*4882a593Smuzhiyun #define STATION_ADDR0 0xa040
24*4882a593Smuzhiyun #define STATION_ADDR1 0xa044
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define RGMII_REG_0 0x27e0
27*4882a593Smuzhiyun #define ICM_CONFIG0_REG_0 0x2c00
28*4882a593Smuzhiyun #define ICM_CONFIG2_REG_0 0x2c08
29*4882a593Smuzhiyun #define ECM_CONFIG0_REG_0 0x2d00
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* Register fields */
32*4882a593Smuzhiyun #define SOFT_RESET BIT(31)
33*4882a593Smuzhiyun #define TX_EN BIT(0)
34*4882a593Smuzhiyun #define RX_EN BIT(2)
35*4882a593Smuzhiyun #define PAD_CRC BIT(2)
36*4882a593Smuzhiyun #define CRC_EN BIT(1)
37*4882a593Smuzhiyun #define FULL_DUPLEX BIT(0)
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define INTF_MODE_POS 8
40*4882a593Smuzhiyun #define INTF_MODE_LEN 2
41*4882a593Smuzhiyun #define HD_MODE_POS 25
42*4882a593Smuzhiyun #define HD_MODE_LEN 2
43*4882a593Smuzhiyun #define CFG_MACMODE_POS 18
44*4882a593Smuzhiyun #define CFG_MACMODE_LEN 2
45*4882a593Smuzhiyun #define CFG_WAITASYNCRD_POS 0
46*4882a593Smuzhiyun #define CFG_WAITASYNCRD_LEN 16
47*4882a593Smuzhiyun #define CFG_SPEED_125_POS 24
48*4882a593Smuzhiyun #define CFG_WFIFOFULLTHR_POS 0
49*4882a593Smuzhiyun #define CFG_WFIFOFULLTHR_LEN 7
50*4882a593Smuzhiyun #define MGMT_CLOCK_SEL_POS 0
51*4882a593Smuzhiyun #define MGMT_CLOCK_SEL_LEN 3
52*4882a593Smuzhiyun #define PHY_ADDR_POS 8
53*4882a593Smuzhiyun #define PHY_ADDR_LEN 5
54*4882a593Smuzhiyun #define REG_ADDR_POS 0
55*4882a593Smuzhiyun #define REG_ADDR_LEN 5
56*4882a593Smuzhiyun #define MII_MGMT_BUSY BIT(0)
57*4882a593Smuzhiyun #define MII_READ_CYCLE BIT(0)
58*4882a593Smuzhiyun #define CFG_WAITASYNCRD_EN BIT(16)
59*4882a593Smuzhiyun
xgene_set_reg_bits(u32 * var,int pos,int len,u32 val)60*4882a593Smuzhiyun static inline void xgene_set_reg_bits(u32 *var, int pos, int len, u32 val)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun u32 mask = GENMASK(pos + len, pos);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun *var &= ~mask;
65*4882a593Smuzhiyun *var |= ((val << pos) & mask);
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
xgene_get_reg_bits(u32 var,int pos,int len)68*4882a593Smuzhiyun static inline u32 xgene_get_reg_bits(u32 var, int pos, int len)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun u32 mask = GENMASK(pos + len, pos);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun return (var & mask) >> pos;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun #define SET_REG_BITS(var, field, val) \
76*4882a593Smuzhiyun xgene_set_reg_bits(var, field ## _POS, field ## _LEN, val)
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun #define SET_REG_BIT(var, field, val) \
79*4882a593Smuzhiyun xgene_set_reg_bits(var, field ## _POS, 1, val)
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun #define GET_REG_BITS(var, field) \
82*4882a593Smuzhiyun xgene_get_reg_bits(var, field ## _POS, field ## _LEN)
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun #define GET_REG_BIT(var, field) ((var) & (field))
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun struct xge_pdata;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun void xge_mac_reset(struct xge_pdata *pdata);
89*4882a593Smuzhiyun void xge_mac_set_speed(struct xge_pdata *pdata);
90*4882a593Smuzhiyun void xge_mac_enable(struct xge_pdata *pdata);
91*4882a593Smuzhiyun void xge_mac_disable(struct xge_pdata *pdata);
92*4882a593Smuzhiyun void xge_mac_init(struct xge_pdata *pdata);
93*4882a593Smuzhiyun void xge_mac_set_station_addr(struct xge_pdata *pdata);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun #endif /* __XGENE_ENET_V2_MAC_H__ */
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