1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Applied Micro X-Gene SoC Ethernet v2 Driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2017, Applied Micro Circuits Corporation 6*4882a593Smuzhiyun * Author(s): Iyappan Subramanian <isubramanian@apm.com> 7*4882a593Smuzhiyun * Keyur Chudgar <kchudgar@apm.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __XGENE_ENET_V2_ENET_H__ 11*4882a593Smuzhiyun #define __XGENE_ENET_V2_ENET_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define ENET_CLKEN 0xc008 14*4882a593Smuzhiyun #define ENET_SRST 0xc000 15*4882a593Smuzhiyun #define ENET_SHIM 0xc010 16*4882a593Smuzhiyun #define CFG_MEM_RAM_SHUTDOWN 0xd070 17*4882a593Smuzhiyun #define BLOCK_MEM_RDY 0xd074 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define MEM_RDY 0xffffffff 20*4882a593Smuzhiyun #define DEVM_ARAUX_COH BIT(19) 21*4882a593Smuzhiyun #define DEVM_AWAUX_COH BIT(3) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define CFG_FORCE_LINK_STATUS_EN 0x229c 24*4882a593Smuzhiyun #define FORCE_LINK_STATUS 0x22a0 25*4882a593Smuzhiyun #define CFG_LINK_AGGR_RESUME 0x27c8 26*4882a593Smuzhiyun #define RX_DV_GATE_REG 0x2dfc 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun void xge_wr_csr(struct xge_pdata *pdata, u32 offset, u32 val); 29*4882a593Smuzhiyun u32 xge_rd_csr(struct xge_pdata *pdata, u32 offset); 30*4882a593Smuzhiyun int xge_port_reset(struct net_device *ndev); 31*4882a593Smuzhiyun void xge_port_init(struct net_device *ndev); 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #endif /* __XGENE_ENET_V2_ENET__H__ */ 34