1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /* $Id: sunlance.c,v 1.112 2002/01/15 06:48:55 davem Exp $
3*4882a593Smuzhiyun * lance.c: Linux/Sparc/Lance driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Written 1995, 1996 by Miguel de Icaza
6*4882a593Smuzhiyun * Sources:
7*4882a593Smuzhiyun * The Linux depca driver
8*4882a593Smuzhiyun * The Linux lance driver.
9*4882a593Smuzhiyun * The Linux skeleton driver.
10*4882a593Smuzhiyun * The NetBSD Sparc/Lance driver.
11*4882a593Smuzhiyun * Theo de Raadt (deraadt@openbsd.org)
12*4882a593Smuzhiyun * NCR92C990 Lan Controller manual
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * 1.4:
15*4882a593Smuzhiyun * Added support to run with a ledma on the Sun4m
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun * 1.5:
18*4882a593Smuzhiyun * Added multiple card detection.
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * 4/17/96: Burst sizes and tpe selection on sun4m by Eddie C. Dost
21*4882a593Smuzhiyun * (ecd@skynet.be)
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * 5/15/96: auto carrier detection on sun4m by Eddie C. Dost
24*4882a593Smuzhiyun * (ecd@skynet.be)
25*4882a593Smuzhiyun *
26*4882a593Smuzhiyun * 5/17/96: lebuffer on scsi/ether cards now work David S. Miller
27*4882a593Smuzhiyun * (davem@caip.rutgers.edu)
28*4882a593Smuzhiyun *
29*4882a593Smuzhiyun * 5/29/96: override option 'tpe-link-test?', if it is 'false', as
30*4882a593Smuzhiyun * this disables auto carrier detection on sun4m. Eddie C. Dost
31*4882a593Smuzhiyun * (ecd@skynet.be)
32*4882a593Smuzhiyun *
33*4882a593Smuzhiyun * 1.7:
34*4882a593Smuzhiyun * 6/26/96: Bug fix for multiple ledmas, miguel.
35*4882a593Smuzhiyun *
36*4882a593Smuzhiyun * 1.8:
37*4882a593Smuzhiyun * Stole multicast code from depca.c, fixed lance_tx.
38*4882a593Smuzhiyun *
39*4882a593Smuzhiyun * 1.9:
40*4882a593Smuzhiyun * 8/21/96: Fixed the multicast code (Pedro Roque)
41*4882a593Smuzhiyun *
42*4882a593Smuzhiyun * 8/28/96: Send fake packet in lance_open() if auto_select is true,
43*4882a593Smuzhiyun * so we can detect the carrier loss condition in time.
44*4882a593Smuzhiyun * Eddie C. Dost (ecd@skynet.be)
45*4882a593Smuzhiyun *
46*4882a593Smuzhiyun * 9/15/96: Align rx_buf so that eth_copy_and_sum() won't cause an
47*4882a593Smuzhiyun * MNA trap during chksum_partial_copy(). (ecd@skynet.be)
48*4882a593Smuzhiyun *
49*4882a593Smuzhiyun * 11/17/96: Handle LE_C0_MERR in lance_interrupt(). (ecd@skynet.be)
50*4882a593Smuzhiyun *
51*4882a593Smuzhiyun * 12/22/96: Don't loop forever in lance_rx() on incomplete packets.
52*4882a593Smuzhiyun * This was the sun4c killer. Shit, stupid bug.
53*4882a593Smuzhiyun * (ecd@skynet.be)
54*4882a593Smuzhiyun *
55*4882a593Smuzhiyun * 1.10:
56*4882a593Smuzhiyun * 1/26/97: Modularize driver. (ecd@skynet.be)
57*4882a593Smuzhiyun *
58*4882a593Smuzhiyun * 1.11:
59*4882a593Smuzhiyun * 12/27/97: Added sun4d support. (jj@sunsite.mff.cuni.cz)
60*4882a593Smuzhiyun *
61*4882a593Smuzhiyun * 1.12:
62*4882a593Smuzhiyun * 11/3/99: Fixed SMP race in lance_start_xmit found by davem.
63*4882a593Smuzhiyun * Anton Blanchard (anton@progsoc.uts.edu.au)
64*4882a593Smuzhiyun * 2.00: 11/9/99: Massive overhaul and port to new SBUS driver interfaces.
65*4882a593Smuzhiyun * David S. Miller (davem@redhat.com)
66*4882a593Smuzhiyun * 2.01:
67*4882a593Smuzhiyun * 11/08/01: Use library crc32 functions (Matt_Domsch@dell.com)
68*4882a593Smuzhiyun *
69*4882a593Smuzhiyun */
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun #undef DEBUG_DRIVER
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun static char lancestr[] = "LANCE";
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun #include <linux/module.h>
76*4882a593Smuzhiyun #include <linux/kernel.h>
77*4882a593Smuzhiyun #include <linux/types.h>
78*4882a593Smuzhiyun #include <linux/fcntl.h>
79*4882a593Smuzhiyun #include <linux/interrupt.h>
80*4882a593Smuzhiyun #include <linux/ioport.h>
81*4882a593Smuzhiyun #include <linux/in.h>
82*4882a593Smuzhiyun #include <linux/string.h>
83*4882a593Smuzhiyun #include <linux/delay.h>
84*4882a593Smuzhiyun #include <linux/crc32.h>
85*4882a593Smuzhiyun #include <linux/errno.h>
86*4882a593Smuzhiyun #include <linux/socket.h> /* Used for the temporal inet entries and routing */
87*4882a593Smuzhiyun #include <linux/route.h>
88*4882a593Smuzhiyun #include <linux/netdevice.h>
89*4882a593Smuzhiyun #include <linux/etherdevice.h>
90*4882a593Smuzhiyun #include <linux/skbuff.h>
91*4882a593Smuzhiyun #include <linux/ethtool.h>
92*4882a593Smuzhiyun #include <linux/bitops.h>
93*4882a593Smuzhiyun #include <linux/dma-mapping.h>
94*4882a593Smuzhiyun #include <linux/of.h>
95*4882a593Smuzhiyun #include <linux/of_device.h>
96*4882a593Smuzhiyun #include <linux/gfp.h>
97*4882a593Smuzhiyun #include <linux/pgtable.h>
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun #include <asm/io.h>
100*4882a593Smuzhiyun #include <asm/dma.h>
101*4882a593Smuzhiyun #include <asm/byteorder.h> /* Used by the checksum routines */
102*4882a593Smuzhiyun #include <asm/idprom.h>
103*4882a593Smuzhiyun #include <asm/prom.h>
104*4882a593Smuzhiyun #include <asm/auxio.h> /* For tpe-link-test? setting */
105*4882a593Smuzhiyun #include <asm/irq.h>
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun #define DRV_NAME "sunlance"
108*4882a593Smuzhiyun #define DRV_RELDATE "8/24/03"
109*4882a593Smuzhiyun #define DRV_AUTHOR "Miguel de Icaza (miguel@nuclecu.unam.mx)"
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun MODULE_AUTHOR(DRV_AUTHOR);
112*4882a593Smuzhiyun MODULE_DESCRIPTION("Sun Lance ethernet driver");
113*4882a593Smuzhiyun MODULE_LICENSE("GPL");
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun /* Define: 2^4 Tx buffers and 2^4 Rx buffers */
116*4882a593Smuzhiyun #ifndef LANCE_LOG_TX_BUFFERS
117*4882a593Smuzhiyun #define LANCE_LOG_TX_BUFFERS 4
118*4882a593Smuzhiyun #define LANCE_LOG_RX_BUFFERS 4
119*4882a593Smuzhiyun #endif
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun #define LE_CSR0 0
122*4882a593Smuzhiyun #define LE_CSR1 1
123*4882a593Smuzhiyun #define LE_CSR2 2
124*4882a593Smuzhiyun #define LE_CSR3 3
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun #define LE_MO_PROM 0x8000 /* Enable promiscuous mode */
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun #define LE_C0_ERR 0x8000 /* Error: set if BAB, SQE, MISS or ME is set */
129*4882a593Smuzhiyun #define LE_C0_BABL 0x4000 /* BAB: Babble: tx timeout. */
130*4882a593Smuzhiyun #define LE_C0_CERR 0x2000 /* SQE: Signal quality error */
131*4882a593Smuzhiyun #define LE_C0_MISS 0x1000 /* MISS: Missed a packet */
132*4882a593Smuzhiyun #define LE_C0_MERR 0x0800 /* ME: Memory error */
133*4882a593Smuzhiyun #define LE_C0_RINT 0x0400 /* Received interrupt */
134*4882a593Smuzhiyun #define LE_C0_TINT 0x0200 /* Transmitter Interrupt */
135*4882a593Smuzhiyun #define LE_C0_IDON 0x0100 /* IFIN: Init finished. */
136*4882a593Smuzhiyun #define LE_C0_INTR 0x0080 /* Interrupt or error */
137*4882a593Smuzhiyun #define LE_C0_INEA 0x0040 /* Interrupt enable */
138*4882a593Smuzhiyun #define LE_C0_RXON 0x0020 /* Receiver on */
139*4882a593Smuzhiyun #define LE_C0_TXON 0x0010 /* Transmitter on */
140*4882a593Smuzhiyun #define LE_C0_TDMD 0x0008 /* Transmitter demand */
141*4882a593Smuzhiyun #define LE_C0_STOP 0x0004 /* Stop the card */
142*4882a593Smuzhiyun #define LE_C0_STRT 0x0002 /* Start the card */
143*4882a593Smuzhiyun #define LE_C0_INIT 0x0001 /* Init the card */
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun #define LE_C3_BSWP 0x4 /* SWAP */
146*4882a593Smuzhiyun #define LE_C3_ACON 0x2 /* ALE Control */
147*4882a593Smuzhiyun #define LE_C3_BCON 0x1 /* Byte control */
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun /* Receive message descriptor 1 */
150*4882a593Smuzhiyun #define LE_R1_OWN 0x80 /* Who owns the entry */
151*4882a593Smuzhiyun #define LE_R1_ERR 0x40 /* Error: if FRA, OFL, CRC or BUF is set */
152*4882a593Smuzhiyun #define LE_R1_FRA 0x20 /* FRA: Frame error */
153*4882a593Smuzhiyun #define LE_R1_OFL 0x10 /* OFL: Frame overflow */
154*4882a593Smuzhiyun #define LE_R1_CRC 0x08 /* CRC error */
155*4882a593Smuzhiyun #define LE_R1_BUF 0x04 /* BUF: Buffer error */
156*4882a593Smuzhiyun #define LE_R1_SOP 0x02 /* Start of packet */
157*4882a593Smuzhiyun #define LE_R1_EOP 0x01 /* End of packet */
158*4882a593Smuzhiyun #define LE_R1_POK 0x03 /* Packet is complete: SOP + EOP */
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun #define LE_T1_OWN 0x80 /* Lance owns the packet */
161*4882a593Smuzhiyun #define LE_T1_ERR 0x40 /* Error summary */
162*4882a593Smuzhiyun #define LE_T1_EMORE 0x10 /* Error: more than one retry needed */
163*4882a593Smuzhiyun #define LE_T1_EONE 0x08 /* Error: one retry needed */
164*4882a593Smuzhiyun #define LE_T1_EDEF 0x04 /* Error: deferred */
165*4882a593Smuzhiyun #define LE_T1_SOP 0x02 /* Start of packet */
166*4882a593Smuzhiyun #define LE_T1_EOP 0x01 /* End of packet */
167*4882a593Smuzhiyun #define LE_T1_POK 0x03 /* Packet is complete: SOP + EOP */
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun #define LE_T3_BUF 0x8000 /* Buffer error */
170*4882a593Smuzhiyun #define LE_T3_UFL 0x4000 /* Error underflow */
171*4882a593Smuzhiyun #define LE_T3_LCOL 0x1000 /* Error late collision */
172*4882a593Smuzhiyun #define LE_T3_CLOS 0x0800 /* Error carrier loss */
173*4882a593Smuzhiyun #define LE_T3_RTY 0x0400 /* Error retry */
174*4882a593Smuzhiyun #define LE_T3_TDR 0x03ff /* Time Domain Reflectometry counter */
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun #define TX_RING_SIZE (1 << (LANCE_LOG_TX_BUFFERS))
177*4882a593Smuzhiyun #define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
178*4882a593Smuzhiyun #define TX_RING_LEN_BITS ((LANCE_LOG_TX_BUFFERS) << 29)
179*4882a593Smuzhiyun #define TX_NEXT(__x) (((__x)+1) & TX_RING_MOD_MASK)
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun #define RX_RING_SIZE (1 << (LANCE_LOG_RX_BUFFERS))
182*4882a593Smuzhiyun #define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
183*4882a593Smuzhiyun #define RX_RING_LEN_BITS ((LANCE_LOG_RX_BUFFERS) << 29)
184*4882a593Smuzhiyun #define RX_NEXT(__x) (((__x)+1) & RX_RING_MOD_MASK)
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun #define PKT_BUF_SZ 1544
187*4882a593Smuzhiyun #define RX_BUFF_SIZE PKT_BUF_SZ
188*4882a593Smuzhiyun #define TX_BUFF_SIZE PKT_BUF_SZ
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun struct lance_rx_desc {
191*4882a593Smuzhiyun u16 rmd0; /* low address of packet */
192*4882a593Smuzhiyun u8 rmd1_bits; /* descriptor bits */
193*4882a593Smuzhiyun u8 rmd1_hadr; /* high address of packet */
194*4882a593Smuzhiyun s16 length; /* This length is 2s complement (negative)!
195*4882a593Smuzhiyun * Buffer length
196*4882a593Smuzhiyun */
197*4882a593Smuzhiyun u16 mblength; /* This is the actual number of bytes received */
198*4882a593Smuzhiyun };
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun struct lance_tx_desc {
201*4882a593Smuzhiyun u16 tmd0; /* low address of packet */
202*4882a593Smuzhiyun u8 tmd1_bits; /* descriptor bits */
203*4882a593Smuzhiyun u8 tmd1_hadr; /* high address of packet */
204*4882a593Smuzhiyun s16 length; /* Length is 2s complement (negative)! */
205*4882a593Smuzhiyun u16 misc;
206*4882a593Smuzhiyun };
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun /* The LANCE initialization block, described in databook. */
209*4882a593Smuzhiyun /* On the Sparc, this block should be on a DMA region */
210*4882a593Smuzhiyun struct lance_init_block {
211*4882a593Smuzhiyun u16 mode; /* Pre-set mode (reg. 15) */
212*4882a593Smuzhiyun u8 phys_addr[6]; /* Physical ethernet address */
213*4882a593Smuzhiyun u32 filter[2]; /* Multicast filter. */
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun /* Receive and transmit ring base, along with extra bits. */
216*4882a593Smuzhiyun u16 rx_ptr; /* receive descriptor addr */
217*4882a593Smuzhiyun u16 rx_len; /* receive len and high addr */
218*4882a593Smuzhiyun u16 tx_ptr; /* transmit descriptor addr */
219*4882a593Smuzhiyun u16 tx_len; /* transmit len and high addr */
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun /* The Tx and Rx ring entries must aligned on 8-byte boundaries. */
222*4882a593Smuzhiyun struct lance_rx_desc brx_ring[RX_RING_SIZE];
223*4882a593Smuzhiyun struct lance_tx_desc btx_ring[TX_RING_SIZE];
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun u8 tx_buf [TX_RING_SIZE][TX_BUFF_SIZE];
226*4882a593Smuzhiyun u8 pad[2]; /* align rx_buf for copy_and_sum(). */
227*4882a593Smuzhiyun u8 rx_buf [RX_RING_SIZE][RX_BUFF_SIZE];
228*4882a593Smuzhiyun };
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun #define libdesc_offset(rt, elem) \
231*4882a593Smuzhiyun ((__u32)(((unsigned long)(&(((struct lance_init_block *)0)->rt[elem])))))
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun #define libbuff_offset(rt, elem) \
234*4882a593Smuzhiyun ((__u32)(((unsigned long)(&(((struct lance_init_block *)0)->rt[elem][0])))))
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun struct lance_private {
237*4882a593Smuzhiyun void __iomem *lregs; /* Lance RAP/RDP regs. */
238*4882a593Smuzhiyun void __iomem *dregs; /* DMA controller regs. */
239*4882a593Smuzhiyun struct lance_init_block __iomem *init_block_iomem;
240*4882a593Smuzhiyun struct lance_init_block *init_block_mem;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun spinlock_t lock;
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun int rx_new, tx_new;
245*4882a593Smuzhiyun int rx_old, tx_old;
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun struct platform_device *ledma; /* If set this points to ledma */
248*4882a593Smuzhiyun char tpe; /* cable-selection is TPE */
249*4882a593Smuzhiyun char auto_select; /* cable-selection by carrier */
250*4882a593Smuzhiyun char burst_sizes; /* ledma SBus burst sizes */
251*4882a593Smuzhiyun char pio_buffer; /* init block in PIO space? */
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun unsigned short busmaster_regval;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun void (*init_ring)(struct net_device *);
256*4882a593Smuzhiyun void (*rx)(struct net_device *);
257*4882a593Smuzhiyun void (*tx)(struct net_device *);
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun char *name;
260*4882a593Smuzhiyun dma_addr_t init_block_dvma;
261*4882a593Smuzhiyun struct net_device *dev; /* Backpointer */
262*4882a593Smuzhiyun struct platform_device *op;
263*4882a593Smuzhiyun struct platform_device *lebuffer;
264*4882a593Smuzhiyun struct timer_list multicast_timer;
265*4882a593Smuzhiyun };
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
268*4882a593Smuzhiyun lp->tx_old+TX_RING_MOD_MASK-lp->tx_new:\
269*4882a593Smuzhiyun lp->tx_old - lp->tx_new-1)
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun /* Lance registers. */
272*4882a593Smuzhiyun #define RDP 0x00UL /* register data port */
273*4882a593Smuzhiyun #define RAP 0x02UL /* register address port */
274*4882a593Smuzhiyun #define LANCE_REG_SIZE 0x04UL
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun #define STOP_LANCE(__lp) \
277*4882a593Smuzhiyun do { void __iomem *__base = (__lp)->lregs; \
278*4882a593Smuzhiyun sbus_writew(LE_CSR0, __base + RAP); \
279*4882a593Smuzhiyun sbus_writew(LE_C0_STOP, __base + RDP); \
280*4882a593Smuzhiyun } while (0)
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun int sparc_lance_debug = 2;
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun /* The Lance uses 24 bit addresses */
285*4882a593Smuzhiyun /* On the Sun4c the DVMA will provide the remaining bytes for us */
286*4882a593Smuzhiyun /* On the Sun4m we have to instruct the ledma to provide them */
287*4882a593Smuzhiyun /* Even worse, on scsi/ether SBUS cards, the init block and the
288*4882a593Smuzhiyun * transmit/receive buffers are addresses as offsets from absolute
289*4882a593Smuzhiyun * zero on the lebuffer PIO area. -DaveM
290*4882a593Smuzhiyun */
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun #define LANCE_ADDR(x) ((long)(x) & ~0xff000000)
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun /* Load the CSR registers */
load_csrs(struct lance_private * lp)295*4882a593Smuzhiyun static void load_csrs(struct lance_private *lp)
296*4882a593Smuzhiyun {
297*4882a593Smuzhiyun u32 leptr;
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun if (lp->pio_buffer)
300*4882a593Smuzhiyun leptr = 0;
301*4882a593Smuzhiyun else
302*4882a593Smuzhiyun leptr = LANCE_ADDR(lp->init_block_dvma);
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun sbus_writew(LE_CSR1, lp->lregs + RAP);
305*4882a593Smuzhiyun sbus_writew(leptr & 0xffff, lp->lregs + RDP);
306*4882a593Smuzhiyun sbus_writew(LE_CSR2, lp->lregs + RAP);
307*4882a593Smuzhiyun sbus_writew(leptr >> 16, lp->lregs + RDP);
308*4882a593Smuzhiyun sbus_writew(LE_CSR3, lp->lregs + RAP);
309*4882a593Smuzhiyun sbus_writew(lp->busmaster_regval, lp->lregs + RDP);
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun /* Point back to csr0 */
312*4882a593Smuzhiyun sbus_writew(LE_CSR0, lp->lregs + RAP);
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun /* Setup the Lance Rx and Tx rings */
lance_init_ring_dvma(struct net_device * dev)316*4882a593Smuzhiyun static void lance_init_ring_dvma(struct net_device *dev)
317*4882a593Smuzhiyun {
318*4882a593Smuzhiyun struct lance_private *lp = netdev_priv(dev);
319*4882a593Smuzhiyun struct lance_init_block *ib = lp->init_block_mem;
320*4882a593Smuzhiyun dma_addr_t aib = lp->init_block_dvma;
321*4882a593Smuzhiyun __u32 leptr;
322*4882a593Smuzhiyun int i;
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun /* Lock out other processes while setting up hardware */
325*4882a593Smuzhiyun netif_stop_queue(dev);
326*4882a593Smuzhiyun lp->rx_new = lp->tx_new = 0;
327*4882a593Smuzhiyun lp->rx_old = lp->tx_old = 0;
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun /* Copy the ethernet address to the lance init block
330*4882a593Smuzhiyun * Note that on the sparc you need to swap the ethernet address.
331*4882a593Smuzhiyun */
332*4882a593Smuzhiyun ib->phys_addr [0] = dev->dev_addr [1];
333*4882a593Smuzhiyun ib->phys_addr [1] = dev->dev_addr [0];
334*4882a593Smuzhiyun ib->phys_addr [2] = dev->dev_addr [3];
335*4882a593Smuzhiyun ib->phys_addr [3] = dev->dev_addr [2];
336*4882a593Smuzhiyun ib->phys_addr [4] = dev->dev_addr [5];
337*4882a593Smuzhiyun ib->phys_addr [5] = dev->dev_addr [4];
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun /* Setup the Tx ring entries */
340*4882a593Smuzhiyun for (i = 0; i < TX_RING_SIZE; i++) {
341*4882a593Smuzhiyun leptr = LANCE_ADDR(aib + libbuff_offset(tx_buf, i));
342*4882a593Smuzhiyun ib->btx_ring [i].tmd0 = leptr;
343*4882a593Smuzhiyun ib->btx_ring [i].tmd1_hadr = leptr >> 16;
344*4882a593Smuzhiyun ib->btx_ring [i].tmd1_bits = 0;
345*4882a593Smuzhiyun ib->btx_ring [i].length = 0xf000; /* The ones required by tmd2 */
346*4882a593Smuzhiyun ib->btx_ring [i].misc = 0;
347*4882a593Smuzhiyun }
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun /* Setup the Rx ring entries */
350*4882a593Smuzhiyun for (i = 0; i < RX_RING_SIZE; i++) {
351*4882a593Smuzhiyun leptr = LANCE_ADDR(aib + libbuff_offset(rx_buf, i));
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun ib->brx_ring [i].rmd0 = leptr;
354*4882a593Smuzhiyun ib->brx_ring [i].rmd1_hadr = leptr >> 16;
355*4882a593Smuzhiyun ib->brx_ring [i].rmd1_bits = LE_R1_OWN;
356*4882a593Smuzhiyun ib->brx_ring [i].length = -RX_BUFF_SIZE | 0xf000;
357*4882a593Smuzhiyun ib->brx_ring [i].mblength = 0;
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun /* Setup the initialization block */
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun /* Setup rx descriptor pointer */
363*4882a593Smuzhiyun leptr = LANCE_ADDR(aib + libdesc_offset(brx_ring, 0));
364*4882a593Smuzhiyun ib->rx_len = (LANCE_LOG_RX_BUFFERS << 13) | (leptr >> 16);
365*4882a593Smuzhiyun ib->rx_ptr = leptr;
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun /* Setup tx descriptor pointer */
368*4882a593Smuzhiyun leptr = LANCE_ADDR(aib + libdesc_offset(btx_ring, 0));
369*4882a593Smuzhiyun ib->tx_len = (LANCE_LOG_TX_BUFFERS << 13) | (leptr >> 16);
370*4882a593Smuzhiyun ib->tx_ptr = leptr;
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun
lance_init_ring_pio(struct net_device * dev)373*4882a593Smuzhiyun static void lance_init_ring_pio(struct net_device *dev)
374*4882a593Smuzhiyun {
375*4882a593Smuzhiyun struct lance_private *lp = netdev_priv(dev);
376*4882a593Smuzhiyun struct lance_init_block __iomem *ib = lp->init_block_iomem;
377*4882a593Smuzhiyun u32 leptr;
378*4882a593Smuzhiyun int i;
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun /* Lock out other processes while setting up hardware */
381*4882a593Smuzhiyun netif_stop_queue(dev);
382*4882a593Smuzhiyun lp->rx_new = lp->tx_new = 0;
383*4882a593Smuzhiyun lp->rx_old = lp->tx_old = 0;
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun /* Copy the ethernet address to the lance init block
386*4882a593Smuzhiyun * Note that on the sparc you need to swap the ethernet address.
387*4882a593Smuzhiyun */
388*4882a593Smuzhiyun sbus_writeb(dev->dev_addr[1], &ib->phys_addr[0]);
389*4882a593Smuzhiyun sbus_writeb(dev->dev_addr[0], &ib->phys_addr[1]);
390*4882a593Smuzhiyun sbus_writeb(dev->dev_addr[3], &ib->phys_addr[2]);
391*4882a593Smuzhiyun sbus_writeb(dev->dev_addr[2], &ib->phys_addr[3]);
392*4882a593Smuzhiyun sbus_writeb(dev->dev_addr[5], &ib->phys_addr[4]);
393*4882a593Smuzhiyun sbus_writeb(dev->dev_addr[4], &ib->phys_addr[5]);
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun /* Setup the Tx ring entries */
396*4882a593Smuzhiyun for (i = 0; i < TX_RING_SIZE; i++) {
397*4882a593Smuzhiyun leptr = libbuff_offset(tx_buf, i);
398*4882a593Smuzhiyun sbus_writew(leptr, &ib->btx_ring [i].tmd0);
399*4882a593Smuzhiyun sbus_writeb(leptr >> 16,&ib->btx_ring [i].tmd1_hadr);
400*4882a593Smuzhiyun sbus_writeb(0, &ib->btx_ring [i].tmd1_bits);
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun /* The ones required by tmd2 */
403*4882a593Smuzhiyun sbus_writew(0xf000, &ib->btx_ring [i].length);
404*4882a593Smuzhiyun sbus_writew(0, &ib->btx_ring [i].misc);
405*4882a593Smuzhiyun }
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun /* Setup the Rx ring entries */
408*4882a593Smuzhiyun for (i = 0; i < RX_RING_SIZE; i++) {
409*4882a593Smuzhiyun leptr = libbuff_offset(rx_buf, i);
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun sbus_writew(leptr, &ib->brx_ring [i].rmd0);
412*4882a593Smuzhiyun sbus_writeb(leptr >> 16,&ib->brx_ring [i].rmd1_hadr);
413*4882a593Smuzhiyun sbus_writeb(LE_R1_OWN, &ib->brx_ring [i].rmd1_bits);
414*4882a593Smuzhiyun sbus_writew(-RX_BUFF_SIZE|0xf000,
415*4882a593Smuzhiyun &ib->brx_ring [i].length);
416*4882a593Smuzhiyun sbus_writew(0, &ib->brx_ring [i].mblength);
417*4882a593Smuzhiyun }
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun /* Setup the initialization block */
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun /* Setup rx descriptor pointer */
422*4882a593Smuzhiyun leptr = libdesc_offset(brx_ring, 0);
423*4882a593Smuzhiyun sbus_writew((LANCE_LOG_RX_BUFFERS << 13) | (leptr >> 16),
424*4882a593Smuzhiyun &ib->rx_len);
425*4882a593Smuzhiyun sbus_writew(leptr, &ib->rx_ptr);
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun /* Setup tx descriptor pointer */
428*4882a593Smuzhiyun leptr = libdesc_offset(btx_ring, 0);
429*4882a593Smuzhiyun sbus_writew((LANCE_LOG_TX_BUFFERS << 13) | (leptr >> 16),
430*4882a593Smuzhiyun &ib->tx_len);
431*4882a593Smuzhiyun sbus_writew(leptr, &ib->tx_ptr);
432*4882a593Smuzhiyun }
433*4882a593Smuzhiyun
init_restart_ledma(struct lance_private * lp)434*4882a593Smuzhiyun static void init_restart_ledma(struct lance_private *lp)
435*4882a593Smuzhiyun {
436*4882a593Smuzhiyun u32 csr = sbus_readl(lp->dregs + DMA_CSR);
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun if (!(csr & DMA_HNDL_ERROR)) {
439*4882a593Smuzhiyun /* E-Cache draining */
440*4882a593Smuzhiyun while (sbus_readl(lp->dregs + DMA_CSR) & DMA_FIFO_ISDRAIN)
441*4882a593Smuzhiyun barrier();
442*4882a593Smuzhiyun }
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun csr = sbus_readl(lp->dregs + DMA_CSR);
445*4882a593Smuzhiyun csr &= ~DMA_E_BURSTS;
446*4882a593Smuzhiyun if (lp->burst_sizes & DMA_BURST32)
447*4882a593Smuzhiyun csr |= DMA_E_BURST32;
448*4882a593Smuzhiyun else
449*4882a593Smuzhiyun csr |= DMA_E_BURST16;
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun csr |= (DMA_DSBL_RD_DRN | DMA_DSBL_WR_INV | DMA_FIFO_INV);
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun if (lp->tpe)
454*4882a593Smuzhiyun csr |= DMA_EN_ENETAUI;
455*4882a593Smuzhiyun else
456*4882a593Smuzhiyun csr &= ~DMA_EN_ENETAUI;
457*4882a593Smuzhiyun udelay(20);
458*4882a593Smuzhiyun sbus_writel(csr, lp->dregs + DMA_CSR);
459*4882a593Smuzhiyun udelay(200);
460*4882a593Smuzhiyun }
461*4882a593Smuzhiyun
init_restart_lance(struct lance_private * lp)462*4882a593Smuzhiyun static int init_restart_lance(struct lance_private *lp)
463*4882a593Smuzhiyun {
464*4882a593Smuzhiyun u16 regval = 0;
465*4882a593Smuzhiyun int i;
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun if (lp->dregs)
468*4882a593Smuzhiyun init_restart_ledma(lp);
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun sbus_writew(LE_CSR0, lp->lregs + RAP);
471*4882a593Smuzhiyun sbus_writew(LE_C0_INIT, lp->lregs + RDP);
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun /* Wait for the lance to complete initialization */
474*4882a593Smuzhiyun for (i = 0; i < 100; i++) {
475*4882a593Smuzhiyun regval = sbus_readw(lp->lregs + RDP);
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun if (regval & (LE_C0_ERR | LE_C0_IDON))
478*4882a593Smuzhiyun break;
479*4882a593Smuzhiyun barrier();
480*4882a593Smuzhiyun }
481*4882a593Smuzhiyun if (i == 100 || (regval & LE_C0_ERR)) {
482*4882a593Smuzhiyun printk(KERN_ERR "LANCE unopened after %d ticks, csr0=%4.4x.\n",
483*4882a593Smuzhiyun i, regval);
484*4882a593Smuzhiyun if (lp->dregs)
485*4882a593Smuzhiyun printk("dcsr=%8.8x\n", sbus_readl(lp->dregs + DMA_CSR));
486*4882a593Smuzhiyun return -1;
487*4882a593Smuzhiyun }
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun /* Clear IDON by writing a "1", enable interrupts and start lance */
490*4882a593Smuzhiyun sbus_writew(LE_C0_IDON, lp->lregs + RDP);
491*4882a593Smuzhiyun sbus_writew(LE_C0_INEA | LE_C0_STRT, lp->lregs + RDP);
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun if (lp->dregs) {
494*4882a593Smuzhiyun u32 csr = sbus_readl(lp->dregs + DMA_CSR);
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun csr |= DMA_INT_ENAB;
497*4882a593Smuzhiyun sbus_writel(csr, lp->dregs + DMA_CSR);
498*4882a593Smuzhiyun }
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun return 0;
501*4882a593Smuzhiyun }
502*4882a593Smuzhiyun
lance_rx_dvma(struct net_device * dev)503*4882a593Smuzhiyun static void lance_rx_dvma(struct net_device *dev)
504*4882a593Smuzhiyun {
505*4882a593Smuzhiyun struct lance_private *lp = netdev_priv(dev);
506*4882a593Smuzhiyun struct lance_init_block *ib = lp->init_block_mem;
507*4882a593Smuzhiyun struct lance_rx_desc *rd;
508*4882a593Smuzhiyun u8 bits;
509*4882a593Smuzhiyun int len, entry = lp->rx_new;
510*4882a593Smuzhiyun struct sk_buff *skb;
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun for (rd = &ib->brx_ring [entry];
513*4882a593Smuzhiyun !((bits = rd->rmd1_bits) & LE_R1_OWN);
514*4882a593Smuzhiyun rd = &ib->brx_ring [entry]) {
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun /* We got an incomplete frame? */
517*4882a593Smuzhiyun if ((bits & LE_R1_POK) != LE_R1_POK) {
518*4882a593Smuzhiyun dev->stats.rx_over_errors++;
519*4882a593Smuzhiyun dev->stats.rx_errors++;
520*4882a593Smuzhiyun } else if (bits & LE_R1_ERR) {
521*4882a593Smuzhiyun /* Count only the end frame as a rx error,
522*4882a593Smuzhiyun * not the beginning
523*4882a593Smuzhiyun */
524*4882a593Smuzhiyun if (bits & LE_R1_BUF) dev->stats.rx_fifo_errors++;
525*4882a593Smuzhiyun if (bits & LE_R1_CRC) dev->stats.rx_crc_errors++;
526*4882a593Smuzhiyun if (bits & LE_R1_OFL) dev->stats.rx_over_errors++;
527*4882a593Smuzhiyun if (bits & LE_R1_FRA) dev->stats.rx_frame_errors++;
528*4882a593Smuzhiyun if (bits & LE_R1_EOP) dev->stats.rx_errors++;
529*4882a593Smuzhiyun } else {
530*4882a593Smuzhiyun len = (rd->mblength & 0xfff) - 4;
531*4882a593Smuzhiyun skb = netdev_alloc_skb(dev, len + 2);
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun if (skb == NULL) {
534*4882a593Smuzhiyun dev->stats.rx_dropped++;
535*4882a593Smuzhiyun rd->mblength = 0;
536*4882a593Smuzhiyun rd->rmd1_bits = LE_R1_OWN;
537*4882a593Smuzhiyun lp->rx_new = RX_NEXT(entry);
538*4882a593Smuzhiyun return;
539*4882a593Smuzhiyun }
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun dev->stats.rx_bytes += len;
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun skb_reserve(skb, 2); /* 16 byte align */
544*4882a593Smuzhiyun skb_put(skb, len); /* make room */
545*4882a593Smuzhiyun skb_copy_to_linear_data(skb,
546*4882a593Smuzhiyun (unsigned char *)&(ib->rx_buf [entry][0]),
547*4882a593Smuzhiyun len);
548*4882a593Smuzhiyun skb->protocol = eth_type_trans(skb, dev);
549*4882a593Smuzhiyun netif_rx(skb);
550*4882a593Smuzhiyun dev->stats.rx_packets++;
551*4882a593Smuzhiyun }
552*4882a593Smuzhiyun
553*4882a593Smuzhiyun /* Return the packet to the pool */
554*4882a593Smuzhiyun rd->mblength = 0;
555*4882a593Smuzhiyun rd->rmd1_bits = LE_R1_OWN;
556*4882a593Smuzhiyun entry = RX_NEXT(entry);
557*4882a593Smuzhiyun }
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun lp->rx_new = entry;
560*4882a593Smuzhiyun }
561*4882a593Smuzhiyun
lance_tx_dvma(struct net_device * dev)562*4882a593Smuzhiyun static void lance_tx_dvma(struct net_device *dev)
563*4882a593Smuzhiyun {
564*4882a593Smuzhiyun struct lance_private *lp = netdev_priv(dev);
565*4882a593Smuzhiyun struct lance_init_block *ib = lp->init_block_mem;
566*4882a593Smuzhiyun int i, j;
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun spin_lock(&lp->lock);
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun j = lp->tx_old;
571*4882a593Smuzhiyun for (i = j; i != lp->tx_new; i = j) {
572*4882a593Smuzhiyun struct lance_tx_desc *td = &ib->btx_ring [i];
573*4882a593Smuzhiyun u8 bits = td->tmd1_bits;
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun /* If we hit a packet not owned by us, stop */
576*4882a593Smuzhiyun if (bits & LE_T1_OWN)
577*4882a593Smuzhiyun break;
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun if (bits & LE_T1_ERR) {
580*4882a593Smuzhiyun u16 status = td->misc;
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun dev->stats.tx_errors++;
583*4882a593Smuzhiyun if (status & LE_T3_RTY) dev->stats.tx_aborted_errors++;
584*4882a593Smuzhiyun if (status & LE_T3_LCOL) dev->stats.tx_window_errors++;
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun if (status & LE_T3_CLOS) {
587*4882a593Smuzhiyun dev->stats.tx_carrier_errors++;
588*4882a593Smuzhiyun if (lp->auto_select) {
589*4882a593Smuzhiyun lp->tpe = 1 - lp->tpe;
590*4882a593Smuzhiyun printk(KERN_NOTICE "%s: Carrier Lost, trying %s\n",
591*4882a593Smuzhiyun dev->name, lp->tpe?"TPE":"AUI");
592*4882a593Smuzhiyun STOP_LANCE(lp);
593*4882a593Smuzhiyun lp->init_ring(dev);
594*4882a593Smuzhiyun load_csrs(lp);
595*4882a593Smuzhiyun init_restart_lance(lp);
596*4882a593Smuzhiyun goto out;
597*4882a593Smuzhiyun }
598*4882a593Smuzhiyun }
599*4882a593Smuzhiyun
600*4882a593Smuzhiyun /* Buffer errors and underflows turn off the
601*4882a593Smuzhiyun * transmitter, restart the adapter.
602*4882a593Smuzhiyun */
603*4882a593Smuzhiyun if (status & (LE_T3_BUF|LE_T3_UFL)) {
604*4882a593Smuzhiyun dev->stats.tx_fifo_errors++;
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun printk(KERN_ERR "%s: Tx: ERR_BUF|ERR_UFL, restarting\n",
607*4882a593Smuzhiyun dev->name);
608*4882a593Smuzhiyun STOP_LANCE(lp);
609*4882a593Smuzhiyun lp->init_ring(dev);
610*4882a593Smuzhiyun load_csrs(lp);
611*4882a593Smuzhiyun init_restart_lance(lp);
612*4882a593Smuzhiyun goto out;
613*4882a593Smuzhiyun }
614*4882a593Smuzhiyun } else if ((bits & LE_T1_POK) == LE_T1_POK) {
615*4882a593Smuzhiyun /*
616*4882a593Smuzhiyun * So we don't count the packet more than once.
617*4882a593Smuzhiyun */
618*4882a593Smuzhiyun td->tmd1_bits = bits & ~(LE_T1_POK);
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun /* One collision before packet was sent. */
621*4882a593Smuzhiyun if (bits & LE_T1_EONE)
622*4882a593Smuzhiyun dev->stats.collisions++;
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun /* More than one collision, be optimistic. */
625*4882a593Smuzhiyun if (bits & LE_T1_EMORE)
626*4882a593Smuzhiyun dev->stats.collisions += 2;
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun dev->stats.tx_packets++;
629*4882a593Smuzhiyun }
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun j = TX_NEXT(j);
632*4882a593Smuzhiyun }
633*4882a593Smuzhiyun lp->tx_old = j;
634*4882a593Smuzhiyun out:
635*4882a593Smuzhiyun if (netif_queue_stopped(dev) &&
636*4882a593Smuzhiyun TX_BUFFS_AVAIL > 0)
637*4882a593Smuzhiyun netif_wake_queue(dev);
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun spin_unlock(&lp->lock);
640*4882a593Smuzhiyun }
641*4882a593Smuzhiyun
lance_piocopy_to_skb(struct sk_buff * skb,void __iomem * piobuf,int len)642*4882a593Smuzhiyun static void lance_piocopy_to_skb(struct sk_buff *skb, void __iomem *piobuf, int len)
643*4882a593Smuzhiyun {
644*4882a593Smuzhiyun u16 *p16 = (u16 *) skb->data;
645*4882a593Smuzhiyun u32 *p32;
646*4882a593Smuzhiyun u8 *p8;
647*4882a593Smuzhiyun void __iomem *pbuf = piobuf;
648*4882a593Smuzhiyun
649*4882a593Smuzhiyun /* We know here that both src and dest are on a 16bit boundary. */
650*4882a593Smuzhiyun *p16++ = sbus_readw(pbuf);
651*4882a593Smuzhiyun p32 = (u32 *) p16;
652*4882a593Smuzhiyun pbuf += 2;
653*4882a593Smuzhiyun len -= 2;
654*4882a593Smuzhiyun
655*4882a593Smuzhiyun while (len >= 4) {
656*4882a593Smuzhiyun *p32++ = sbus_readl(pbuf);
657*4882a593Smuzhiyun pbuf += 4;
658*4882a593Smuzhiyun len -= 4;
659*4882a593Smuzhiyun }
660*4882a593Smuzhiyun p8 = (u8 *) p32;
661*4882a593Smuzhiyun if (len >= 2) {
662*4882a593Smuzhiyun p16 = (u16 *) p32;
663*4882a593Smuzhiyun *p16++ = sbus_readw(pbuf);
664*4882a593Smuzhiyun pbuf += 2;
665*4882a593Smuzhiyun len -= 2;
666*4882a593Smuzhiyun p8 = (u8 *) p16;
667*4882a593Smuzhiyun }
668*4882a593Smuzhiyun if (len >= 1)
669*4882a593Smuzhiyun *p8 = sbus_readb(pbuf);
670*4882a593Smuzhiyun }
671*4882a593Smuzhiyun
lance_rx_pio(struct net_device * dev)672*4882a593Smuzhiyun static void lance_rx_pio(struct net_device *dev)
673*4882a593Smuzhiyun {
674*4882a593Smuzhiyun struct lance_private *lp = netdev_priv(dev);
675*4882a593Smuzhiyun struct lance_init_block __iomem *ib = lp->init_block_iomem;
676*4882a593Smuzhiyun struct lance_rx_desc __iomem *rd;
677*4882a593Smuzhiyun unsigned char bits;
678*4882a593Smuzhiyun int len, entry;
679*4882a593Smuzhiyun struct sk_buff *skb;
680*4882a593Smuzhiyun
681*4882a593Smuzhiyun entry = lp->rx_new;
682*4882a593Smuzhiyun for (rd = &ib->brx_ring [entry];
683*4882a593Smuzhiyun !((bits = sbus_readb(&rd->rmd1_bits)) & LE_R1_OWN);
684*4882a593Smuzhiyun rd = &ib->brx_ring [entry]) {
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun /* We got an incomplete frame? */
687*4882a593Smuzhiyun if ((bits & LE_R1_POK) != LE_R1_POK) {
688*4882a593Smuzhiyun dev->stats.rx_over_errors++;
689*4882a593Smuzhiyun dev->stats.rx_errors++;
690*4882a593Smuzhiyun } else if (bits & LE_R1_ERR) {
691*4882a593Smuzhiyun /* Count only the end frame as a rx error,
692*4882a593Smuzhiyun * not the beginning
693*4882a593Smuzhiyun */
694*4882a593Smuzhiyun if (bits & LE_R1_BUF) dev->stats.rx_fifo_errors++;
695*4882a593Smuzhiyun if (bits & LE_R1_CRC) dev->stats.rx_crc_errors++;
696*4882a593Smuzhiyun if (bits & LE_R1_OFL) dev->stats.rx_over_errors++;
697*4882a593Smuzhiyun if (bits & LE_R1_FRA) dev->stats.rx_frame_errors++;
698*4882a593Smuzhiyun if (bits & LE_R1_EOP) dev->stats.rx_errors++;
699*4882a593Smuzhiyun } else {
700*4882a593Smuzhiyun len = (sbus_readw(&rd->mblength) & 0xfff) - 4;
701*4882a593Smuzhiyun skb = netdev_alloc_skb(dev, len + 2);
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun if (skb == NULL) {
704*4882a593Smuzhiyun dev->stats.rx_dropped++;
705*4882a593Smuzhiyun sbus_writew(0, &rd->mblength);
706*4882a593Smuzhiyun sbus_writeb(LE_R1_OWN, &rd->rmd1_bits);
707*4882a593Smuzhiyun lp->rx_new = RX_NEXT(entry);
708*4882a593Smuzhiyun return;
709*4882a593Smuzhiyun }
710*4882a593Smuzhiyun
711*4882a593Smuzhiyun dev->stats.rx_bytes += len;
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun skb_reserve (skb, 2); /* 16 byte align */
714*4882a593Smuzhiyun skb_put(skb, len); /* make room */
715*4882a593Smuzhiyun lance_piocopy_to_skb(skb, &(ib->rx_buf[entry][0]), len);
716*4882a593Smuzhiyun skb->protocol = eth_type_trans(skb, dev);
717*4882a593Smuzhiyun netif_rx(skb);
718*4882a593Smuzhiyun dev->stats.rx_packets++;
719*4882a593Smuzhiyun }
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun /* Return the packet to the pool */
722*4882a593Smuzhiyun sbus_writew(0, &rd->mblength);
723*4882a593Smuzhiyun sbus_writeb(LE_R1_OWN, &rd->rmd1_bits);
724*4882a593Smuzhiyun entry = RX_NEXT(entry);
725*4882a593Smuzhiyun }
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun lp->rx_new = entry;
728*4882a593Smuzhiyun }
729*4882a593Smuzhiyun
lance_tx_pio(struct net_device * dev)730*4882a593Smuzhiyun static void lance_tx_pio(struct net_device *dev)
731*4882a593Smuzhiyun {
732*4882a593Smuzhiyun struct lance_private *lp = netdev_priv(dev);
733*4882a593Smuzhiyun struct lance_init_block __iomem *ib = lp->init_block_iomem;
734*4882a593Smuzhiyun int i, j;
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun spin_lock(&lp->lock);
737*4882a593Smuzhiyun
738*4882a593Smuzhiyun j = lp->tx_old;
739*4882a593Smuzhiyun for (i = j; i != lp->tx_new; i = j) {
740*4882a593Smuzhiyun struct lance_tx_desc __iomem *td = &ib->btx_ring [i];
741*4882a593Smuzhiyun u8 bits = sbus_readb(&td->tmd1_bits);
742*4882a593Smuzhiyun
743*4882a593Smuzhiyun /* If we hit a packet not owned by us, stop */
744*4882a593Smuzhiyun if (bits & LE_T1_OWN)
745*4882a593Smuzhiyun break;
746*4882a593Smuzhiyun
747*4882a593Smuzhiyun if (bits & LE_T1_ERR) {
748*4882a593Smuzhiyun u16 status = sbus_readw(&td->misc);
749*4882a593Smuzhiyun
750*4882a593Smuzhiyun dev->stats.tx_errors++;
751*4882a593Smuzhiyun if (status & LE_T3_RTY) dev->stats.tx_aborted_errors++;
752*4882a593Smuzhiyun if (status & LE_T3_LCOL) dev->stats.tx_window_errors++;
753*4882a593Smuzhiyun
754*4882a593Smuzhiyun if (status & LE_T3_CLOS) {
755*4882a593Smuzhiyun dev->stats.tx_carrier_errors++;
756*4882a593Smuzhiyun if (lp->auto_select) {
757*4882a593Smuzhiyun lp->tpe = 1 - lp->tpe;
758*4882a593Smuzhiyun printk(KERN_NOTICE "%s: Carrier Lost, trying %s\n",
759*4882a593Smuzhiyun dev->name, lp->tpe?"TPE":"AUI");
760*4882a593Smuzhiyun STOP_LANCE(lp);
761*4882a593Smuzhiyun lp->init_ring(dev);
762*4882a593Smuzhiyun load_csrs(lp);
763*4882a593Smuzhiyun init_restart_lance(lp);
764*4882a593Smuzhiyun goto out;
765*4882a593Smuzhiyun }
766*4882a593Smuzhiyun }
767*4882a593Smuzhiyun
768*4882a593Smuzhiyun /* Buffer errors and underflows turn off the
769*4882a593Smuzhiyun * transmitter, restart the adapter.
770*4882a593Smuzhiyun */
771*4882a593Smuzhiyun if (status & (LE_T3_BUF|LE_T3_UFL)) {
772*4882a593Smuzhiyun dev->stats.tx_fifo_errors++;
773*4882a593Smuzhiyun
774*4882a593Smuzhiyun printk(KERN_ERR "%s: Tx: ERR_BUF|ERR_UFL, restarting\n",
775*4882a593Smuzhiyun dev->name);
776*4882a593Smuzhiyun STOP_LANCE(lp);
777*4882a593Smuzhiyun lp->init_ring(dev);
778*4882a593Smuzhiyun load_csrs(lp);
779*4882a593Smuzhiyun init_restart_lance(lp);
780*4882a593Smuzhiyun goto out;
781*4882a593Smuzhiyun }
782*4882a593Smuzhiyun } else if ((bits & LE_T1_POK) == LE_T1_POK) {
783*4882a593Smuzhiyun /*
784*4882a593Smuzhiyun * So we don't count the packet more than once.
785*4882a593Smuzhiyun */
786*4882a593Smuzhiyun sbus_writeb(bits & ~(LE_T1_POK), &td->tmd1_bits);
787*4882a593Smuzhiyun
788*4882a593Smuzhiyun /* One collision before packet was sent. */
789*4882a593Smuzhiyun if (bits & LE_T1_EONE)
790*4882a593Smuzhiyun dev->stats.collisions++;
791*4882a593Smuzhiyun
792*4882a593Smuzhiyun /* More than one collision, be optimistic. */
793*4882a593Smuzhiyun if (bits & LE_T1_EMORE)
794*4882a593Smuzhiyun dev->stats.collisions += 2;
795*4882a593Smuzhiyun
796*4882a593Smuzhiyun dev->stats.tx_packets++;
797*4882a593Smuzhiyun }
798*4882a593Smuzhiyun
799*4882a593Smuzhiyun j = TX_NEXT(j);
800*4882a593Smuzhiyun }
801*4882a593Smuzhiyun lp->tx_old = j;
802*4882a593Smuzhiyun
803*4882a593Smuzhiyun if (netif_queue_stopped(dev) &&
804*4882a593Smuzhiyun TX_BUFFS_AVAIL > 0)
805*4882a593Smuzhiyun netif_wake_queue(dev);
806*4882a593Smuzhiyun out:
807*4882a593Smuzhiyun spin_unlock(&lp->lock);
808*4882a593Smuzhiyun }
809*4882a593Smuzhiyun
lance_interrupt(int irq,void * dev_id)810*4882a593Smuzhiyun static irqreturn_t lance_interrupt(int irq, void *dev_id)
811*4882a593Smuzhiyun {
812*4882a593Smuzhiyun struct net_device *dev = dev_id;
813*4882a593Smuzhiyun struct lance_private *lp = netdev_priv(dev);
814*4882a593Smuzhiyun int csr0;
815*4882a593Smuzhiyun
816*4882a593Smuzhiyun sbus_writew(LE_CSR0, lp->lregs + RAP);
817*4882a593Smuzhiyun csr0 = sbus_readw(lp->lregs + RDP);
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun /* Acknowledge all the interrupt sources ASAP */
820*4882a593Smuzhiyun sbus_writew(csr0 & (LE_C0_INTR | LE_C0_TINT | LE_C0_RINT),
821*4882a593Smuzhiyun lp->lregs + RDP);
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun if ((csr0 & LE_C0_ERR) != 0) {
824*4882a593Smuzhiyun /* Clear the error condition */
825*4882a593Smuzhiyun sbus_writew((LE_C0_BABL | LE_C0_ERR | LE_C0_MISS |
826*4882a593Smuzhiyun LE_C0_CERR | LE_C0_MERR),
827*4882a593Smuzhiyun lp->lregs + RDP);
828*4882a593Smuzhiyun }
829*4882a593Smuzhiyun
830*4882a593Smuzhiyun if (csr0 & LE_C0_RINT)
831*4882a593Smuzhiyun lp->rx(dev);
832*4882a593Smuzhiyun
833*4882a593Smuzhiyun if (csr0 & LE_C0_TINT)
834*4882a593Smuzhiyun lp->tx(dev);
835*4882a593Smuzhiyun
836*4882a593Smuzhiyun if (csr0 & LE_C0_BABL)
837*4882a593Smuzhiyun dev->stats.tx_errors++;
838*4882a593Smuzhiyun
839*4882a593Smuzhiyun if (csr0 & LE_C0_MISS)
840*4882a593Smuzhiyun dev->stats.rx_errors++;
841*4882a593Smuzhiyun
842*4882a593Smuzhiyun if (csr0 & LE_C0_MERR) {
843*4882a593Smuzhiyun if (lp->dregs) {
844*4882a593Smuzhiyun u32 addr = sbus_readl(lp->dregs + DMA_ADDR);
845*4882a593Smuzhiyun
846*4882a593Smuzhiyun printk(KERN_ERR "%s: Memory error, status %04x, addr %06x\n",
847*4882a593Smuzhiyun dev->name, csr0, addr & 0xffffff);
848*4882a593Smuzhiyun } else {
849*4882a593Smuzhiyun printk(KERN_ERR "%s: Memory error, status %04x\n",
850*4882a593Smuzhiyun dev->name, csr0);
851*4882a593Smuzhiyun }
852*4882a593Smuzhiyun
853*4882a593Smuzhiyun sbus_writew(LE_C0_STOP, lp->lregs + RDP);
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun if (lp->dregs) {
856*4882a593Smuzhiyun u32 dma_csr = sbus_readl(lp->dregs + DMA_CSR);
857*4882a593Smuzhiyun
858*4882a593Smuzhiyun dma_csr |= DMA_FIFO_INV;
859*4882a593Smuzhiyun sbus_writel(dma_csr, lp->dregs + DMA_CSR);
860*4882a593Smuzhiyun }
861*4882a593Smuzhiyun
862*4882a593Smuzhiyun lp->init_ring(dev);
863*4882a593Smuzhiyun load_csrs(lp);
864*4882a593Smuzhiyun init_restart_lance(lp);
865*4882a593Smuzhiyun netif_wake_queue(dev);
866*4882a593Smuzhiyun }
867*4882a593Smuzhiyun
868*4882a593Smuzhiyun sbus_writew(LE_C0_INEA, lp->lregs + RDP);
869*4882a593Smuzhiyun
870*4882a593Smuzhiyun return IRQ_HANDLED;
871*4882a593Smuzhiyun }
872*4882a593Smuzhiyun
873*4882a593Smuzhiyun /* Build a fake network packet and send it to ourselves. */
build_fake_packet(struct lance_private * lp)874*4882a593Smuzhiyun static void build_fake_packet(struct lance_private *lp)
875*4882a593Smuzhiyun {
876*4882a593Smuzhiyun struct net_device *dev = lp->dev;
877*4882a593Smuzhiyun int i, entry;
878*4882a593Smuzhiyun
879*4882a593Smuzhiyun entry = lp->tx_new & TX_RING_MOD_MASK;
880*4882a593Smuzhiyun if (lp->pio_buffer) {
881*4882a593Smuzhiyun struct lance_init_block __iomem *ib = lp->init_block_iomem;
882*4882a593Smuzhiyun u16 __iomem *packet = (u16 __iomem *) &(ib->tx_buf[entry][0]);
883*4882a593Smuzhiyun struct ethhdr __iomem *eth = (struct ethhdr __iomem *) packet;
884*4882a593Smuzhiyun for (i = 0; i < (ETH_ZLEN / sizeof(u16)); i++)
885*4882a593Smuzhiyun sbus_writew(0, &packet[i]);
886*4882a593Smuzhiyun for (i = 0; i < 6; i++) {
887*4882a593Smuzhiyun sbus_writeb(dev->dev_addr[i], ð->h_dest[i]);
888*4882a593Smuzhiyun sbus_writeb(dev->dev_addr[i], ð->h_source[i]);
889*4882a593Smuzhiyun }
890*4882a593Smuzhiyun sbus_writew((-ETH_ZLEN) | 0xf000, &ib->btx_ring[entry].length);
891*4882a593Smuzhiyun sbus_writew(0, &ib->btx_ring[entry].misc);
892*4882a593Smuzhiyun sbus_writeb(LE_T1_POK|LE_T1_OWN, &ib->btx_ring[entry].tmd1_bits);
893*4882a593Smuzhiyun } else {
894*4882a593Smuzhiyun struct lance_init_block *ib = lp->init_block_mem;
895*4882a593Smuzhiyun u16 *packet = (u16 *) &(ib->tx_buf[entry][0]);
896*4882a593Smuzhiyun struct ethhdr *eth = (struct ethhdr *) packet;
897*4882a593Smuzhiyun memset(packet, 0, ETH_ZLEN);
898*4882a593Smuzhiyun for (i = 0; i < 6; i++) {
899*4882a593Smuzhiyun eth->h_dest[i] = dev->dev_addr[i];
900*4882a593Smuzhiyun eth->h_source[i] = dev->dev_addr[i];
901*4882a593Smuzhiyun }
902*4882a593Smuzhiyun ib->btx_ring[entry].length = (-ETH_ZLEN) | 0xf000;
903*4882a593Smuzhiyun ib->btx_ring[entry].misc = 0;
904*4882a593Smuzhiyun ib->btx_ring[entry].tmd1_bits = (LE_T1_POK|LE_T1_OWN);
905*4882a593Smuzhiyun }
906*4882a593Smuzhiyun lp->tx_new = TX_NEXT(entry);
907*4882a593Smuzhiyun }
908*4882a593Smuzhiyun
lance_open(struct net_device * dev)909*4882a593Smuzhiyun static int lance_open(struct net_device *dev)
910*4882a593Smuzhiyun {
911*4882a593Smuzhiyun struct lance_private *lp = netdev_priv(dev);
912*4882a593Smuzhiyun int status = 0;
913*4882a593Smuzhiyun
914*4882a593Smuzhiyun STOP_LANCE(lp);
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun if (request_irq(dev->irq, lance_interrupt, IRQF_SHARED,
917*4882a593Smuzhiyun lancestr, (void *) dev)) {
918*4882a593Smuzhiyun printk(KERN_ERR "Lance: Can't get irq %d\n", dev->irq);
919*4882a593Smuzhiyun return -EAGAIN;
920*4882a593Smuzhiyun }
921*4882a593Smuzhiyun
922*4882a593Smuzhiyun /* On the 4m, setup the ledma to provide the upper bits for buffers */
923*4882a593Smuzhiyun if (lp->dregs) {
924*4882a593Smuzhiyun u32 regval = lp->init_block_dvma & 0xff000000;
925*4882a593Smuzhiyun
926*4882a593Smuzhiyun sbus_writel(regval, lp->dregs + DMA_TEST);
927*4882a593Smuzhiyun }
928*4882a593Smuzhiyun
929*4882a593Smuzhiyun /* Set mode and clear multicast filter only at device open,
930*4882a593Smuzhiyun * so that lance_init_ring() called at any error will not
931*4882a593Smuzhiyun * forget multicast filters.
932*4882a593Smuzhiyun *
933*4882a593Smuzhiyun * BTW it is common bug in all lance drivers! --ANK
934*4882a593Smuzhiyun */
935*4882a593Smuzhiyun if (lp->pio_buffer) {
936*4882a593Smuzhiyun struct lance_init_block __iomem *ib = lp->init_block_iomem;
937*4882a593Smuzhiyun sbus_writew(0, &ib->mode);
938*4882a593Smuzhiyun sbus_writel(0, &ib->filter[0]);
939*4882a593Smuzhiyun sbus_writel(0, &ib->filter[1]);
940*4882a593Smuzhiyun } else {
941*4882a593Smuzhiyun struct lance_init_block *ib = lp->init_block_mem;
942*4882a593Smuzhiyun ib->mode = 0;
943*4882a593Smuzhiyun ib->filter [0] = 0;
944*4882a593Smuzhiyun ib->filter [1] = 0;
945*4882a593Smuzhiyun }
946*4882a593Smuzhiyun
947*4882a593Smuzhiyun lp->init_ring(dev);
948*4882a593Smuzhiyun load_csrs(lp);
949*4882a593Smuzhiyun
950*4882a593Smuzhiyun netif_start_queue(dev);
951*4882a593Smuzhiyun
952*4882a593Smuzhiyun status = init_restart_lance(lp);
953*4882a593Smuzhiyun if (!status && lp->auto_select) {
954*4882a593Smuzhiyun build_fake_packet(lp);
955*4882a593Smuzhiyun sbus_writew(LE_C0_INEA | LE_C0_TDMD, lp->lregs + RDP);
956*4882a593Smuzhiyun }
957*4882a593Smuzhiyun
958*4882a593Smuzhiyun return status;
959*4882a593Smuzhiyun }
960*4882a593Smuzhiyun
lance_close(struct net_device * dev)961*4882a593Smuzhiyun static int lance_close(struct net_device *dev)
962*4882a593Smuzhiyun {
963*4882a593Smuzhiyun struct lance_private *lp = netdev_priv(dev);
964*4882a593Smuzhiyun
965*4882a593Smuzhiyun netif_stop_queue(dev);
966*4882a593Smuzhiyun del_timer_sync(&lp->multicast_timer);
967*4882a593Smuzhiyun
968*4882a593Smuzhiyun STOP_LANCE(lp);
969*4882a593Smuzhiyun
970*4882a593Smuzhiyun free_irq(dev->irq, (void *) dev);
971*4882a593Smuzhiyun return 0;
972*4882a593Smuzhiyun }
973*4882a593Smuzhiyun
lance_reset(struct net_device * dev)974*4882a593Smuzhiyun static int lance_reset(struct net_device *dev)
975*4882a593Smuzhiyun {
976*4882a593Smuzhiyun struct lance_private *lp = netdev_priv(dev);
977*4882a593Smuzhiyun int status;
978*4882a593Smuzhiyun
979*4882a593Smuzhiyun STOP_LANCE(lp);
980*4882a593Smuzhiyun
981*4882a593Smuzhiyun /* On the 4m, reset the dma too */
982*4882a593Smuzhiyun if (lp->dregs) {
983*4882a593Smuzhiyun u32 csr, addr;
984*4882a593Smuzhiyun
985*4882a593Smuzhiyun printk(KERN_ERR "resetting ledma\n");
986*4882a593Smuzhiyun csr = sbus_readl(lp->dregs + DMA_CSR);
987*4882a593Smuzhiyun sbus_writel(csr | DMA_RST_ENET, lp->dregs + DMA_CSR);
988*4882a593Smuzhiyun udelay(200);
989*4882a593Smuzhiyun sbus_writel(csr & ~DMA_RST_ENET, lp->dregs + DMA_CSR);
990*4882a593Smuzhiyun
991*4882a593Smuzhiyun addr = lp->init_block_dvma & 0xff000000;
992*4882a593Smuzhiyun sbus_writel(addr, lp->dregs + DMA_TEST);
993*4882a593Smuzhiyun }
994*4882a593Smuzhiyun lp->init_ring(dev);
995*4882a593Smuzhiyun load_csrs(lp);
996*4882a593Smuzhiyun netif_trans_update(dev); /* prevent tx timeout */
997*4882a593Smuzhiyun status = init_restart_lance(lp);
998*4882a593Smuzhiyun return status;
999*4882a593Smuzhiyun }
1000*4882a593Smuzhiyun
lance_piocopy_from_skb(void __iomem * dest,unsigned char * src,int len)1001*4882a593Smuzhiyun static void lance_piocopy_from_skb(void __iomem *dest, unsigned char *src, int len)
1002*4882a593Smuzhiyun {
1003*4882a593Smuzhiyun void __iomem *piobuf = dest;
1004*4882a593Smuzhiyun u32 *p32;
1005*4882a593Smuzhiyun u16 *p16;
1006*4882a593Smuzhiyun u8 *p8;
1007*4882a593Smuzhiyun
1008*4882a593Smuzhiyun switch ((unsigned long)src & 0x3) {
1009*4882a593Smuzhiyun case 0:
1010*4882a593Smuzhiyun p32 = (u32 *) src;
1011*4882a593Smuzhiyun while (len >= 4) {
1012*4882a593Smuzhiyun sbus_writel(*p32, piobuf);
1013*4882a593Smuzhiyun p32++;
1014*4882a593Smuzhiyun piobuf += 4;
1015*4882a593Smuzhiyun len -= 4;
1016*4882a593Smuzhiyun }
1017*4882a593Smuzhiyun src = (char *) p32;
1018*4882a593Smuzhiyun break;
1019*4882a593Smuzhiyun case 1:
1020*4882a593Smuzhiyun case 3:
1021*4882a593Smuzhiyun p8 = (u8 *) src;
1022*4882a593Smuzhiyun while (len >= 4) {
1023*4882a593Smuzhiyun u32 val;
1024*4882a593Smuzhiyun
1025*4882a593Smuzhiyun val = p8[0] << 24;
1026*4882a593Smuzhiyun val |= p8[1] << 16;
1027*4882a593Smuzhiyun val |= p8[2] << 8;
1028*4882a593Smuzhiyun val |= p8[3];
1029*4882a593Smuzhiyun sbus_writel(val, piobuf);
1030*4882a593Smuzhiyun p8 += 4;
1031*4882a593Smuzhiyun piobuf += 4;
1032*4882a593Smuzhiyun len -= 4;
1033*4882a593Smuzhiyun }
1034*4882a593Smuzhiyun src = (char *) p8;
1035*4882a593Smuzhiyun break;
1036*4882a593Smuzhiyun case 2:
1037*4882a593Smuzhiyun p16 = (u16 *) src;
1038*4882a593Smuzhiyun while (len >= 4) {
1039*4882a593Smuzhiyun u32 val = p16[0]<<16 | p16[1];
1040*4882a593Smuzhiyun sbus_writel(val, piobuf);
1041*4882a593Smuzhiyun p16 += 2;
1042*4882a593Smuzhiyun piobuf += 4;
1043*4882a593Smuzhiyun len -= 4;
1044*4882a593Smuzhiyun }
1045*4882a593Smuzhiyun src = (char *) p16;
1046*4882a593Smuzhiyun break;
1047*4882a593Smuzhiyun }
1048*4882a593Smuzhiyun if (len >= 2) {
1049*4882a593Smuzhiyun u16 val = src[0] << 8 | src[1];
1050*4882a593Smuzhiyun sbus_writew(val, piobuf);
1051*4882a593Smuzhiyun src += 2;
1052*4882a593Smuzhiyun piobuf += 2;
1053*4882a593Smuzhiyun len -= 2;
1054*4882a593Smuzhiyun }
1055*4882a593Smuzhiyun if (len >= 1)
1056*4882a593Smuzhiyun sbus_writeb(src[0], piobuf);
1057*4882a593Smuzhiyun }
1058*4882a593Smuzhiyun
lance_piozero(void __iomem * dest,int len)1059*4882a593Smuzhiyun static void lance_piozero(void __iomem *dest, int len)
1060*4882a593Smuzhiyun {
1061*4882a593Smuzhiyun void __iomem *piobuf = dest;
1062*4882a593Smuzhiyun
1063*4882a593Smuzhiyun if ((unsigned long)piobuf & 1) {
1064*4882a593Smuzhiyun sbus_writeb(0, piobuf);
1065*4882a593Smuzhiyun piobuf += 1;
1066*4882a593Smuzhiyun len -= 1;
1067*4882a593Smuzhiyun if (len == 0)
1068*4882a593Smuzhiyun return;
1069*4882a593Smuzhiyun }
1070*4882a593Smuzhiyun if (len == 1) {
1071*4882a593Smuzhiyun sbus_writeb(0, piobuf);
1072*4882a593Smuzhiyun return;
1073*4882a593Smuzhiyun }
1074*4882a593Smuzhiyun if ((unsigned long)piobuf & 2) {
1075*4882a593Smuzhiyun sbus_writew(0, piobuf);
1076*4882a593Smuzhiyun piobuf += 2;
1077*4882a593Smuzhiyun len -= 2;
1078*4882a593Smuzhiyun if (len == 0)
1079*4882a593Smuzhiyun return;
1080*4882a593Smuzhiyun }
1081*4882a593Smuzhiyun while (len >= 4) {
1082*4882a593Smuzhiyun sbus_writel(0, piobuf);
1083*4882a593Smuzhiyun piobuf += 4;
1084*4882a593Smuzhiyun len -= 4;
1085*4882a593Smuzhiyun }
1086*4882a593Smuzhiyun if (len >= 2) {
1087*4882a593Smuzhiyun sbus_writew(0, piobuf);
1088*4882a593Smuzhiyun piobuf += 2;
1089*4882a593Smuzhiyun len -= 2;
1090*4882a593Smuzhiyun }
1091*4882a593Smuzhiyun if (len >= 1)
1092*4882a593Smuzhiyun sbus_writeb(0, piobuf);
1093*4882a593Smuzhiyun }
1094*4882a593Smuzhiyun
lance_tx_timeout(struct net_device * dev,unsigned int txqueue)1095*4882a593Smuzhiyun static void lance_tx_timeout(struct net_device *dev, unsigned int txqueue)
1096*4882a593Smuzhiyun {
1097*4882a593Smuzhiyun struct lance_private *lp = netdev_priv(dev);
1098*4882a593Smuzhiyun
1099*4882a593Smuzhiyun printk(KERN_ERR "%s: transmit timed out, status %04x, reset\n",
1100*4882a593Smuzhiyun dev->name, sbus_readw(lp->lregs + RDP));
1101*4882a593Smuzhiyun lance_reset(dev);
1102*4882a593Smuzhiyun netif_wake_queue(dev);
1103*4882a593Smuzhiyun }
1104*4882a593Smuzhiyun
lance_start_xmit(struct sk_buff * skb,struct net_device * dev)1105*4882a593Smuzhiyun static netdev_tx_t lance_start_xmit(struct sk_buff *skb, struct net_device *dev)
1106*4882a593Smuzhiyun {
1107*4882a593Smuzhiyun struct lance_private *lp = netdev_priv(dev);
1108*4882a593Smuzhiyun int entry, skblen, len;
1109*4882a593Smuzhiyun
1110*4882a593Smuzhiyun skblen = skb->len;
1111*4882a593Smuzhiyun
1112*4882a593Smuzhiyun len = (skblen <= ETH_ZLEN) ? ETH_ZLEN : skblen;
1113*4882a593Smuzhiyun
1114*4882a593Smuzhiyun spin_lock_irq(&lp->lock);
1115*4882a593Smuzhiyun
1116*4882a593Smuzhiyun dev->stats.tx_bytes += len;
1117*4882a593Smuzhiyun
1118*4882a593Smuzhiyun entry = lp->tx_new & TX_RING_MOD_MASK;
1119*4882a593Smuzhiyun if (lp->pio_buffer) {
1120*4882a593Smuzhiyun struct lance_init_block __iomem *ib = lp->init_block_iomem;
1121*4882a593Smuzhiyun sbus_writew((-len) | 0xf000, &ib->btx_ring[entry].length);
1122*4882a593Smuzhiyun sbus_writew(0, &ib->btx_ring[entry].misc);
1123*4882a593Smuzhiyun lance_piocopy_from_skb(&ib->tx_buf[entry][0], skb->data, skblen);
1124*4882a593Smuzhiyun if (len != skblen)
1125*4882a593Smuzhiyun lance_piozero(&ib->tx_buf[entry][skblen], len - skblen);
1126*4882a593Smuzhiyun sbus_writeb(LE_T1_POK | LE_T1_OWN, &ib->btx_ring[entry].tmd1_bits);
1127*4882a593Smuzhiyun } else {
1128*4882a593Smuzhiyun struct lance_init_block *ib = lp->init_block_mem;
1129*4882a593Smuzhiyun ib->btx_ring [entry].length = (-len) | 0xf000;
1130*4882a593Smuzhiyun ib->btx_ring [entry].misc = 0;
1131*4882a593Smuzhiyun skb_copy_from_linear_data(skb, &ib->tx_buf [entry][0], skblen);
1132*4882a593Smuzhiyun if (len != skblen)
1133*4882a593Smuzhiyun memset((char *) &ib->tx_buf [entry][skblen], 0, len - skblen);
1134*4882a593Smuzhiyun ib->btx_ring [entry].tmd1_bits = (LE_T1_POK | LE_T1_OWN);
1135*4882a593Smuzhiyun }
1136*4882a593Smuzhiyun
1137*4882a593Smuzhiyun lp->tx_new = TX_NEXT(entry);
1138*4882a593Smuzhiyun
1139*4882a593Smuzhiyun if (TX_BUFFS_AVAIL <= 0)
1140*4882a593Smuzhiyun netif_stop_queue(dev);
1141*4882a593Smuzhiyun
1142*4882a593Smuzhiyun /* Kick the lance: transmit now */
1143*4882a593Smuzhiyun sbus_writew(LE_C0_INEA | LE_C0_TDMD, lp->lregs + RDP);
1144*4882a593Smuzhiyun
1145*4882a593Smuzhiyun /* Read back CSR to invalidate the E-Cache.
1146*4882a593Smuzhiyun * This is needed, because DMA_DSBL_WR_INV is set.
1147*4882a593Smuzhiyun */
1148*4882a593Smuzhiyun if (lp->dregs)
1149*4882a593Smuzhiyun sbus_readw(lp->lregs + RDP);
1150*4882a593Smuzhiyun
1151*4882a593Smuzhiyun spin_unlock_irq(&lp->lock);
1152*4882a593Smuzhiyun
1153*4882a593Smuzhiyun dev_kfree_skb(skb);
1154*4882a593Smuzhiyun
1155*4882a593Smuzhiyun return NETDEV_TX_OK;
1156*4882a593Smuzhiyun }
1157*4882a593Smuzhiyun
1158*4882a593Smuzhiyun /* taken from the depca driver */
lance_load_multicast(struct net_device * dev)1159*4882a593Smuzhiyun static void lance_load_multicast(struct net_device *dev)
1160*4882a593Smuzhiyun {
1161*4882a593Smuzhiyun struct lance_private *lp = netdev_priv(dev);
1162*4882a593Smuzhiyun struct netdev_hw_addr *ha;
1163*4882a593Smuzhiyun u32 crc;
1164*4882a593Smuzhiyun u32 val;
1165*4882a593Smuzhiyun
1166*4882a593Smuzhiyun /* set all multicast bits */
1167*4882a593Smuzhiyun if (dev->flags & IFF_ALLMULTI)
1168*4882a593Smuzhiyun val = ~0;
1169*4882a593Smuzhiyun else
1170*4882a593Smuzhiyun val = 0;
1171*4882a593Smuzhiyun
1172*4882a593Smuzhiyun if (lp->pio_buffer) {
1173*4882a593Smuzhiyun struct lance_init_block __iomem *ib = lp->init_block_iomem;
1174*4882a593Smuzhiyun sbus_writel(val, &ib->filter[0]);
1175*4882a593Smuzhiyun sbus_writel(val, &ib->filter[1]);
1176*4882a593Smuzhiyun } else {
1177*4882a593Smuzhiyun struct lance_init_block *ib = lp->init_block_mem;
1178*4882a593Smuzhiyun ib->filter [0] = val;
1179*4882a593Smuzhiyun ib->filter [1] = val;
1180*4882a593Smuzhiyun }
1181*4882a593Smuzhiyun
1182*4882a593Smuzhiyun if (dev->flags & IFF_ALLMULTI)
1183*4882a593Smuzhiyun return;
1184*4882a593Smuzhiyun
1185*4882a593Smuzhiyun /* Add addresses */
1186*4882a593Smuzhiyun netdev_for_each_mc_addr(ha, dev) {
1187*4882a593Smuzhiyun crc = ether_crc_le(6, ha->addr);
1188*4882a593Smuzhiyun crc = crc >> 26;
1189*4882a593Smuzhiyun if (lp->pio_buffer) {
1190*4882a593Smuzhiyun struct lance_init_block __iomem *ib = lp->init_block_iomem;
1191*4882a593Smuzhiyun u16 __iomem *mcast_table = (u16 __iomem *) &ib->filter;
1192*4882a593Smuzhiyun u16 tmp = sbus_readw(&mcast_table[crc>>4]);
1193*4882a593Smuzhiyun tmp |= 1 << (crc & 0xf);
1194*4882a593Smuzhiyun sbus_writew(tmp, &mcast_table[crc>>4]);
1195*4882a593Smuzhiyun } else {
1196*4882a593Smuzhiyun struct lance_init_block *ib = lp->init_block_mem;
1197*4882a593Smuzhiyun u16 *mcast_table = (u16 *) &ib->filter;
1198*4882a593Smuzhiyun mcast_table [crc >> 4] |= 1 << (crc & 0xf);
1199*4882a593Smuzhiyun }
1200*4882a593Smuzhiyun }
1201*4882a593Smuzhiyun }
1202*4882a593Smuzhiyun
lance_set_multicast(struct net_device * dev)1203*4882a593Smuzhiyun static void lance_set_multicast(struct net_device *dev)
1204*4882a593Smuzhiyun {
1205*4882a593Smuzhiyun struct lance_private *lp = netdev_priv(dev);
1206*4882a593Smuzhiyun struct lance_init_block *ib_mem = lp->init_block_mem;
1207*4882a593Smuzhiyun struct lance_init_block __iomem *ib_iomem = lp->init_block_iomem;
1208*4882a593Smuzhiyun u16 mode;
1209*4882a593Smuzhiyun
1210*4882a593Smuzhiyun if (!netif_running(dev))
1211*4882a593Smuzhiyun return;
1212*4882a593Smuzhiyun
1213*4882a593Smuzhiyun if (lp->tx_old != lp->tx_new) {
1214*4882a593Smuzhiyun mod_timer(&lp->multicast_timer, jiffies + 4);
1215*4882a593Smuzhiyun netif_wake_queue(dev);
1216*4882a593Smuzhiyun return;
1217*4882a593Smuzhiyun }
1218*4882a593Smuzhiyun
1219*4882a593Smuzhiyun netif_stop_queue(dev);
1220*4882a593Smuzhiyun
1221*4882a593Smuzhiyun STOP_LANCE(lp);
1222*4882a593Smuzhiyun lp->init_ring(dev);
1223*4882a593Smuzhiyun
1224*4882a593Smuzhiyun if (lp->pio_buffer)
1225*4882a593Smuzhiyun mode = sbus_readw(&ib_iomem->mode);
1226*4882a593Smuzhiyun else
1227*4882a593Smuzhiyun mode = ib_mem->mode;
1228*4882a593Smuzhiyun if (dev->flags & IFF_PROMISC) {
1229*4882a593Smuzhiyun mode |= LE_MO_PROM;
1230*4882a593Smuzhiyun if (lp->pio_buffer)
1231*4882a593Smuzhiyun sbus_writew(mode, &ib_iomem->mode);
1232*4882a593Smuzhiyun else
1233*4882a593Smuzhiyun ib_mem->mode = mode;
1234*4882a593Smuzhiyun } else {
1235*4882a593Smuzhiyun mode &= ~LE_MO_PROM;
1236*4882a593Smuzhiyun if (lp->pio_buffer)
1237*4882a593Smuzhiyun sbus_writew(mode, &ib_iomem->mode);
1238*4882a593Smuzhiyun else
1239*4882a593Smuzhiyun ib_mem->mode = mode;
1240*4882a593Smuzhiyun lance_load_multicast(dev);
1241*4882a593Smuzhiyun }
1242*4882a593Smuzhiyun load_csrs(lp);
1243*4882a593Smuzhiyun init_restart_lance(lp);
1244*4882a593Smuzhiyun netif_wake_queue(dev);
1245*4882a593Smuzhiyun }
1246*4882a593Smuzhiyun
lance_set_multicast_retry(struct timer_list * t)1247*4882a593Smuzhiyun static void lance_set_multicast_retry(struct timer_list *t)
1248*4882a593Smuzhiyun {
1249*4882a593Smuzhiyun struct lance_private *lp = from_timer(lp, t, multicast_timer);
1250*4882a593Smuzhiyun struct net_device *dev = lp->dev;
1251*4882a593Smuzhiyun
1252*4882a593Smuzhiyun lance_set_multicast(dev);
1253*4882a593Smuzhiyun }
1254*4882a593Smuzhiyun
lance_free_hwresources(struct lance_private * lp)1255*4882a593Smuzhiyun static void lance_free_hwresources(struct lance_private *lp)
1256*4882a593Smuzhiyun {
1257*4882a593Smuzhiyun if (lp->lregs)
1258*4882a593Smuzhiyun of_iounmap(&lp->op->resource[0], lp->lregs, LANCE_REG_SIZE);
1259*4882a593Smuzhiyun if (lp->dregs) {
1260*4882a593Smuzhiyun struct platform_device *ledma = lp->ledma;
1261*4882a593Smuzhiyun
1262*4882a593Smuzhiyun of_iounmap(&ledma->resource[0], lp->dregs,
1263*4882a593Smuzhiyun resource_size(&ledma->resource[0]));
1264*4882a593Smuzhiyun }
1265*4882a593Smuzhiyun if (lp->init_block_iomem) {
1266*4882a593Smuzhiyun of_iounmap(&lp->lebuffer->resource[0], lp->init_block_iomem,
1267*4882a593Smuzhiyun sizeof(struct lance_init_block));
1268*4882a593Smuzhiyun } else if (lp->init_block_mem) {
1269*4882a593Smuzhiyun dma_free_coherent(&lp->op->dev,
1270*4882a593Smuzhiyun sizeof(struct lance_init_block),
1271*4882a593Smuzhiyun lp->init_block_mem,
1272*4882a593Smuzhiyun lp->init_block_dvma);
1273*4882a593Smuzhiyun }
1274*4882a593Smuzhiyun }
1275*4882a593Smuzhiyun
1276*4882a593Smuzhiyun /* Ethtool support... */
sparc_lance_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)1277*4882a593Smuzhiyun static void sparc_lance_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1278*4882a593Smuzhiyun {
1279*4882a593Smuzhiyun strlcpy(info->driver, "sunlance", sizeof(info->driver));
1280*4882a593Smuzhiyun }
1281*4882a593Smuzhiyun
1282*4882a593Smuzhiyun static const struct ethtool_ops sparc_lance_ethtool_ops = {
1283*4882a593Smuzhiyun .get_drvinfo = sparc_lance_get_drvinfo,
1284*4882a593Smuzhiyun .get_link = ethtool_op_get_link,
1285*4882a593Smuzhiyun };
1286*4882a593Smuzhiyun
1287*4882a593Smuzhiyun static const struct net_device_ops sparc_lance_ops = {
1288*4882a593Smuzhiyun .ndo_open = lance_open,
1289*4882a593Smuzhiyun .ndo_stop = lance_close,
1290*4882a593Smuzhiyun .ndo_start_xmit = lance_start_xmit,
1291*4882a593Smuzhiyun .ndo_set_rx_mode = lance_set_multicast,
1292*4882a593Smuzhiyun .ndo_tx_timeout = lance_tx_timeout,
1293*4882a593Smuzhiyun .ndo_set_mac_address = eth_mac_addr,
1294*4882a593Smuzhiyun .ndo_validate_addr = eth_validate_addr,
1295*4882a593Smuzhiyun };
1296*4882a593Smuzhiyun
sparc_lance_probe_one(struct platform_device * op,struct platform_device * ledma,struct platform_device * lebuffer)1297*4882a593Smuzhiyun static int sparc_lance_probe_one(struct platform_device *op,
1298*4882a593Smuzhiyun struct platform_device *ledma,
1299*4882a593Smuzhiyun struct platform_device *lebuffer)
1300*4882a593Smuzhiyun {
1301*4882a593Smuzhiyun struct device_node *dp = op->dev.of_node;
1302*4882a593Smuzhiyun struct lance_private *lp;
1303*4882a593Smuzhiyun struct net_device *dev;
1304*4882a593Smuzhiyun int i;
1305*4882a593Smuzhiyun
1306*4882a593Smuzhiyun dev = alloc_etherdev(sizeof(struct lance_private) + 8);
1307*4882a593Smuzhiyun if (!dev)
1308*4882a593Smuzhiyun return -ENOMEM;
1309*4882a593Smuzhiyun
1310*4882a593Smuzhiyun lp = netdev_priv(dev);
1311*4882a593Smuzhiyun
1312*4882a593Smuzhiyun spin_lock_init(&lp->lock);
1313*4882a593Smuzhiyun
1314*4882a593Smuzhiyun /* Copy the IDPROM ethernet address to the device structure, later we
1315*4882a593Smuzhiyun * will copy the address in the device structure to the lance
1316*4882a593Smuzhiyun * initialization block.
1317*4882a593Smuzhiyun */
1318*4882a593Smuzhiyun for (i = 0; i < 6; i++)
1319*4882a593Smuzhiyun dev->dev_addr[i] = idprom->id_ethaddr[i];
1320*4882a593Smuzhiyun
1321*4882a593Smuzhiyun /* Get the IO region */
1322*4882a593Smuzhiyun lp->lregs = of_ioremap(&op->resource[0], 0,
1323*4882a593Smuzhiyun LANCE_REG_SIZE, lancestr);
1324*4882a593Smuzhiyun if (!lp->lregs) {
1325*4882a593Smuzhiyun printk(KERN_ERR "SunLance: Cannot map registers.\n");
1326*4882a593Smuzhiyun goto fail;
1327*4882a593Smuzhiyun }
1328*4882a593Smuzhiyun
1329*4882a593Smuzhiyun lp->ledma = ledma;
1330*4882a593Smuzhiyun if (lp->ledma) {
1331*4882a593Smuzhiyun lp->dregs = of_ioremap(&ledma->resource[0], 0,
1332*4882a593Smuzhiyun resource_size(&ledma->resource[0]),
1333*4882a593Smuzhiyun "ledma");
1334*4882a593Smuzhiyun if (!lp->dregs) {
1335*4882a593Smuzhiyun printk(KERN_ERR "SunLance: Cannot map "
1336*4882a593Smuzhiyun "ledma registers.\n");
1337*4882a593Smuzhiyun goto fail;
1338*4882a593Smuzhiyun }
1339*4882a593Smuzhiyun }
1340*4882a593Smuzhiyun
1341*4882a593Smuzhiyun lp->op = op;
1342*4882a593Smuzhiyun lp->lebuffer = lebuffer;
1343*4882a593Smuzhiyun if (lebuffer) {
1344*4882a593Smuzhiyun /* sanity check */
1345*4882a593Smuzhiyun if (lebuffer->resource[0].start & 7) {
1346*4882a593Smuzhiyun printk(KERN_ERR "SunLance: ERROR: Rx and Tx rings not on even boundary.\n");
1347*4882a593Smuzhiyun goto fail;
1348*4882a593Smuzhiyun }
1349*4882a593Smuzhiyun lp->init_block_iomem =
1350*4882a593Smuzhiyun of_ioremap(&lebuffer->resource[0], 0,
1351*4882a593Smuzhiyun sizeof(struct lance_init_block), "lebuffer");
1352*4882a593Smuzhiyun if (!lp->init_block_iomem) {
1353*4882a593Smuzhiyun printk(KERN_ERR "SunLance: Cannot map PIO buffer.\n");
1354*4882a593Smuzhiyun goto fail;
1355*4882a593Smuzhiyun }
1356*4882a593Smuzhiyun lp->init_block_dvma = 0;
1357*4882a593Smuzhiyun lp->pio_buffer = 1;
1358*4882a593Smuzhiyun lp->init_ring = lance_init_ring_pio;
1359*4882a593Smuzhiyun lp->rx = lance_rx_pio;
1360*4882a593Smuzhiyun lp->tx = lance_tx_pio;
1361*4882a593Smuzhiyun } else {
1362*4882a593Smuzhiyun lp->init_block_mem =
1363*4882a593Smuzhiyun dma_alloc_coherent(&op->dev,
1364*4882a593Smuzhiyun sizeof(struct lance_init_block),
1365*4882a593Smuzhiyun &lp->init_block_dvma, GFP_ATOMIC);
1366*4882a593Smuzhiyun if (!lp->init_block_mem)
1367*4882a593Smuzhiyun goto fail;
1368*4882a593Smuzhiyun
1369*4882a593Smuzhiyun lp->pio_buffer = 0;
1370*4882a593Smuzhiyun lp->init_ring = lance_init_ring_dvma;
1371*4882a593Smuzhiyun lp->rx = lance_rx_dvma;
1372*4882a593Smuzhiyun lp->tx = lance_tx_dvma;
1373*4882a593Smuzhiyun }
1374*4882a593Smuzhiyun lp->busmaster_regval = of_getintprop_default(dp, "busmaster-regval",
1375*4882a593Smuzhiyun (LE_C3_BSWP |
1376*4882a593Smuzhiyun LE_C3_ACON |
1377*4882a593Smuzhiyun LE_C3_BCON));
1378*4882a593Smuzhiyun
1379*4882a593Smuzhiyun lp->name = lancestr;
1380*4882a593Smuzhiyun
1381*4882a593Smuzhiyun lp->burst_sizes = 0;
1382*4882a593Smuzhiyun if (lp->ledma) {
1383*4882a593Smuzhiyun struct device_node *ledma_dp = ledma->dev.of_node;
1384*4882a593Smuzhiyun struct device_node *sbus_dp;
1385*4882a593Smuzhiyun unsigned int sbmask;
1386*4882a593Smuzhiyun const char *prop;
1387*4882a593Smuzhiyun u32 csr;
1388*4882a593Smuzhiyun
1389*4882a593Smuzhiyun /* Find burst-size property for ledma */
1390*4882a593Smuzhiyun lp->burst_sizes = of_getintprop_default(ledma_dp,
1391*4882a593Smuzhiyun "burst-sizes", 0);
1392*4882a593Smuzhiyun
1393*4882a593Smuzhiyun /* ledma may be capable of fast bursts, but sbus may not. */
1394*4882a593Smuzhiyun sbus_dp = ledma_dp->parent;
1395*4882a593Smuzhiyun sbmask = of_getintprop_default(sbus_dp, "burst-sizes",
1396*4882a593Smuzhiyun DMA_BURSTBITS);
1397*4882a593Smuzhiyun lp->burst_sizes &= sbmask;
1398*4882a593Smuzhiyun
1399*4882a593Smuzhiyun /* Get the cable-selection property */
1400*4882a593Smuzhiyun prop = of_get_property(ledma_dp, "cable-selection", NULL);
1401*4882a593Smuzhiyun if (!prop || prop[0] == '\0') {
1402*4882a593Smuzhiyun struct device_node *nd;
1403*4882a593Smuzhiyun
1404*4882a593Smuzhiyun printk(KERN_INFO "SunLance: using "
1405*4882a593Smuzhiyun "auto-carrier-detection.\n");
1406*4882a593Smuzhiyun
1407*4882a593Smuzhiyun nd = of_find_node_by_path("/options");
1408*4882a593Smuzhiyun if (!nd)
1409*4882a593Smuzhiyun goto no_link_test;
1410*4882a593Smuzhiyun
1411*4882a593Smuzhiyun prop = of_get_property(nd, "tpe-link-test?", NULL);
1412*4882a593Smuzhiyun if (!prop)
1413*4882a593Smuzhiyun goto node_put;
1414*4882a593Smuzhiyun
1415*4882a593Smuzhiyun if (strcmp(prop, "true")) {
1416*4882a593Smuzhiyun printk(KERN_NOTICE "SunLance: warning: overriding option "
1417*4882a593Smuzhiyun "'tpe-link-test?'\n");
1418*4882a593Smuzhiyun printk(KERN_NOTICE "SunLance: warning: mail any problems "
1419*4882a593Smuzhiyun "to ecd@skynet.be\n");
1420*4882a593Smuzhiyun auxio_set_lte(AUXIO_LTE_ON);
1421*4882a593Smuzhiyun }
1422*4882a593Smuzhiyun node_put:
1423*4882a593Smuzhiyun of_node_put(nd);
1424*4882a593Smuzhiyun no_link_test:
1425*4882a593Smuzhiyun lp->auto_select = 1;
1426*4882a593Smuzhiyun lp->tpe = 0;
1427*4882a593Smuzhiyun } else if (!strcmp(prop, "aui")) {
1428*4882a593Smuzhiyun lp->auto_select = 0;
1429*4882a593Smuzhiyun lp->tpe = 0;
1430*4882a593Smuzhiyun } else {
1431*4882a593Smuzhiyun lp->auto_select = 0;
1432*4882a593Smuzhiyun lp->tpe = 1;
1433*4882a593Smuzhiyun }
1434*4882a593Smuzhiyun
1435*4882a593Smuzhiyun /* Reset ledma */
1436*4882a593Smuzhiyun csr = sbus_readl(lp->dregs + DMA_CSR);
1437*4882a593Smuzhiyun sbus_writel(csr | DMA_RST_ENET, lp->dregs + DMA_CSR);
1438*4882a593Smuzhiyun udelay(200);
1439*4882a593Smuzhiyun sbus_writel(csr & ~DMA_RST_ENET, lp->dregs + DMA_CSR);
1440*4882a593Smuzhiyun } else
1441*4882a593Smuzhiyun lp->dregs = NULL;
1442*4882a593Smuzhiyun
1443*4882a593Smuzhiyun lp->dev = dev;
1444*4882a593Smuzhiyun SET_NETDEV_DEV(dev, &op->dev);
1445*4882a593Smuzhiyun dev->watchdog_timeo = 5*HZ;
1446*4882a593Smuzhiyun dev->ethtool_ops = &sparc_lance_ethtool_ops;
1447*4882a593Smuzhiyun dev->netdev_ops = &sparc_lance_ops;
1448*4882a593Smuzhiyun
1449*4882a593Smuzhiyun dev->irq = op->archdata.irqs[0];
1450*4882a593Smuzhiyun
1451*4882a593Smuzhiyun /* We cannot sleep if the chip is busy during a
1452*4882a593Smuzhiyun * multicast list update event, because such events
1453*4882a593Smuzhiyun * can occur from interrupts (ex. IPv6). So we
1454*4882a593Smuzhiyun * use a timer to try again later when necessary. -DaveM
1455*4882a593Smuzhiyun */
1456*4882a593Smuzhiyun timer_setup(&lp->multicast_timer, lance_set_multicast_retry, 0);
1457*4882a593Smuzhiyun
1458*4882a593Smuzhiyun if (register_netdev(dev)) {
1459*4882a593Smuzhiyun printk(KERN_ERR "SunLance: Cannot register device.\n");
1460*4882a593Smuzhiyun goto fail;
1461*4882a593Smuzhiyun }
1462*4882a593Smuzhiyun
1463*4882a593Smuzhiyun platform_set_drvdata(op, lp);
1464*4882a593Smuzhiyun
1465*4882a593Smuzhiyun printk(KERN_INFO "%s: LANCE %pM\n",
1466*4882a593Smuzhiyun dev->name, dev->dev_addr);
1467*4882a593Smuzhiyun
1468*4882a593Smuzhiyun return 0;
1469*4882a593Smuzhiyun
1470*4882a593Smuzhiyun fail:
1471*4882a593Smuzhiyun lance_free_hwresources(lp);
1472*4882a593Smuzhiyun free_netdev(dev);
1473*4882a593Smuzhiyun return -ENODEV;
1474*4882a593Smuzhiyun }
1475*4882a593Smuzhiyun
sunlance_sbus_probe(struct platform_device * op)1476*4882a593Smuzhiyun static int sunlance_sbus_probe(struct platform_device *op)
1477*4882a593Smuzhiyun {
1478*4882a593Smuzhiyun struct platform_device *parent = to_platform_device(op->dev.parent);
1479*4882a593Smuzhiyun struct device_node *parent_dp = parent->dev.of_node;
1480*4882a593Smuzhiyun int err;
1481*4882a593Smuzhiyun
1482*4882a593Smuzhiyun if (of_node_name_eq(parent_dp, "ledma")) {
1483*4882a593Smuzhiyun err = sparc_lance_probe_one(op, parent, NULL);
1484*4882a593Smuzhiyun } else if (of_node_name_eq(parent_dp, "lebuffer")) {
1485*4882a593Smuzhiyun err = sparc_lance_probe_one(op, NULL, parent);
1486*4882a593Smuzhiyun } else
1487*4882a593Smuzhiyun err = sparc_lance_probe_one(op, NULL, NULL);
1488*4882a593Smuzhiyun
1489*4882a593Smuzhiyun return err;
1490*4882a593Smuzhiyun }
1491*4882a593Smuzhiyun
sunlance_sbus_remove(struct platform_device * op)1492*4882a593Smuzhiyun static int sunlance_sbus_remove(struct platform_device *op)
1493*4882a593Smuzhiyun {
1494*4882a593Smuzhiyun struct lance_private *lp = platform_get_drvdata(op);
1495*4882a593Smuzhiyun struct net_device *net_dev = lp->dev;
1496*4882a593Smuzhiyun
1497*4882a593Smuzhiyun unregister_netdev(net_dev);
1498*4882a593Smuzhiyun
1499*4882a593Smuzhiyun lance_free_hwresources(lp);
1500*4882a593Smuzhiyun
1501*4882a593Smuzhiyun free_netdev(net_dev);
1502*4882a593Smuzhiyun
1503*4882a593Smuzhiyun return 0;
1504*4882a593Smuzhiyun }
1505*4882a593Smuzhiyun
1506*4882a593Smuzhiyun static const struct of_device_id sunlance_sbus_match[] = {
1507*4882a593Smuzhiyun {
1508*4882a593Smuzhiyun .name = "le",
1509*4882a593Smuzhiyun },
1510*4882a593Smuzhiyun {},
1511*4882a593Smuzhiyun };
1512*4882a593Smuzhiyun
1513*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, sunlance_sbus_match);
1514*4882a593Smuzhiyun
1515*4882a593Smuzhiyun static struct platform_driver sunlance_sbus_driver = {
1516*4882a593Smuzhiyun .driver = {
1517*4882a593Smuzhiyun .name = "sunlance",
1518*4882a593Smuzhiyun .of_match_table = sunlance_sbus_match,
1519*4882a593Smuzhiyun },
1520*4882a593Smuzhiyun .probe = sunlance_sbus_probe,
1521*4882a593Smuzhiyun .remove = sunlance_sbus_remove,
1522*4882a593Smuzhiyun };
1523*4882a593Smuzhiyun
1524*4882a593Smuzhiyun module_platform_driver(sunlance_sbus_driver);
1525