1*4882a593Smuzhiyun /* am7990 (lance) definitions 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * This is an extension to the Linux operating system, and is covered by 4*4882a593Smuzhiyun * same GNU General Public License that covers that work. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Michael Hipp 7*4882a593Smuzhiyun * email: mhipp@student.uni-tuebingen.de 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * sources: (mail me or ask archie if you need them) 10*4882a593Smuzhiyun * crynwr-packet-driver 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * Control and Status Register 0 (CSR0) bit definitions 15*4882a593Smuzhiyun * (R=Readable) (W=Writeable) (S=Set on write) (C-Clear on write) 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define CSR0_ERR 0x8000 /* Error summary (R) */ 20*4882a593Smuzhiyun #define CSR0_BABL 0x4000 /* Babble transmitter timeout error (RC) */ 21*4882a593Smuzhiyun #define CSR0_CERR 0x2000 /* Collision Error (RC) */ 22*4882a593Smuzhiyun #define CSR0_MISS 0x1000 /* Missed packet (RC) */ 23*4882a593Smuzhiyun #define CSR0_MERR 0x0800 /* Memory Error (RC) */ 24*4882a593Smuzhiyun #define CSR0_RINT 0x0400 /* Receiver Interrupt (RC) */ 25*4882a593Smuzhiyun #define CSR0_TINT 0x0200 /* Transmit Interrupt (RC) */ 26*4882a593Smuzhiyun #define CSR0_IDON 0x0100 /* Initialization Done (RC) */ 27*4882a593Smuzhiyun #define CSR0_INTR 0x0080 /* Interrupt Flag (R) */ 28*4882a593Smuzhiyun #define CSR0_INEA 0x0040 /* Interrupt Enable (RW) */ 29*4882a593Smuzhiyun #define CSR0_RXON 0x0020 /* Receiver on (R) */ 30*4882a593Smuzhiyun #define CSR0_TXON 0x0010 /* Transmitter on (R) */ 31*4882a593Smuzhiyun #define CSR0_TDMD 0x0008 /* Transmit Demand (RS) */ 32*4882a593Smuzhiyun #define CSR0_STOP 0x0004 /* Stop (RS) */ 33*4882a593Smuzhiyun #define CSR0_STRT 0x0002 /* Start (RS) */ 34*4882a593Smuzhiyun #define CSR0_INIT 0x0001 /* Initialize (RS) */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define CSR0_CLRALL 0x7f00 /* mask for all clearable bits */ 37*4882a593Smuzhiyun /* 38*4882a593Smuzhiyun * Initialization Block Mode operation Bit Definitions. 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define M_PROM 0x8000 /* Promiscuous Mode */ 42*4882a593Smuzhiyun #define M_INTL 0x0040 /* Internal Loopback */ 43*4882a593Smuzhiyun #define M_DRTY 0x0020 /* Disable Retry */ 44*4882a593Smuzhiyun #define M_COLL 0x0010 /* Force Collision */ 45*4882a593Smuzhiyun #define M_DTCR 0x0008 /* Disable Transmit CRC) */ 46*4882a593Smuzhiyun #define M_LOOP 0x0004 /* Loopback */ 47*4882a593Smuzhiyun #define M_DTX 0x0002 /* Disable the Transmitter */ 48*4882a593Smuzhiyun #define M_DRX 0x0001 /* Disable the Receiver */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * Receive message descriptor bit definitions. 53*4882a593Smuzhiyun */ 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define RCV_OWN 0x80 /* owner bit 0 = host, 1 = lance */ 56*4882a593Smuzhiyun #define RCV_ERR 0x40 /* Error Summary */ 57*4882a593Smuzhiyun #define RCV_FRAM 0x20 /* Framing Error */ 58*4882a593Smuzhiyun #define RCV_OFLO 0x10 /* Overflow Error */ 59*4882a593Smuzhiyun #define RCV_CRC 0x08 /* CRC Error */ 60*4882a593Smuzhiyun #define RCV_BUF_ERR 0x04 /* Buffer Error */ 61*4882a593Smuzhiyun #define RCV_START 0x02 /* Start of Packet */ 62*4882a593Smuzhiyun #define RCV_END 0x01 /* End of Packet */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* 66*4882a593Smuzhiyun * Transmit message descriptor bit definitions. 67*4882a593Smuzhiyun */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define XMIT_OWN 0x80 /* owner bit 0 = host, 1 = lance */ 70*4882a593Smuzhiyun #define XMIT_ERR 0x40 /* Error Summary */ 71*4882a593Smuzhiyun #define XMIT_RETRY 0x10 /* more the 1 retry needed to Xmit */ 72*4882a593Smuzhiyun #define XMIT_1_RETRY 0x08 /* one retry needed to Xmit */ 73*4882a593Smuzhiyun #define XMIT_DEF 0x04 /* Deferred */ 74*4882a593Smuzhiyun #define XMIT_START 0x02 /* Start of Packet */ 75*4882a593Smuzhiyun #define XMIT_END 0x01 /* End of Packet */ 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* 78*4882a593Smuzhiyun * transmit status (2) (valid if XMIT_ERR == 1) 79*4882a593Smuzhiyun */ 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define XMIT_TDRMASK 0x03ff /* time-domain-reflectometer-value */ 82*4882a593Smuzhiyun #define XMIT_RTRY 0x0400 /* Failed after 16 retransmissions */ 83*4882a593Smuzhiyun #define XMIT_LCAR 0x0800 /* Loss of Carrier */ 84*4882a593Smuzhiyun #define XMIT_LCOL 0x1000 /* Late collision */ 85*4882a593Smuzhiyun #define XMIT_RESERV 0x2000 /* Reserved */ 86*4882a593Smuzhiyun #define XMIT_UFLO 0x4000 /* Underflow (late memory) */ 87*4882a593Smuzhiyun #define XMIT_BUFF 0x8000 /* Buffering error (no ENP) */ 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun struct init_block { 90*4882a593Smuzhiyun unsigned short mode; 91*4882a593Smuzhiyun unsigned char eaddr[6]; 92*4882a593Smuzhiyun unsigned char filter[8]; 93*4882a593Smuzhiyun /* bit 29-31: number of rmd's (power of 2) */ 94*4882a593Smuzhiyun u32 rrp; /* receive ring pointer (align 8) */ 95*4882a593Smuzhiyun /* bit 29-31: number of tmd's (power of 2) */ 96*4882a593Smuzhiyun u32 trp; /* transmit ring pointer (align 8) */ 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun struct rmd { /* Receive Message Descriptor */ 100*4882a593Smuzhiyun union { 101*4882a593Smuzhiyun volatile u32 buffer; 102*4882a593Smuzhiyun struct { 103*4882a593Smuzhiyun volatile unsigned char dummy[3]; 104*4882a593Smuzhiyun volatile unsigned char status; 105*4882a593Smuzhiyun } s; 106*4882a593Smuzhiyun } u; 107*4882a593Smuzhiyun volatile short blen; 108*4882a593Smuzhiyun volatile unsigned short mlen; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun struct tmd { 112*4882a593Smuzhiyun union { 113*4882a593Smuzhiyun volatile u32 buffer; 114*4882a593Smuzhiyun struct { 115*4882a593Smuzhiyun volatile unsigned char dummy[3]; 116*4882a593Smuzhiyun volatile unsigned char status; 117*4882a593Smuzhiyun } s; 118*4882a593Smuzhiyun } u; 119*4882a593Smuzhiyun volatile unsigned short blen; 120*4882a593Smuzhiyun volatile unsigned short status2; 121*4882a593Smuzhiyun }; 122