1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * ni6510 (am7990 'lance' chip) driver for Linux-net-3
3*4882a593Smuzhiyun * BETAcode v0.71 (96/09/29) for 2.0.0 (or later)
4*4882a593Smuzhiyun * copyrights (c) 1994,1995,1996 by M.Hipp
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This driver can handle the old ni6510 board and the newer ni6510
7*4882a593Smuzhiyun * EtherBlaster. (probably it also works with every full NE2100
8*4882a593Smuzhiyun * compatible card)
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * driver probes: io: 0x360,0x300,0x320,0x340 / dma: 3,5,6,7
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * This is an extension to the Linux operating system, and is covered by the
13*4882a593Smuzhiyun * same GNU General Public License that covers the Linux-kernel.
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * comments/bugs/suggestions can be sent to:
16*4882a593Smuzhiyun * Michael Hipp
17*4882a593Smuzhiyun * email: hippm@informatik.uni-tuebingen.de
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * sources:
20*4882a593Smuzhiyun * some things are from the 'ni6510-packet-driver for dos by Russ Nelson'
21*4882a593Smuzhiyun * and from the original drivers by D.Becker
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * known problems:
24*4882a593Smuzhiyun * - on some PCI boards (including my own) the card/board/ISA-bridge has
25*4882a593Smuzhiyun * problems with bus master DMA. This results in lotsa overruns.
26*4882a593Smuzhiyun * It may help to '#define RCV_PARANOIA_CHECK' or try to #undef
27*4882a593Smuzhiyun * the XMT and RCV_VIA_SKB option .. this reduces driver performance.
28*4882a593Smuzhiyun * Or just play with your BIOS options to optimize ISA-DMA access.
29*4882a593Smuzhiyun * Maybe you also wanna play with the LOW_PERFORAMCE and MID_PERFORMANCE
30*4882a593Smuzhiyun * defines -> please report me your experience then
31*4882a593Smuzhiyun * - Harald reported for ASUS SP3G mainboards, that you should use
32*4882a593Smuzhiyun * the 'optimal settings' from the user's manual on page 3-12!
33*4882a593Smuzhiyun *
34*4882a593Smuzhiyun * credits:
35*4882a593Smuzhiyun * thanx to Jason Sullivan for sending me a ni6510 card!
36*4882a593Smuzhiyun * lot of debug runs with ASUS SP3G Boards (Intel Saturn) by Harald Koenig
37*4882a593Smuzhiyun *
38*4882a593Smuzhiyun * simple performance test: (486DX-33/Ni6510-EB receives from 486DX4-100/Ni6510-EB)
39*4882a593Smuzhiyun * average: FTP -> 8384421 bytes received in 8.5 seconds
40*4882a593Smuzhiyun * (no RCV_VIA_SKB,no XMT_VIA_SKB,PARANOIA_CHECK,4 XMIT BUFS, 8 RCV_BUFFS)
41*4882a593Smuzhiyun * peak: FTP -> 8384421 bytes received in 7.5 seconds
42*4882a593Smuzhiyun * (RCV_VIA_SKB,XMT_VIA_SKB,no PARANOIA_CHECK,1(!) XMIT BUF, 16 RCV BUFFS)
43*4882a593Smuzhiyun */
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /*
46*4882a593Smuzhiyun * 99.Jun.8: added support for /proc/net/dev byte count for xosview (HK)
47*4882a593Smuzhiyun * 96.Sept.29: virt_to_bus stuff added for new memory modell
48*4882a593Smuzhiyun * 96.April.29: Added Harald Koenig's Patches (MH)
49*4882a593Smuzhiyun * 96.April.13: enhanced error handling .. more tests (MH)
50*4882a593Smuzhiyun * 96.April.5/6: a lot of performance tests. Got it stable now (hopefully) (MH)
51*4882a593Smuzhiyun * 96.April.1: (no joke ;) .. added EtherBlaster and Module support (MH)
52*4882a593Smuzhiyun * 96.Feb.19: fixed a few bugs .. cleanups .. tested for 1.3.66 (MH)
53*4882a593Smuzhiyun * hopefully no more 16MB limit
54*4882a593Smuzhiyun *
55*4882a593Smuzhiyun * 95.Nov.18: multicast tweaked (AC).
56*4882a593Smuzhiyun *
57*4882a593Smuzhiyun * 94.Aug.22: changes in xmit_intr (ack more than one xmitted-packet), ni65_send_packet (p->lock) (MH)
58*4882a593Smuzhiyun *
59*4882a593Smuzhiyun * 94.July.16: fixed bugs in recv_skb and skb-alloc stuff (MH)
60*4882a593Smuzhiyun */
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun #include <linux/kernel.h>
63*4882a593Smuzhiyun #include <linux/string.h>
64*4882a593Smuzhiyun #include <linux/errno.h>
65*4882a593Smuzhiyun #include <linux/ioport.h>
66*4882a593Smuzhiyun #include <linux/slab.h>
67*4882a593Smuzhiyun #include <linux/interrupt.h>
68*4882a593Smuzhiyun #include <linux/delay.h>
69*4882a593Smuzhiyun #include <linux/init.h>
70*4882a593Smuzhiyun #include <linux/netdevice.h>
71*4882a593Smuzhiyun #include <linux/etherdevice.h>
72*4882a593Smuzhiyun #include <linux/skbuff.h>
73*4882a593Smuzhiyun #include <linux/module.h>
74*4882a593Smuzhiyun #include <linux/bitops.h>
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun #include <asm/io.h>
77*4882a593Smuzhiyun #include <asm/dma.h>
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun #include "ni65.h"
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /*
82*4882a593Smuzhiyun * the current setting allows an acceptable performance
83*4882a593Smuzhiyun * for 'RCV_PARANOIA_CHECK' read the 'known problems' part in
84*4882a593Smuzhiyun * the header of this file
85*4882a593Smuzhiyun * 'invert' the defines for max. performance. This may cause DMA problems
86*4882a593Smuzhiyun * on some boards (e.g on my ASUS SP3G)
87*4882a593Smuzhiyun */
88*4882a593Smuzhiyun #undef XMT_VIA_SKB
89*4882a593Smuzhiyun #undef RCV_VIA_SKB
90*4882a593Smuzhiyun #define RCV_PARANOIA_CHECK
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun #define MID_PERFORMANCE
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun #if defined( LOW_PERFORMANCE )
95*4882a593Smuzhiyun static int isa0=7,isa1=7,csr80=0x0c10;
96*4882a593Smuzhiyun #elif defined( MID_PERFORMANCE )
97*4882a593Smuzhiyun static int isa0=5,isa1=5,csr80=0x2810;
98*4882a593Smuzhiyun #else /* high performance */
99*4882a593Smuzhiyun static int isa0=4,isa1=4,csr80=0x0017;
100*4882a593Smuzhiyun #endif
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /*
103*4882a593Smuzhiyun * a few card/vendor specific defines
104*4882a593Smuzhiyun */
105*4882a593Smuzhiyun #define NI65_ID0 0x00
106*4882a593Smuzhiyun #define NI65_ID1 0x55
107*4882a593Smuzhiyun #define NI65_EB_ID0 0x52
108*4882a593Smuzhiyun #define NI65_EB_ID1 0x44
109*4882a593Smuzhiyun #define NE2100_ID0 0x57
110*4882a593Smuzhiyun #define NE2100_ID1 0x57
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun #define PORT p->cmdr_addr
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /*
115*4882a593Smuzhiyun * buffer configuration
116*4882a593Smuzhiyun */
117*4882a593Smuzhiyun #if 1
118*4882a593Smuzhiyun #define RMDNUM 16
119*4882a593Smuzhiyun #define RMDNUMMASK 0x80000000
120*4882a593Smuzhiyun #else
121*4882a593Smuzhiyun #define RMDNUM 8
122*4882a593Smuzhiyun #define RMDNUMMASK 0x60000000 /* log2(RMDNUM)<<29 */
123*4882a593Smuzhiyun #endif
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun #if 0
126*4882a593Smuzhiyun #define TMDNUM 1
127*4882a593Smuzhiyun #define TMDNUMMASK 0x00000000
128*4882a593Smuzhiyun #else
129*4882a593Smuzhiyun #define TMDNUM 4
130*4882a593Smuzhiyun #define TMDNUMMASK 0x40000000 /* log2(TMDNUM)<<29 */
131*4882a593Smuzhiyun #endif
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun /* slightly oversized */
134*4882a593Smuzhiyun #define R_BUF_SIZE 1544
135*4882a593Smuzhiyun #define T_BUF_SIZE 1544
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun /*
138*4882a593Smuzhiyun * lance register defines
139*4882a593Smuzhiyun */
140*4882a593Smuzhiyun #define L_DATAREG 0x00
141*4882a593Smuzhiyun #define L_ADDRREG 0x02
142*4882a593Smuzhiyun #define L_RESET 0x04
143*4882a593Smuzhiyun #define L_CONFIG 0x05
144*4882a593Smuzhiyun #define L_BUSIF 0x06
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun /*
147*4882a593Smuzhiyun * to access the lance/am7990-regs, you have to write
148*4882a593Smuzhiyun * reg-number into L_ADDRREG, then you can access it using L_DATAREG
149*4882a593Smuzhiyun */
150*4882a593Smuzhiyun #define CSR0 0x00
151*4882a593Smuzhiyun #define CSR1 0x01
152*4882a593Smuzhiyun #define CSR2 0x02
153*4882a593Smuzhiyun #define CSR3 0x03
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun #define INIT_RING_BEFORE_START 0x1
156*4882a593Smuzhiyun #define FULL_RESET_ON_ERROR 0x2
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun #if 0
159*4882a593Smuzhiyun #define writereg(val,reg) {outw(reg,PORT+L_ADDRREG);inw(PORT+L_ADDRREG); \
160*4882a593Smuzhiyun outw(val,PORT+L_DATAREG);inw(PORT+L_DATAREG);}
161*4882a593Smuzhiyun #define readreg(reg) (outw(reg,PORT+L_ADDRREG),inw(PORT+L_ADDRREG),\
162*4882a593Smuzhiyun inw(PORT+L_DATAREG))
163*4882a593Smuzhiyun #if 0
164*4882a593Smuzhiyun #define writedatareg(val) {outw(val,PORT+L_DATAREG);inw(PORT+L_DATAREG);}
165*4882a593Smuzhiyun #else
166*4882a593Smuzhiyun #define writedatareg(val) { writereg(val,CSR0); }
167*4882a593Smuzhiyun #endif
168*4882a593Smuzhiyun #else
169*4882a593Smuzhiyun #define writereg(val,reg) {outw(reg,PORT+L_ADDRREG);outw(val,PORT+L_DATAREG);}
170*4882a593Smuzhiyun #define readreg(reg) (outw(reg,PORT+L_ADDRREG),inw(PORT+L_DATAREG))
171*4882a593Smuzhiyun #define writedatareg(val) { writereg(val,CSR0); }
172*4882a593Smuzhiyun #endif
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun static unsigned char ni_vendor[] = { 0x02,0x07,0x01 };
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun static struct card {
177*4882a593Smuzhiyun unsigned char id0,id1;
178*4882a593Smuzhiyun short id_offset;
179*4882a593Smuzhiyun short total_size;
180*4882a593Smuzhiyun short cmd_offset;
181*4882a593Smuzhiyun short addr_offset;
182*4882a593Smuzhiyun unsigned char *vendor_id;
183*4882a593Smuzhiyun char *cardname;
184*4882a593Smuzhiyun unsigned long config;
185*4882a593Smuzhiyun } cards[] = {
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun .id0 = NI65_ID0,
188*4882a593Smuzhiyun .id1 = NI65_ID1,
189*4882a593Smuzhiyun .id_offset = 0x0e,
190*4882a593Smuzhiyun .total_size = 0x10,
191*4882a593Smuzhiyun .cmd_offset = 0x0,
192*4882a593Smuzhiyun .addr_offset = 0x8,
193*4882a593Smuzhiyun .vendor_id = ni_vendor,
194*4882a593Smuzhiyun .cardname = "ni6510",
195*4882a593Smuzhiyun .config = 0x1,
196*4882a593Smuzhiyun },
197*4882a593Smuzhiyun {
198*4882a593Smuzhiyun .id0 = NI65_EB_ID0,
199*4882a593Smuzhiyun .id1 = NI65_EB_ID1,
200*4882a593Smuzhiyun .id_offset = 0x0e,
201*4882a593Smuzhiyun .total_size = 0x18,
202*4882a593Smuzhiyun .cmd_offset = 0x10,
203*4882a593Smuzhiyun .addr_offset = 0x0,
204*4882a593Smuzhiyun .vendor_id = ni_vendor,
205*4882a593Smuzhiyun .cardname = "ni6510 EtherBlaster",
206*4882a593Smuzhiyun .config = 0x2,
207*4882a593Smuzhiyun },
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun .id0 = NE2100_ID0,
210*4882a593Smuzhiyun .id1 = NE2100_ID1,
211*4882a593Smuzhiyun .id_offset = 0x0e,
212*4882a593Smuzhiyun .total_size = 0x18,
213*4882a593Smuzhiyun .cmd_offset = 0x10,
214*4882a593Smuzhiyun .addr_offset = 0x0,
215*4882a593Smuzhiyun .vendor_id = NULL,
216*4882a593Smuzhiyun .cardname = "generic NE2100",
217*4882a593Smuzhiyun .config = 0x0,
218*4882a593Smuzhiyun },
219*4882a593Smuzhiyun };
220*4882a593Smuzhiyun #define NUM_CARDS 3
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun struct priv
223*4882a593Smuzhiyun {
224*4882a593Smuzhiyun struct rmd rmdhead[RMDNUM];
225*4882a593Smuzhiyun struct tmd tmdhead[TMDNUM];
226*4882a593Smuzhiyun struct init_block ib;
227*4882a593Smuzhiyun int rmdnum;
228*4882a593Smuzhiyun int tmdnum,tmdlast;
229*4882a593Smuzhiyun #ifdef RCV_VIA_SKB
230*4882a593Smuzhiyun struct sk_buff *recv_skb[RMDNUM];
231*4882a593Smuzhiyun #else
232*4882a593Smuzhiyun void *recvbounce[RMDNUM];
233*4882a593Smuzhiyun #endif
234*4882a593Smuzhiyun #ifdef XMT_VIA_SKB
235*4882a593Smuzhiyun struct sk_buff *tmd_skb[TMDNUM];
236*4882a593Smuzhiyun #endif
237*4882a593Smuzhiyun void *tmdbounce[TMDNUM];
238*4882a593Smuzhiyun int tmdbouncenum;
239*4882a593Smuzhiyun int lock,xmit_queued;
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun void *self;
242*4882a593Smuzhiyun int cmdr_addr;
243*4882a593Smuzhiyun int cardno;
244*4882a593Smuzhiyun int features;
245*4882a593Smuzhiyun spinlock_t ring_lock;
246*4882a593Smuzhiyun };
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun static int ni65_probe1(struct net_device *dev,int);
249*4882a593Smuzhiyun static irqreturn_t ni65_interrupt(int irq, void * dev_id);
250*4882a593Smuzhiyun static void ni65_recv_intr(struct net_device *dev,int);
251*4882a593Smuzhiyun static void ni65_xmit_intr(struct net_device *dev,int);
252*4882a593Smuzhiyun static int ni65_open(struct net_device *dev);
253*4882a593Smuzhiyun static int ni65_lance_reinit(struct net_device *dev);
254*4882a593Smuzhiyun static void ni65_init_lance(struct priv *p,unsigned char*,int,int);
255*4882a593Smuzhiyun static netdev_tx_t ni65_send_packet(struct sk_buff *skb,
256*4882a593Smuzhiyun struct net_device *dev);
257*4882a593Smuzhiyun static void ni65_timeout(struct net_device *dev, unsigned int txqueue);
258*4882a593Smuzhiyun static int ni65_close(struct net_device *dev);
259*4882a593Smuzhiyun static int ni65_alloc_buffer(struct net_device *dev);
260*4882a593Smuzhiyun static void ni65_free_buffer(struct priv *p);
261*4882a593Smuzhiyun static void set_multicast_list(struct net_device *dev);
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun static int irqtab[] __initdata = { 9,12,15,5 }; /* irq config-translate */
264*4882a593Smuzhiyun static int dmatab[] __initdata = { 0,3,5,6,7 }; /* dma config-translate and autodetect */
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun static int debuglevel = 1;
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun /*
269*4882a593Smuzhiyun * set 'performance' registers .. we must STOP lance for that
270*4882a593Smuzhiyun */
ni65_set_performance(struct priv * p)271*4882a593Smuzhiyun static void ni65_set_performance(struct priv *p)
272*4882a593Smuzhiyun {
273*4882a593Smuzhiyun writereg(CSR0_STOP | CSR0_CLRALL,CSR0); /* STOP */
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun if( !(cards[p->cardno].config & 0x02) )
276*4882a593Smuzhiyun return;
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun outw(80,PORT+L_ADDRREG);
279*4882a593Smuzhiyun if(inw(PORT+L_ADDRREG) != 80)
280*4882a593Smuzhiyun return;
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun writereg( (csr80 & 0x3fff) ,80); /* FIFO watermarks */
283*4882a593Smuzhiyun outw(0,PORT+L_ADDRREG);
284*4882a593Smuzhiyun outw((short)isa0,PORT+L_BUSIF); /* write ISA 0: DMA_R : isa0 * 50ns */
285*4882a593Smuzhiyun outw(1,PORT+L_ADDRREG);
286*4882a593Smuzhiyun outw((short)isa1,PORT+L_BUSIF); /* write ISA 1: DMA_W : isa1 * 50ns */
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun outw(CSR0,PORT+L_ADDRREG); /* switch back to CSR0 */
289*4882a593Smuzhiyun }
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun /*
292*4882a593Smuzhiyun * open interface (up)
293*4882a593Smuzhiyun */
ni65_open(struct net_device * dev)294*4882a593Smuzhiyun static int ni65_open(struct net_device *dev)
295*4882a593Smuzhiyun {
296*4882a593Smuzhiyun struct priv *p = dev->ml_priv;
297*4882a593Smuzhiyun int irqval = request_irq(dev->irq, ni65_interrupt,0,
298*4882a593Smuzhiyun cards[p->cardno].cardname,dev);
299*4882a593Smuzhiyun if (irqval) {
300*4882a593Smuzhiyun printk(KERN_ERR "%s: unable to get IRQ %d (irqval=%d).\n",
301*4882a593Smuzhiyun dev->name,dev->irq, irqval);
302*4882a593Smuzhiyun return -EAGAIN;
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun if(ni65_lance_reinit(dev))
306*4882a593Smuzhiyun {
307*4882a593Smuzhiyun netif_start_queue(dev);
308*4882a593Smuzhiyun return 0;
309*4882a593Smuzhiyun }
310*4882a593Smuzhiyun else
311*4882a593Smuzhiyun {
312*4882a593Smuzhiyun free_irq(dev->irq,dev);
313*4882a593Smuzhiyun return -EAGAIN;
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun }
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun /*
318*4882a593Smuzhiyun * close interface (down)
319*4882a593Smuzhiyun */
ni65_close(struct net_device * dev)320*4882a593Smuzhiyun static int ni65_close(struct net_device *dev)
321*4882a593Smuzhiyun {
322*4882a593Smuzhiyun struct priv *p = dev->ml_priv;
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun netif_stop_queue(dev);
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun outw(inw(PORT+L_RESET),PORT+L_RESET); /* that's the hard way */
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun #ifdef XMT_VIA_SKB
329*4882a593Smuzhiyun {
330*4882a593Smuzhiyun int i;
331*4882a593Smuzhiyun for(i=0;i<TMDNUM;i++)
332*4882a593Smuzhiyun {
333*4882a593Smuzhiyun if(p->tmd_skb[i]) {
334*4882a593Smuzhiyun dev_kfree_skb(p->tmd_skb[i]);
335*4882a593Smuzhiyun p->tmd_skb[i] = NULL;
336*4882a593Smuzhiyun }
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun }
339*4882a593Smuzhiyun #endif
340*4882a593Smuzhiyun free_irq(dev->irq,dev);
341*4882a593Smuzhiyun return 0;
342*4882a593Smuzhiyun }
343*4882a593Smuzhiyun
cleanup_card(struct net_device * dev)344*4882a593Smuzhiyun static void cleanup_card(struct net_device *dev)
345*4882a593Smuzhiyun {
346*4882a593Smuzhiyun struct priv *p = dev->ml_priv;
347*4882a593Smuzhiyun disable_dma(dev->dma);
348*4882a593Smuzhiyun free_dma(dev->dma);
349*4882a593Smuzhiyun release_region(dev->base_addr, cards[p->cardno].total_size);
350*4882a593Smuzhiyun ni65_free_buffer(p);
351*4882a593Smuzhiyun }
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun /* set: io,irq,dma or set it when calling insmod */
354*4882a593Smuzhiyun static int irq;
355*4882a593Smuzhiyun static int io;
356*4882a593Smuzhiyun static int dma;
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun /*
359*4882a593Smuzhiyun * Probe The Card (not the lance-chip)
360*4882a593Smuzhiyun */
ni65_probe(int unit)361*4882a593Smuzhiyun struct net_device * __init ni65_probe(int unit)
362*4882a593Smuzhiyun {
363*4882a593Smuzhiyun struct net_device *dev = alloc_etherdev(0);
364*4882a593Smuzhiyun static const int ports[] = { 0x360, 0x300, 0x320, 0x340, 0 };
365*4882a593Smuzhiyun const int *port;
366*4882a593Smuzhiyun int err = 0;
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun if (!dev)
369*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun if (unit >= 0) {
372*4882a593Smuzhiyun sprintf(dev->name, "eth%d", unit);
373*4882a593Smuzhiyun netdev_boot_setup_check(dev);
374*4882a593Smuzhiyun irq = dev->irq;
375*4882a593Smuzhiyun dma = dev->dma;
376*4882a593Smuzhiyun } else {
377*4882a593Smuzhiyun dev->base_addr = io;
378*4882a593Smuzhiyun }
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun if (dev->base_addr > 0x1ff) { /* Check a single specified location. */
381*4882a593Smuzhiyun err = ni65_probe1(dev, dev->base_addr);
382*4882a593Smuzhiyun } else if (dev->base_addr > 0) { /* Don't probe at all. */
383*4882a593Smuzhiyun err = -ENXIO;
384*4882a593Smuzhiyun } else {
385*4882a593Smuzhiyun for (port = ports; *port && ni65_probe1(dev, *port); port++)
386*4882a593Smuzhiyun ;
387*4882a593Smuzhiyun if (!*port)
388*4882a593Smuzhiyun err = -ENODEV;
389*4882a593Smuzhiyun }
390*4882a593Smuzhiyun if (err)
391*4882a593Smuzhiyun goto out;
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun err = register_netdev(dev);
394*4882a593Smuzhiyun if (err)
395*4882a593Smuzhiyun goto out1;
396*4882a593Smuzhiyun return dev;
397*4882a593Smuzhiyun out1:
398*4882a593Smuzhiyun cleanup_card(dev);
399*4882a593Smuzhiyun out:
400*4882a593Smuzhiyun free_netdev(dev);
401*4882a593Smuzhiyun return ERR_PTR(err);
402*4882a593Smuzhiyun }
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun static const struct net_device_ops ni65_netdev_ops = {
405*4882a593Smuzhiyun .ndo_open = ni65_open,
406*4882a593Smuzhiyun .ndo_stop = ni65_close,
407*4882a593Smuzhiyun .ndo_start_xmit = ni65_send_packet,
408*4882a593Smuzhiyun .ndo_tx_timeout = ni65_timeout,
409*4882a593Smuzhiyun .ndo_set_rx_mode = set_multicast_list,
410*4882a593Smuzhiyun .ndo_set_mac_address = eth_mac_addr,
411*4882a593Smuzhiyun .ndo_validate_addr = eth_validate_addr,
412*4882a593Smuzhiyun };
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun /*
415*4882a593Smuzhiyun * this is the real card probe ..
416*4882a593Smuzhiyun */
ni65_probe1(struct net_device * dev,int ioaddr)417*4882a593Smuzhiyun static int __init ni65_probe1(struct net_device *dev,int ioaddr)
418*4882a593Smuzhiyun {
419*4882a593Smuzhiyun int i,j;
420*4882a593Smuzhiyun struct priv *p;
421*4882a593Smuzhiyun unsigned long flags;
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun dev->irq = irq;
424*4882a593Smuzhiyun dev->dma = dma;
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun for(i=0;i<NUM_CARDS;i++) {
427*4882a593Smuzhiyun if(!request_region(ioaddr, cards[i].total_size, cards[i].cardname))
428*4882a593Smuzhiyun continue;
429*4882a593Smuzhiyun if(cards[i].id_offset >= 0) {
430*4882a593Smuzhiyun if(inb(ioaddr+cards[i].id_offset+0) != cards[i].id0 ||
431*4882a593Smuzhiyun inb(ioaddr+cards[i].id_offset+1) != cards[i].id1) {
432*4882a593Smuzhiyun release_region(ioaddr, cards[i].total_size);
433*4882a593Smuzhiyun continue;
434*4882a593Smuzhiyun }
435*4882a593Smuzhiyun }
436*4882a593Smuzhiyun if(cards[i].vendor_id) {
437*4882a593Smuzhiyun for(j=0;j<3;j++)
438*4882a593Smuzhiyun if(inb(ioaddr+cards[i].addr_offset+j) != cards[i].vendor_id[j])
439*4882a593Smuzhiyun release_region(ioaddr, cards[i].total_size);
440*4882a593Smuzhiyun }
441*4882a593Smuzhiyun break;
442*4882a593Smuzhiyun }
443*4882a593Smuzhiyun if(i == NUM_CARDS)
444*4882a593Smuzhiyun return -ENODEV;
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun for(j=0;j<6;j++)
447*4882a593Smuzhiyun dev->dev_addr[j] = inb(ioaddr+cards[i].addr_offset+j);
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun if( (j=ni65_alloc_buffer(dev)) < 0) {
450*4882a593Smuzhiyun release_region(ioaddr, cards[i].total_size);
451*4882a593Smuzhiyun return j;
452*4882a593Smuzhiyun }
453*4882a593Smuzhiyun p = dev->ml_priv;
454*4882a593Smuzhiyun p->cmdr_addr = ioaddr + cards[i].cmd_offset;
455*4882a593Smuzhiyun p->cardno = i;
456*4882a593Smuzhiyun spin_lock_init(&p->ring_lock);
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun printk(KERN_INFO "%s: %s found at %#3x, ", dev->name, cards[p->cardno].cardname , ioaddr);
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun outw(inw(PORT+L_RESET),PORT+L_RESET); /* first: reset the card */
461*4882a593Smuzhiyun if( (j=readreg(CSR0)) != 0x4) {
462*4882a593Smuzhiyun printk("failed.\n");
463*4882a593Smuzhiyun printk(KERN_ERR "%s: Can't RESET card: %04x\n", dev->name, j);
464*4882a593Smuzhiyun ni65_free_buffer(p);
465*4882a593Smuzhiyun release_region(ioaddr, cards[p->cardno].total_size);
466*4882a593Smuzhiyun return -EAGAIN;
467*4882a593Smuzhiyun }
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun outw(88,PORT+L_ADDRREG);
470*4882a593Smuzhiyun if(inw(PORT+L_ADDRREG) == 88) {
471*4882a593Smuzhiyun unsigned long v;
472*4882a593Smuzhiyun v = inw(PORT+L_DATAREG);
473*4882a593Smuzhiyun v <<= 16;
474*4882a593Smuzhiyun outw(89,PORT+L_ADDRREG);
475*4882a593Smuzhiyun v |= inw(PORT+L_DATAREG);
476*4882a593Smuzhiyun printk("Version %#08lx, ",v);
477*4882a593Smuzhiyun p->features = INIT_RING_BEFORE_START;
478*4882a593Smuzhiyun }
479*4882a593Smuzhiyun else {
480*4882a593Smuzhiyun printk("ancient LANCE, ");
481*4882a593Smuzhiyun p->features = 0x0;
482*4882a593Smuzhiyun }
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun if(test_bit(0,&cards[i].config)) {
485*4882a593Smuzhiyun dev->irq = irqtab[(inw(ioaddr+L_CONFIG)>>2)&3];
486*4882a593Smuzhiyun dev->dma = dmatab[inw(ioaddr+L_CONFIG)&3];
487*4882a593Smuzhiyun printk("IRQ %d (from card), DMA %d (from card).\n",dev->irq,dev->dma);
488*4882a593Smuzhiyun }
489*4882a593Smuzhiyun else {
490*4882a593Smuzhiyun if(dev->dma == 0) {
491*4882a593Smuzhiyun /* 'stuck test' from lance.c */
492*4882a593Smuzhiyun unsigned long dma_channels =
493*4882a593Smuzhiyun ((inb(DMA1_STAT_REG) >> 4) & 0x0f)
494*4882a593Smuzhiyun | (inb(DMA2_STAT_REG) & 0xf0);
495*4882a593Smuzhiyun for(i=1;i<5;i++) {
496*4882a593Smuzhiyun int dma = dmatab[i];
497*4882a593Smuzhiyun if(test_bit(dma,&dma_channels) || request_dma(dma,"ni6510"))
498*4882a593Smuzhiyun continue;
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun flags=claim_dma_lock();
501*4882a593Smuzhiyun disable_dma(dma);
502*4882a593Smuzhiyun set_dma_mode(dma,DMA_MODE_CASCADE);
503*4882a593Smuzhiyun enable_dma(dma);
504*4882a593Smuzhiyun release_dma_lock(flags);
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun ni65_init_lance(p,dev->dev_addr,0,0); /* trigger memory access */
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun flags=claim_dma_lock();
509*4882a593Smuzhiyun disable_dma(dma);
510*4882a593Smuzhiyun free_dma(dma);
511*4882a593Smuzhiyun release_dma_lock(flags);
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun if(readreg(CSR0) & CSR0_IDON)
514*4882a593Smuzhiyun break;
515*4882a593Smuzhiyun }
516*4882a593Smuzhiyun if(i == 5) {
517*4882a593Smuzhiyun printk("failed.\n");
518*4882a593Smuzhiyun printk(KERN_ERR "%s: Can't detect DMA channel!\n", dev->name);
519*4882a593Smuzhiyun ni65_free_buffer(p);
520*4882a593Smuzhiyun release_region(ioaddr, cards[p->cardno].total_size);
521*4882a593Smuzhiyun return -EAGAIN;
522*4882a593Smuzhiyun }
523*4882a593Smuzhiyun dev->dma = dmatab[i];
524*4882a593Smuzhiyun printk("DMA %d (autodetected), ",dev->dma);
525*4882a593Smuzhiyun }
526*4882a593Smuzhiyun else
527*4882a593Smuzhiyun printk("DMA %d (assigned), ",dev->dma);
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun if(dev->irq < 2)
530*4882a593Smuzhiyun {
531*4882a593Smuzhiyun unsigned long irq_mask;
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun ni65_init_lance(p,dev->dev_addr,0,0);
534*4882a593Smuzhiyun irq_mask = probe_irq_on();
535*4882a593Smuzhiyun writereg(CSR0_INIT|CSR0_INEA,CSR0); /* trigger interrupt */
536*4882a593Smuzhiyun msleep(20);
537*4882a593Smuzhiyun dev->irq = probe_irq_off(irq_mask);
538*4882a593Smuzhiyun if(!dev->irq)
539*4882a593Smuzhiyun {
540*4882a593Smuzhiyun printk("Failed to detect IRQ line!\n");
541*4882a593Smuzhiyun ni65_free_buffer(p);
542*4882a593Smuzhiyun release_region(ioaddr, cards[p->cardno].total_size);
543*4882a593Smuzhiyun return -EAGAIN;
544*4882a593Smuzhiyun }
545*4882a593Smuzhiyun printk("IRQ %d (autodetected).\n",dev->irq);
546*4882a593Smuzhiyun }
547*4882a593Smuzhiyun else
548*4882a593Smuzhiyun printk("IRQ %d (assigned).\n",dev->irq);
549*4882a593Smuzhiyun }
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun if(request_dma(dev->dma, cards[p->cardno].cardname ) != 0)
552*4882a593Smuzhiyun {
553*4882a593Smuzhiyun printk(KERN_ERR "%s: Can't request dma-channel %d\n",dev->name,(int) dev->dma);
554*4882a593Smuzhiyun ni65_free_buffer(p);
555*4882a593Smuzhiyun release_region(ioaddr, cards[p->cardno].total_size);
556*4882a593Smuzhiyun return -EAGAIN;
557*4882a593Smuzhiyun }
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun dev->base_addr = ioaddr;
560*4882a593Smuzhiyun dev->netdev_ops = &ni65_netdev_ops;
561*4882a593Smuzhiyun dev->watchdog_timeo = HZ/2;
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun return 0; /* everything is OK */
564*4882a593Smuzhiyun }
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun /*
567*4882a593Smuzhiyun * set lance register and trigger init
568*4882a593Smuzhiyun */
ni65_init_lance(struct priv * p,unsigned char * daddr,int filter,int mode)569*4882a593Smuzhiyun static void ni65_init_lance(struct priv *p,unsigned char *daddr,int filter,int mode)
570*4882a593Smuzhiyun {
571*4882a593Smuzhiyun int i;
572*4882a593Smuzhiyun u32 pib;
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun writereg(CSR0_CLRALL|CSR0_STOP,CSR0);
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun for(i=0;i<6;i++)
577*4882a593Smuzhiyun p->ib.eaddr[i] = daddr[i];
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun for(i=0;i<8;i++)
580*4882a593Smuzhiyun p->ib.filter[i] = filter;
581*4882a593Smuzhiyun p->ib.mode = mode;
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun p->ib.trp = (u32) isa_virt_to_bus(p->tmdhead) | TMDNUMMASK;
584*4882a593Smuzhiyun p->ib.rrp = (u32) isa_virt_to_bus(p->rmdhead) | RMDNUMMASK;
585*4882a593Smuzhiyun writereg(0,CSR3); /* busmaster/no word-swap */
586*4882a593Smuzhiyun pib = (u32) isa_virt_to_bus(&p->ib);
587*4882a593Smuzhiyun writereg(pib & 0xffff,CSR1);
588*4882a593Smuzhiyun writereg(pib >> 16,CSR2);
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun writereg(CSR0_INIT,CSR0); /* this changes L_ADDRREG to CSR0 */
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun for(i=0;i<32;i++)
593*4882a593Smuzhiyun {
594*4882a593Smuzhiyun mdelay(4);
595*4882a593Smuzhiyun if(inw(PORT+L_DATAREG) & (CSR0_IDON | CSR0_MERR) )
596*4882a593Smuzhiyun break; /* init ok ? */
597*4882a593Smuzhiyun }
598*4882a593Smuzhiyun }
599*4882a593Smuzhiyun
600*4882a593Smuzhiyun /*
601*4882a593Smuzhiyun * allocate memory area and check the 16MB border
602*4882a593Smuzhiyun */
ni65_alloc_mem(struct net_device * dev,char * what,int size,int type)603*4882a593Smuzhiyun static void *ni65_alloc_mem(struct net_device *dev,char *what,int size,int type)
604*4882a593Smuzhiyun {
605*4882a593Smuzhiyun struct sk_buff *skb=NULL;
606*4882a593Smuzhiyun unsigned char *ptr;
607*4882a593Smuzhiyun void *ret;
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun if(type) {
610*4882a593Smuzhiyun ret = skb = alloc_skb(2+16+size,GFP_KERNEL|GFP_DMA);
611*4882a593Smuzhiyun if(!skb) {
612*4882a593Smuzhiyun printk(KERN_WARNING "%s: unable to allocate %s memory.\n",dev->name,what);
613*4882a593Smuzhiyun return NULL;
614*4882a593Smuzhiyun }
615*4882a593Smuzhiyun skb_reserve(skb,2+16);
616*4882a593Smuzhiyun skb_put(skb,R_BUF_SIZE); /* grab the whole space .. (not necessary) */
617*4882a593Smuzhiyun ptr = skb->data;
618*4882a593Smuzhiyun }
619*4882a593Smuzhiyun else {
620*4882a593Smuzhiyun ret = ptr = kmalloc(T_BUF_SIZE,GFP_KERNEL | GFP_DMA);
621*4882a593Smuzhiyun if(!ret)
622*4882a593Smuzhiyun return NULL;
623*4882a593Smuzhiyun }
624*4882a593Smuzhiyun if( (u32) virt_to_phys(ptr+size) > 0x1000000) {
625*4882a593Smuzhiyun printk(KERN_WARNING "%s: unable to allocate %s memory in lower 16MB!\n",dev->name,what);
626*4882a593Smuzhiyun if(type)
627*4882a593Smuzhiyun kfree_skb(skb);
628*4882a593Smuzhiyun else
629*4882a593Smuzhiyun kfree(ptr);
630*4882a593Smuzhiyun return NULL;
631*4882a593Smuzhiyun }
632*4882a593Smuzhiyun return ret;
633*4882a593Smuzhiyun }
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun /*
636*4882a593Smuzhiyun * allocate all memory structures .. send/recv buffers etc ...
637*4882a593Smuzhiyun */
ni65_alloc_buffer(struct net_device * dev)638*4882a593Smuzhiyun static int ni65_alloc_buffer(struct net_device *dev)
639*4882a593Smuzhiyun {
640*4882a593Smuzhiyun unsigned char *ptr;
641*4882a593Smuzhiyun struct priv *p;
642*4882a593Smuzhiyun int i;
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun /*
645*4882a593Smuzhiyun * we need 8-aligned memory ..
646*4882a593Smuzhiyun */
647*4882a593Smuzhiyun ptr = ni65_alloc_mem(dev,"BUFFER",sizeof(struct priv)+8,0);
648*4882a593Smuzhiyun if(!ptr)
649*4882a593Smuzhiyun return -ENOMEM;
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun p = dev->ml_priv = (struct priv *) (((unsigned long) ptr + 7) & ~0x7);
652*4882a593Smuzhiyun memset((char *)p, 0, sizeof(struct priv));
653*4882a593Smuzhiyun p->self = ptr;
654*4882a593Smuzhiyun
655*4882a593Smuzhiyun for(i=0;i<TMDNUM;i++)
656*4882a593Smuzhiyun {
657*4882a593Smuzhiyun #ifdef XMT_VIA_SKB
658*4882a593Smuzhiyun p->tmd_skb[i] = NULL;
659*4882a593Smuzhiyun #endif
660*4882a593Smuzhiyun p->tmdbounce[i] = ni65_alloc_mem(dev,"XMIT",T_BUF_SIZE,0);
661*4882a593Smuzhiyun if(!p->tmdbounce[i]) {
662*4882a593Smuzhiyun ni65_free_buffer(p);
663*4882a593Smuzhiyun return -ENOMEM;
664*4882a593Smuzhiyun }
665*4882a593Smuzhiyun }
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun for(i=0;i<RMDNUM;i++)
668*4882a593Smuzhiyun {
669*4882a593Smuzhiyun #ifdef RCV_VIA_SKB
670*4882a593Smuzhiyun p->recv_skb[i] = ni65_alloc_mem(dev,"RECV",R_BUF_SIZE,1);
671*4882a593Smuzhiyun if(!p->recv_skb[i]) {
672*4882a593Smuzhiyun ni65_free_buffer(p);
673*4882a593Smuzhiyun return -ENOMEM;
674*4882a593Smuzhiyun }
675*4882a593Smuzhiyun #else
676*4882a593Smuzhiyun p->recvbounce[i] = ni65_alloc_mem(dev,"RECV",R_BUF_SIZE,0);
677*4882a593Smuzhiyun if(!p->recvbounce[i]) {
678*4882a593Smuzhiyun ni65_free_buffer(p);
679*4882a593Smuzhiyun return -ENOMEM;
680*4882a593Smuzhiyun }
681*4882a593Smuzhiyun #endif
682*4882a593Smuzhiyun }
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun return 0; /* everything is OK */
685*4882a593Smuzhiyun }
686*4882a593Smuzhiyun
687*4882a593Smuzhiyun /*
688*4882a593Smuzhiyun * free buffers and private struct
689*4882a593Smuzhiyun */
ni65_free_buffer(struct priv * p)690*4882a593Smuzhiyun static void ni65_free_buffer(struct priv *p)
691*4882a593Smuzhiyun {
692*4882a593Smuzhiyun int i;
693*4882a593Smuzhiyun
694*4882a593Smuzhiyun if(!p)
695*4882a593Smuzhiyun return;
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun for(i=0;i<TMDNUM;i++) {
698*4882a593Smuzhiyun kfree(p->tmdbounce[i]);
699*4882a593Smuzhiyun #ifdef XMT_VIA_SKB
700*4882a593Smuzhiyun dev_kfree_skb(p->tmd_skb[i]);
701*4882a593Smuzhiyun #endif
702*4882a593Smuzhiyun }
703*4882a593Smuzhiyun
704*4882a593Smuzhiyun for(i=0;i<RMDNUM;i++)
705*4882a593Smuzhiyun {
706*4882a593Smuzhiyun #ifdef RCV_VIA_SKB
707*4882a593Smuzhiyun dev_kfree_skb(p->recv_skb[i]);
708*4882a593Smuzhiyun #else
709*4882a593Smuzhiyun kfree(p->recvbounce[i]);
710*4882a593Smuzhiyun #endif
711*4882a593Smuzhiyun }
712*4882a593Smuzhiyun kfree(p->self);
713*4882a593Smuzhiyun }
714*4882a593Smuzhiyun
715*4882a593Smuzhiyun
716*4882a593Smuzhiyun /*
717*4882a593Smuzhiyun * stop and (re)start lance .. e.g after an error
718*4882a593Smuzhiyun */
ni65_stop_start(struct net_device * dev,struct priv * p)719*4882a593Smuzhiyun static void ni65_stop_start(struct net_device *dev,struct priv *p)
720*4882a593Smuzhiyun {
721*4882a593Smuzhiyun int csr0 = CSR0_INEA;
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun writedatareg(CSR0_STOP);
724*4882a593Smuzhiyun
725*4882a593Smuzhiyun if(debuglevel > 1)
726*4882a593Smuzhiyun printk(KERN_DEBUG "ni65_stop_start\n");
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun if(p->features & INIT_RING_BEFORE_START) {
729*4882a593Smuzhiyun int i;
730*4882a593Smuzhiyun #ifdef XMT_VIA_SKB
731*4882a593Smuzhiyun struct sk_buff *skb_save[TMDNUM];
732*4882a593Smuzhiyun #endif
733*4882a593Smuzhiyun unsigned long buffer[TMDNUM];
734*4882a593Smuzhiyun short blen[TMDNUM];
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun if(p->xmit_queued) {
737*4882a593Smuzhiyun while(1) {
738*4882a593Smuzhiyun if((p->tmdhead[p->tmdlast].u.s.status & XMIT_OWN))
739*4882a593Smuzhiyun break;
740*4882a593Smuzhiyun p->tmdlast = (p->tmdlast + 1) & (TMDNUM-1);
741*4882a593Smuzhiyun if(p->tmdlast == p->tmdnum)
742*4882a593Smuzhiyun break;
743*4882a593Smuzhiyun }
744*4882a593Smuzhiyun }
745*4882a593Smuzhiyun
746*4882a593Smuzhiyun for(i=0;i<TMDNUM;i++) {
747*4882a593Smuzhiyun struct tmd *tmdp = p->tmdhead + i;
748*4882a593Smuzhiyun #ifdef XMT_VIA_SKB
749*4882a593Smuzhiyun skb_save[i] = p->tmd_skb[i];
750*4882a593Smuzhiyun #endif
751*4882a593Smuzhiyun buffer[i] = (u32) isa_bus_to_virt(tmdp->u.buffer);
752*4882a593Smuzhiyun blen[i] = tmdp->blen;
753*4882a593Smuzhiyun tmdp->u.s.status = 0x0;
754*4882a593Smuzhiyun }
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun for(i=0;i<RMDNUM;i++) {
757*4882a593Smuzhiyun struct rmd *rmdp = p->rmdhead + i;
758*4882a593Smuzhiyun rmdp->u.s.status = RCV_OWN;
759*4882a593Smuzhiyun }
760*4882a593Smuzhiyun p->tmdnum = p->xmit_queued = 0;
761*4882a593Smuzhiyun writedatareg(CSR0_STRT | csr0);
762*4882a593Smuzhiyun
763*4882a593Smuzhiyun for(i=0;i<TMDNUM;i++) {
764*4882a593Smuzhiyun int num = (i + p->tmdlast) & (TMDNUM-1);
765*4882a593Smuzhiyun p->tmdhead[i].u.buffer = (u32) isa_virt_to_bus((char *)buffer[num]); /* status is part of buffer field */
766*4882a593Smuzhiyun p->tmdhead[i].blen = blen[num];
767*4882a593Smuzhiyun if(p->tmdhead[i].u.s.status & XMIT_OWN) {
768*4882a593Smuzhiyun p->tmdnum = (p->tmdnum + 1) & (TMDNUM-1);
769*4882a593Smuzhiyun p->xmit_queued = 1;
770*4882a593Smuzhiyun writedatareg(CSR0_TDMD | CSR0_INEA | csr0);
771*4882a593Smuzhiyun }
772*4882a593Smuzhiyun #ifdef XMT_VIA_SKB
773*4882a593Smuzhiyun p->tmd_skb[i] = skb_save[num];
774*4882a593Smuzhiyun #endif
775*4882a593Smuzhiyun }
776*4882a593Smuzhiyun p->rmdnum = p->tmdlast = 0;
777*4882a593Smuzhiyun if(!p->lock)
778*4882a593Smuzhiyun if (p->tmdnum || !p->xmit_queued)
779*4882a593Smuzhiyun netif_wake_queue(dev);
780*4882a593Smuzhiyun netif_trans_update(dev); /* prevent tx timeout */
781*4882a593Smuzhiyun }
782*4882a593Smuzhiyun else
783*4882a593Smuzhiyun writedatareg(CSR0_STRT | csr0);
784*4882a593Smuzhiyun }
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun /*
787*4882a593Smuzhiyun * init lance (write init-values .. init-buffers) (open-helper)
788*4882a593Smuzhiyun */
ni65_lance_reinit(struct net_device * dev)789*4882a593Smuzhiyun static int ni65_lance_reinit(struct net_device *dev)
790*4882a593Smuzhiyun {
791*4882a593Smuzhiyun int i;
792*4882a593Smuzhiyun struct priv *p = dev->ml_priv;
793*4882a593Smuzhiyun unsigned long flags;
794*4882a593Smuzhiyun
795*4882a593Smuzhiyun p->lock = 0;
796*4882a593Smuzhiyun p->xmit_queued = 0;
797*4882a593Smuzhiyun
798*4882a593Smuzhiyun flags=claim_dma_lock();
799*4882a593Smuzhiyun disable_dma(dev->dma); /* I've never worked with dma, but we do it like the packetdriver */
800*4882a593Smuzhiyun set_dma_mode(dev->dma,DMA_MODE_CASCADE);
801*4882a593Smuzhiyun enable_dma(dev->dma);
802*4882a593Smuzhiyun release_dma_lock(flags);
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun outw(inw(PORT+L_RESET),PORT+L_RESET); /* first: reset the card */
805*4882a593Smuzhiyun if( (i=readreg(CSR0) ) != 0x4)
806*4882a593Smuzhiyun {
807*4882a593Smuzhiyun printk(KERN_ERR "%s: can't RESET %s card: %04x\n",dev->name,
808*4882a593Smuzhiyun cards[p->cardno].cardname,(int) i);
809*4882a593Smuzhiyun flags=claim_dma_lock();
810*4882a593Smuzhiyun disable_dma(dev->dma);
811*4882a593Smuzhiyun release_dma_lock(flags);
812*4882a593Smuzhiyun return 0;
813*4882a593Smuzhiyun }
814*4882a593Smuzhiyun
815*4882a593Smuzhiyun p->rmdnum = p->tmdnum = p->tmdlast = p->tmdbouncenum = 0;
816*4882a593Smuzhiyun for(i=0;i<TMDNUM;i++)
817*4882a593Smuzhiyun {
818*4882a593Smuzhiyun struct tmd *tmdp = p->tmdhead + i;
819*4882a593Smuzhiyun #ifdef XMT_VIA_SKB
820*4882a593Smuzhiyun if(p->tmd_skb[i]) {
821*4882a593Smuzhiyun dev_kfree_skb(p->tmd_skb[i]);
822*4882a593Smuzhiyun p->tmd_skb[i] = NULL;
823*4882a593Smuzhiyun }
824*4882a593Smuzhiyun #endif
825*4882a593Smuzhiyun tmdp->u.buffer = 0x0;
826*4882a593Smuzhiyun tmdp->u.s.status = XMIT_START | XMIT_END;
827*4882a593Smuzhiyun tmdp->blen = tmdp->status2 = 0;
828*4882a593Smuzhiyun }
829*4882a593Smuzhiyun
830*4882a593Smuzhiyun for(i=0;i<RMDNUM;i++)
831*4882a593Smuzhiyun {
832*4882a593Smuzhiyun struct rmd *rmdp = p->rmdhead + i;
833*4882a593Smuzhiyun #ifdef RCV_VIA_SKB
834*4882a593Smuzhiyun rmdp->u.buffer = (u32) isa_virt_to_bus(p->recv_skb[i]->data);
835*4882a593Smuzhiyun #else
836*4882a593Smuzhiyun rmdp->u.buffer = (u32) isa_virt_to_bus(p->recvbounce[i]);
837*4882a593Smuzhiyun #endif
838*4882a593Smuzhiyun rmdp->blen = -(R_BUF_SIZE-8);
839*4882a593Smuzhiyun rmdp->mlen = 0;
840*4882a593Smuzhiyun rmdp->u.s.status = RCV_OWN;
841*4882a593Smuzhiyun }
842*4882a593Smuzhiyun
843*4882a593Smuzhiyun if(dev->flags & IFF_PROMISC)
844*4882a593Smuzhiyun ni65_init_lance(p,dev->dev_addr,0x00,M_PROM);
845*4882a593Smuzhiyun else if (netdev_mc_count(dev) || dev->flags & IFF_ALLMULTI)
846*4882a593Smuzhiyun ni65_init_lance(p,dev->dev_addr,0xff,0x0);
847*4882a593Smuzhiyun else
848*4882a593Smuzhiyun ni65_init_lance(p,dev->dev_addr,0x00,0x00);
849*4882a593Smuzhiyun
850*4882a593Smuzhiyun /*
851*4882a593Smuzhiyun * ni65_set_lance_mem() sets L_ADDRREG to CSR0
852*4882a593Smuzhiyun * NOW, WE WILL NEVER CHANGE THE L_ADDRREG, CSR0 IS ALWAYS SELECTED
853*4882a593Smuzhiyun */
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun if(inw(PORT+L_DATAREG) & CSR0_IDON) {
856*4882a593Smuzhiyun ni65_set_performance(p);
857*4882a593Smuzhiyun /* init OK: start lance , enable interrupts */
858*4882a593Smuzhiyun writedatareg(CSR0_CLRALL | CSR0_INEA | CSR0_STRT);
859*4882a593Smuzhiyun return 1; /* ->OK */
860*4882a593Smuzhiyun }
861*4882a593Smuzhiyun printk(KERN_ERR "%s: can't init lance, status: %04x\n",dev->name,(int) inw(PORT+L_DATAREG));
862*4882a593Smuzhiyun flags=claim_dma_lock();
863*4882a593Smuzhiyun disable_dma(dev->dma);
864*4882a593Smuzhiyun release_dma_lock(flags);
865*4882a593Smuzhiyun return 0; /* ->Error */
866*4882a593Smuzhiyun }
867*4882a593Smuzhiyun
868*4882a593Smuzhiyun /*
869*4882a593Smuzhiyun * interrupt handler
870*4882a593Smuzhiyun */
ni65_interrupt(int irq,void * dev_id)871*4882a593Smuzhiyun static irqreturn_t ni65_interrupt(int irq, void * dev_id)
872*4882a593Smuzhiyun {
873*4882a593Smuzhiyun int csr0 = 0;
874*4882a593Smuzhiyun struct net_device *dev = dev_id;
875*4882a593Smuzhiyun struct priv *p;
876*4882a593Smuzhiyun int bcnt = 32;
877*4882a593Smuzhiyun
878*4882a593Smuzhiyun p = dev->ml_priv;
879*4882a593Smuzhiyun
880*4882a593Smuzhiyun spin_lock(&p->ring_lock);
881*4882a593Smuzhiyun
882*4882a593Smuzhiyun while(--bcnt) {
883*4882a593Smuzhiyun csr0 = inw(PORT+L_DATAREG);
884*4882a593Smuzhiyun
885*4882a593Smuzhiyun #if 0
886*4882a593Smuzhiyun writedatareg( (csr0 & CSR0_CLRALL) ); /* ack interrupts, disable int. */
887*4882a593Smuzhiyun #else
888*4882a593Smuzhiyun writedatareg( (csr0 & CSR0_CLRALL) | CSR0_INEA ); /* ack interrupts, interrupts enabled */
889*4882a593Smuzhiyun #endif
890*4882a593Smuzhiyun
891*4882a593Smuzhiyun if(!(csr0 & (CSR0_ERR | CSR0_RINT | CSR0_TINT)))
892*4882a593Smuzhiyun break;
893*4882a593Smuzhiyun
894*4882a593Smuzhiyun if(csr0 & CSR0_RINT) /* RECV-int? */
895*4882a593Smuzhiyun ni65_recv_intr(dev,csr0);
896*4882a593Smuzhiyun if(csr0 & CSR0_TINT) /* XMIT-int? */
897*4882a593Smuzhiyun ni65_xmit_intr(dev,csr0);
898*4882a593Smuzhiyun
899*4882a593Smuzhiyun if(csr0 & CSR0_ERR)
900*4882a593Smuzhiyun {
901*4882a593Smuzhiyun if(debuglevel > 1)
902*4882a593Smuzhiyun printk(KERN_ERR "%s: general error: %04x.\n",dev->name,csr0);
903*4882a593Smuzhiyun if(csr0 & CSR0_BABL)
904*4882a593Smuzhiyun dev->stats.tx_errors++;
905*4882a593Smuzhiyun if(csr0 & CSR0_MISS) {
906*4882a593Smuzhiyun int i;
907*4882a593Smuzhiyun for(i=0;i<RMDNUM;i++)
908*4882a593Smuzhiyun printk("%02x ",p->rmdhead[i].u.s.status);
909*4882a593Smuzhiyun printk("\n");
910*4882a593Smuzhiyun dev->stats.rx_errors++;
911*4882a593Smuzhiyun }
912*4882a593Smuzhiyun if(csr0 & CSR0_MERR) {
913*4882a593Smuzhiyun if(debuglevel > 1)
914*4882a593Smuzhiyun printk(KERN_ERR "%s: Ooops .. memory error: %04x.\n",dev->name,csr0);
915*4882a593Smuzhiyun ni65_stop_start(dev,p);
916*4882a593Smuzhiyun }
917*4882a593Smuzhiyun }
918*4882a593Smuzhiyun }
919*4882a593Smuzhiyun
920*4882a593Smuzhiyun #ifdef RCV_PARANOIA_CHECK
921*4882a593Smuzhiyun {
922*4882a593Smuzhiyun int j;
923*4882a593Smuzhiyun for(j=0;j<RMDNUM;j++)
924*4882a593Smuzhiyun {
925*4882a593Smuzhiyun int i, num2;
926*4882a593Smuzhiyun for(i=RMDNUM-1;i>0;i--) {
927*4882a593Smuzhiyun num2 = (p->rmdnum + i) & (RMDNUM-1);
928*4882a593Smuzhiyun if(!(p->rmdhead[num2].u.s.status & RCV_OWN))
929*4882a593Smuzhiyun break;
930*4882a593Smuzhiyun }
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun if(i) {
933*4882a593Smuzhiyun int k, num1;
934*4882a593Smuzhiyun for(k=0;k<RMDNUM;k++) {
935*4882a593Smuzhiyun num1 = (p->rmdnum + k) & (RMDNUM-1);
936*4882a593Smuzhiyun if(!(p->rmdhead[num1].u.s.status & RCV_OWN))
937*4882a593Smuzhiyun break;
938*4882a593Smuzhiyun }
939*4882a593Smuzhiyun if(!k)
940*4882a593Smuzhiyun break;
941*4882a593Smuzhiyun
942*4882a593Smuzhiyun if(debuglevel > 0)
943*4882a593Smuzhiyun {
944*4882a593Smuzhiyun char buf[256],*buf1;
945*4882a593Smuzhiyun buf1 = buf;
946*4882a593Smuzhiyun for(k=0;k<RMDNUM;k++) {
947*4882a593Smuzhiyun sprintf(buf1,"%02x ",(p->rmdhead[k].u.s.status)); /* & RCV_OWN) ); */
948*4882a593Smuzhiyun buf1 += 3;
949*4882a593Smuzhiyun }
950*4882a593Smuzhiyun *buf1 = 0;
951*4882a593Smuzhiyun printk(KERN_ERR "%s: Ooops, receive ring corrupted %2d %2d | %s\n",dev->name,p->rmdnum,i,buf);
952*4882a593Smuzhiyun }
953*4882a593Smuzhiyun
954*4882a593Smuzhiyun p->rmdnum = num1;
955*4882a593Smuzhiyun ni65_recv_intr(dev,csr0);
956*4882a593Smuzhiyun if((p->rmdhead[num2].u.s.status & RCV_OWN))
957*4882a593Smuzhiyun break; /* ok, we are 'in sync' again */
958*4882a593Smuzhiyun }
959*4882a593Smuzhiyun else
960*4882a593Smuzhiyun break;
961*4882a593Smuzhiyun }
962*4882a593Smuzhiyun }
963*4882a593Smuzhiyun #endif
964*4882a593Smuzhiyun
965*4882a593Smuzhiyun if( (csr0 & (CSR0_RXON | CSR0_TXON)) != (CSR0_RXON | CSR0_TXON) ) {
966*4882a593Smuzhiyun printk(KERN_DEBUG "%s: RX or TX was offline -> restart\n",dev->name);
967*4882a593Smuzhiyun ni65_stop_start(dev,p);
968*4882a593Smuzhiyun }
969*4882a593Smuzhiyun else
970*4882a593Smuzhiyun writedatareg(CSR0_INEA);
971*4882a593Smuzhiyun
972*4882a593Smuzhiyun spin_unlock(&p->ring_lock);
973*4882a593Smuzhiyun return IRQ_HANDLED;
974*4882a593Smuzhiyun }
975*4882a593Smuzhiyun
976*4882a593Smuzhiyun /*
977*4882a593Smuzhiyun * We have received an Xmit-Interrupt ..
978*4882a593Smuzhiyun * send a new packet if necessary
979*4882a593Smuzhiyun */
ni65_xmit_intr(struct net_device * dev,int csr0)980*4882a593Smuzhiyun static void ni65_xmit_intr(struct net_device *dev,int csr0)
981*4882a593Smuzhiyun {
982*4882a593Smuzhiyun struct priv *p = dev->ml_priv;
983*4882a593Smuzhiyun
984*4882a593Smuzhiyun while(p->xmit_queued)
985*4882a593Smuzhiyun {
986*4882a593Smuzhiyun struct tmd *tmdp = p->tmdhead + p->tmdlast;
987*4882a593Smuzhiyun int tmdstat = tmdp->u.s.status;
988*4882a593Smuzhiyun
989*4882a593Smuzhiyun if(tmdstat & XMIT_OWN)
990*4882a593Smuzhiyun break;
991*4882a593Smuzhiyun
992*4882a593Smuzhiyun if(tmdstat & XMIT_ERR)
993*4882a593Smuzhiyun {
994*4882a593Smuzhiyun #if 0
995*4882a593Smuzhiyun if(tmdp->status2 & XMIT_TDRMASK && debuglevel > 3)
996*4882a593Smuzhiyun printk(KERN_ERR "%s: tdr-problems (e.g. no resistor)\n",dev->name);
997*4882a593Smuzhiyun #endif
998*4882a593Smuzhiyun /* checking some errors */
999*4882a593Smuzhiyun if(tmdp->status2 & XMIT_RTRY)
1000*4882a593Smuzhiyun dev->stats.tx_aborted_errors++;
1001*4882a593Smuzhiyun if(tmdp->status2 & XMIT_LCAR)
1002*4882a593Smuzhiyun dev->stats.tx_carrier_errors++;
1003*4882a593Smuzhiyun if(tmdp->status2 & (XMIT_BUFF | XMIT_UFLO )) {
1004*4882a593Smuzhiyun /* this stops the xmitter */
1005*4882a593Smuzhiyun dev->stats.tx_fifo_errors++;
1006*4882a593Smuzhiyun if(debuglevel > 0)
1007*4882a593Smuzhiyun printk(KERN_ERR "%s: Xmit FIFO/BUFF error\n",dev->name);
1008*4882a593Smuzhiyun if(p->features & INIT_RING_BEFORE_START) {
1009*4882a593Smuzhiyun tmdp->u.s.status = XMIT_OWN | XMIT_START | XMIT_END; /* test: resend this frame */
1010*4882a593Smuzhiyun ni65_stop_start(dev,p);
1011*4882a593Smuzhiyun break; /* no more Xmit processing .. */
1012*4882a593Smuzhiyun }
1013*4882a593Smuzhiyun else
1014*4882a593Smuzhiyun ni65_stop_start(dev,p);
1015*4882a593Smuzhiyun }
1016*4882a593Smuzhiyun if(debuglevel > 2)
1017*4882a593Smuzhiyun printk(KERN_ERR "%s: xmit-error: %04x %02x-%04x\n",dev->name,csr0,(int) tmdstat,(int) tmdp->status2);
1018*4882a593Smuzhiyun if(!(csr0 & CSR0_BABL)) /* don't count errors twice */
1019*4882a593Smuzhiyun dev->stats.tx_errors++;
1020*4882a593Smuzhiyun tmdp->status2 = 0;
1021*4882a593Smuzhiyun }
1022*4882a593Smuzhiyun else {
1023*4882a593Smuzhiyun dev->stats.tx_bytes -= (short)(tmdp->blen);
1024*4882a593Smuzhiyun dev->stats.tx_packets++;
1025*4882a593Smuzhiyun }
1026*4882a593Smuzhiyun
1027*4882a593Smuzhiyun #ifdef XMT_VIA_SKB
1028*4882a593Smuzhiyun if(p->tmd_skb[p->tmdlast]) {
1029*4882a593Smuzhiyun dev_consume_skb_irq(p->tmd_skb[p->tmdlast]);
1030*4882a593Smuzhiyun p->tmd_skb[p->tmdlast] = NULL;
1031*4882a593Smuzhiyun }
1032*4882a593Smuzhiyun #endif
1033*4882a593Smuzhiyun
1034*4882a593Smuzhiyun p->tmdlast = (p->tmdlast + 1) & (TMDNUM-1);
1035*4882a593Smuzhiyun if(p->tmdlast == p->tmdnum)
1036*4882a593Smuzhiyun p->xmit_queued = 0;
1037*4882a593Smuzhiyun }
1038*4882a593Smuzhiyun netif_wake_queue(dev);
1039*4882a593Smuzhiyun }
1040*4882a593Smuzhiyun
1041*4882a593Smuzhiyun /*
1042*4882a593Smuzhiyun * We have received a packet
1043*4882a593Smuzhiyun */
ni65_recv_intr(struct net_device * dev,int csr0)1044*4882a593Smuzhiyun static void ni65_recv_intr(struct net_device *dev,int csr0)
1045*4882a593Smuzhiyun {
1046*4882a593Smuzhiyun struct rmd *rmdp;
1047*4882a593Smuzhiyun int rmdstat,len;
1048*4882a593Smuzhiyun int cnt=0;
1049*4882a593Smuzhiyun struct priv *p = dev->ml_priv;
1050*4882a593Smuzhiyun
1051*4882a593Smuzhiyun rmdp = p->rmdhead + p->rmdnum;
1052*4882a593Smuzhiyun while(!( (rmdstat = rmdp->u.s.status) & RCV_OWN))
1053*4882a593Smuzhiyun {
1054*4882a593Smuzhiyun cnt++;
1055*4882a593Smuzhiyun if( (rmdstat & (RCV_START | RCV_END | RCV_ERR)) != (RCV_START | RCV_END) ) /* error or oversized? */
1056*4882a593Smuzhiyun {
1057*4882a593Smuzhiyun if(!(rmdstat & RCV_ERR)) {
1058*4882a593Smuzhiyun if(rmdstat & RCV_START)
1059*4882a593Smuzhiyun {
1060*4882a593Smuzhiyun dev->stats.rx_length_errors++;
1061*4882a593Smuzhiyun printk(KERN_ERR "%s: recv, packet too long: %d\n",dev->name,rmdp->mlen & 0x0fff);
1062*4882a593Smuzhiyun }
1063*4882a593Smuzhiyun }
1064*4882a593Smuzhiyun else {
1065*4882a593Smuzhiyun if(debuglevel > 2)
1066*4882a593Smuzhiyun printk(KERN_ERR "%s: receive-error: %04x, lance-status: %04x/%04x\n",
1067*4882a593Smuzhiyun dev->name,(int) rmdstat,csr0,(int) inw(PORT+L_DATAREG) );
1068*4882a593Smuzhiyun if(rmdstat & RCV_FRAM)
1069*4882a593Smuzhiyun dev->stats.rx_frame_errors++;
1070*4882a593Smuzhiyun if(rmdstat & RCV_OFLO)
1071*4882a593Smuzhiyun dev->stats.rx_over_errors++;
1072*4882a593Smuzhiyun if(rmdstat & RCV_CRC)
1073*4882a593Smuzhiyun dev->stats.rx_crc_errors++;
1074*4882a593Smuzhiyun if(rmdstat & RCV_BUF_ERR)
1075*4882a593Smuzhiyun dev->stats.rx_fifo_errors++;
1076*4882a593Smuzhiyun }
1077*4882a593Smuzhiyun if(!(csr0 & CSR0_MISS)) /* don't count errors twice */
1078*4882a593Smuzhiyun dev->stats.rx_errors++;
1079*4882a593Smuzhiyun }
1080*4882a593Smuzhiyun else if( (len = (rmdp->mlen & 0x0fff) - 4) >= 60)
1081*4882a593Smuzhiyun {
1082*4882a593Smuzhiyun #ifdef RCV_VIA_SKB
1083*4882a593Smuzhiyun struct sk_buff *skb = alloc_skb(R_BUF_SIZE+2+16,GFP_ATOMIC);
1084*4882a593Smuzhiyun if (skb)
1085*4882a593Smuzhiyun skb_reserve(skb,16);
1086*4882a593Smuzhiyun #else
1087*4882a593Smuzhiyun struct sk_buff *skb = netdev_alloc_skb(dev, len + 2);
1088*4882a593Smuzhiyun #endif
1089*4882a593Smuzhiyun if(skb)
1090*4882a593Smuzhiyun {
1091*4882a593Smuzhiyun skb_reserve(skb,2);
1092*4882a593Smuzhiyun #ifdef RCV_VIA_SKB
1093*4882a593Smuzhiyun if( (unsigned long) (skb->data + R_BUF_SIZE) > 0x1000000) {
1094*4882a593Smuzhiyun skb_put(skb,len);
1095*4882a593Smuzhiyun skb_copy_to_linear_data(skb, (unsigned char *)(p->recv_skb[p->rmdnum]->data),len);
1096*4882a593Smuzhiyun }
1097*4882a593Smuzhiyun else {
1098*4882a593Smuzhiyun struct sk_buff *skb1 = p->recv_skb[p->rmdnum];
1099*4882a593Smuzhiyun skb_put(skb,R_BUF_SIZE);
1100*4882a593Smuzhiyun p->recv_skb[p->rmdnum] = skb;
1101*4882a593Smuzhiyun rmdp->u.buffer = (u32) isa_virt_to_bus(skb->data);
1102*4882a593Smuzhiyun skb = skb1;
1103*4882a593Smuzhiyun skb_trim(skb,len);
1104*4882a593Smuzhiyun }
1105*4882a593Smuzhiyun #else
1106*4882a593Smuzhiyun skb_put(skb,len);
1107*4882a593Smuzhiyun skb_copy_to_linear_data(skb, (unsigned char *) p->recvbounce[p->rmdnum],len);
1108*4882a593Smuzhiyun #endif
1109*4882a593Smuzhiyun dev->stats.rx_packets++;
1110*4882a593Smuzhiyun dev->stats.rx_bytes += len;
1111*4882a593Smuzhiyun skb->protocol=eth_type_trans(skb,dev);
1112*4882a593Smuzhiyun netif_rx(skb);
1113*4882a593Smuzhiyun }
1114*4882a593Smuzhiyun else
1115*4882a593Smuzhiyun {
1116*4882a593Smuzhiyun printk(KERN_ERR "%s: can't alloc new sk_buff\n",dev->name);
1117*4882a593Smuzhiyun dev->stats.rx_dropped++;
1118*4882a593Smuzhiyun }
1119*4882a593Smuzhiyun }
1120*4882a593Smuzhiyun else {
1121*4882a593Smuzhiyun printk(KERN_INFO "%s: received runt packet\n",dev->name);
1122*4882a593Smuzhiyun dev->stats.rx_errors++;
1123*4882a593Smuzhiyun }
1124*4882a593Smuzhiyun rmdp->blen = -(R_BUF_SIZE-8);
1125*4882a593Smuzhiyun rmdp->mlen = 0;
1126*4882a593Smuzhiyun rmdp->u.s.status = RCV_OWN; /* change owner */
1127*4882a593Smuzhiyun p->rmdnum = (p->rmdnum + 1) & (RMDNUM-1);
1128*4882a593Smuzhiyun rmdp = p->rmdhead + p->rmdnum;
1129*4882a593Smuzhiyun }
1130*4882a593Smuzhiyun }
1131*4882a593Smuzhiyun
1132*4882a593Smuzhiyun /*
1133*4882a593Smuzhiyun * kick xmitter ..
1134*4882a593Smuzhiyun */
1135*4882a593Smuzhiyun
ni65_timeout(struct net_device * dev,unsigned int txqueue)1136*4882a593Smuzhiyun static void ni65_timeout(struct net_device *dev, unsigned int txqueue)
1137*4882a593Smuzhiyun {
1138*4882a593Smuzhiyun int i;
1139*4882a593Smuzhiyun struct priv *p = dev->ml_priv;
1140*4882a593Smuzhiyun
1141*4882a593Smuzhiyun printk(KERN_ERR "%s: xmitter timed out, try to restart!\n",dev->name);
1142*4882a593Smuzhiyun for(i=0;i<TMDNUM;i++)
1143*4882a593Smuzhiyun printk("%02x ",p->tmdhead[i].u.s.status);
1144*4882a593Smuzhiyun printk("\n");
1145*4882a593Smuzhiyun ni65_lance_reinit(dev);
1146*4882a593Smuzhiyun netif_trans_update(dev); /* prevent tx timeout */
1147*4882a593Smuzhiyun netif_wake_queue(dev);
1148*4882a593Smuzhiyun }
1149*4882a593Smuzhiyun
1150*4882a593Smuzhiyun /*
1151*4882a593Smuzhiyun * Send a packet
1152*4882a593Smuzhiyun */
1153*4882a593Smuzhiyun
ni65_send_packet(struct sk_buff * skb,struct net_device * dev)1154*4882a593Smuzhiyun static netdev_tx_t ni65_send_packet(struct sk_buff *skb,
1155*4882a593Smuzhiyun struct net_device *dev)
1156*4882a593Smuzhiyun {
1157*4882a593Smuzhiyun struct priv *p = dev->ml_priv;
1158*4882a593Smuzhiyun
1159*4882a593Smuzhiyun netif_stop_queue(dev);
1160*4882a593Smuzhiyun
1161*4882a593Smuzhiyun if (test_and_set_bit(0, (void*)&p->lock)) {
1162*4882a593Smuzhiyun printk(KERN_ERR "%s: Queue was locked.\n", dev->name);
1163*4882a593Smuzhiyun return NETDEV_TX_BUSY;
1164*4882a593Smuzhiyun }
1165*4882a593Smuzhiyun
1166*4882a593Smuzhiyun {
1167*4882a593Smuzhiyun short len = ETH_ZLEN < skb->len ? skb->len : ETH_ZLEN;
1168*4882a593Smuzhiyun struct tmd *tmdp;
1169*4882a593Smuzhiyun unsigned long flags;
1170*4882a593Smuzhiyun
1171*4882a593Smuzhiyun #ifdef XMT_VIA_SKB
1172*4882a593Smuzhiyun if( (unsigned long) (skb->data + skb->len) > 0x1000000) {
1173*4882a593Smuzhiyun #endif
1174*4882a593Smuzhiyun
1175*4882a593Smuzhiyun skb_copy_from_linear_data(skb, p->tmdbounce[p->tmdbouncenum],
1176*4882a593Smuzhiyun skb->len > T_BUF_SIZE ? T_BUF_SIZE :
1177*4882a593Smuzhiyun skb->len);
1178*4882a593Smuzhiyun if (len > skb->len)
1179*4882a593Smuzhiyun memset((char *)p->tmdbounce[p->tmdbouncenum]+skb->len, 0, len-skb->len);
1180*4882a593Smuzhiyun dev_kfree_skb (skb);
1181*4882a593Smuzhiyun
1182*4882a593Smuzhiyun spin_lock_irqsave(&p->ring_lock, flags);
1183*4882a593Smuzhiyun tmdp = p->tmdhead + p->tmdnum;
1184*4882a593Smuzhiyun tmdp->u.buffer = (u32) isa_virt_to_bus(p->tmdbounce[p->tmdbouncenum]);
1185*4882a593Smuzhiyun p->tmdbouncenum = (p->tmdbouncenum + 1) & (TMDNUM - 1);
1186*4882a593Smuzhiyun
1187*4882a593Smuzhiyun #ifdef XMT_VIA_SKB
1188*4882a593Smuzhiyun }
1189*4882a593Smuzhiyun else {
1190*4882a593Smuzhiyun spin_lock_irqsave(&p->ring_lock, flags);
1191*4882a593Smuzhiyun
1192*4882a593Smuzhiyun tmdp = p->tmdhead + p->tmdnum;
1193*4882a593Smuzhiyun tmdp->u.buffer = (u32) isa_virt_to_bus(skb->data);
1194*4882a593Smuzhiyun p->tmd_skb[p->tmdnum] = skb;
1195*4882a593Smuzhiyun }
1196*4882a593Smuzhiyun #endif
1197*4882a593Smuzhiyun tmdp->blen = -len;
1198*4882a593Smuzhiyun
1199*4882a593Smuzhiyun tmdp->u.s.status = XMIT_OWN | XMIT_START | XMIT_END;
1200*4882a593Smuzhiyun writedatareg(CSR0_TDMD | CSR0_INEA); /* enable xmit & interrupt */
1201*4882a593Smuzhiyun
1202*4882a593Smuzhiyun p->xmit_queued = 1;
1203*4882a593Smuzhiyun p->tmdnum = (p->tmdnum + 1) & (TMDNUM-1);
1204*4882a593Smuzhiyun
1205*4882a593Smuzhiyun if(p->tmdnum != p->tmdlast)
1206*4882a593Smuzhiyun netif_wake_queue(dev);
1207*4882a593Smuzhiyun
1208*4882a593Smuzhiyun p->lock = 0;
1209*4882a593Smuzhiyun
1210*4882a593Smuzhiyun spin_unlock_irqrestore(&p->ring_lock, flags);
1211*4882a593Smuzhiyun }
1212*4882a593Smuzhiyun
1213*4882a593Smuzhiyun return NETDEV_TX_OK;
1214*4882a593Smuzhiyun }
1215*4882a593Smuzhiyun
set_multicast_list(struct net_device * dev)1216*4882a593Smuzhiyun static void set_multicast_list(struct net_device *dev)
1217*4882a593Smuzhiyun {
1218*4882a593Smuzhiyun if(!ni65_lance_reinit(dev))
1219*4882a593Smuzhiyun printk(KERN_ERR "%s: Can't switch card into MC mode!\n",dev->name);
1220*4882a593Smuzhiyun netif_wake_queue(dev);
1221*4882a593Smuzhiyun }
1222*4882a593Smuzhiyun
1223*4882a593Smuzhiyun #ifdef MODULE
1224*4882a593Smuzhiyun static struct net_device *dev_ni65;
1225*4882a593Smuzhiyun
1226*4882a593Smuzhiyun module_param_hw(irq, int, irq, 0);
1227*4882a593Smuzhiyun module_param_hw(io, int, ioport, 0);
1228*4882a593Smuzhiyun module_param_hw(dma, int, dma, 0);
1229*4882a593Smuzhiyun MODULE_PARM_DESC(irq, "ni6510 IRQ number (ignored for some cards)");
1230*4882a593Smuzhiyun MODULE_PARM_DESC(io, "ni6510 I/O base address");
1231*4882a593Smuzhiyun MODULE_PARM_DESC(dma, "ni6510 ISA DMA channel (ignored for some cards)");
1232*4882a593Smuzhiyun
init_module(void)1233*4882a593Smuzhiyun int __init init_module(void)
1234*4882a593Smuzhiyun {
1235*4882a593Smuzhiyun dev_ni65 = ni65_probe(-1);
1236*4882a593Smuzhiyun return PTR_ERR_OR_ZERO(dev_ni65);
1237*4882a593Smuzhiyun }
1238*4882a593Smuzhiyun
cleanup_module(void)1239*4882a593Smuzhiyun void __exit cleanup_module(void)
1240*4882a593Smuzhiyun {
1241*4882a593Smuzhiyun unregister_netdev(dev_ni65);
1242*4882a593Smuzhiyun cleanup_card(dev_ni65);
1243*4882a593Smuzhiyun free_netdev(dev_ni65);
1244*4882a593Smuzhiyun }
1245*4882a593Smuzhiyun #endif /* MODULE */
1246*4882a593Smuzhiyun
1247*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1248