1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Alchemy Au1x00 ethernet driver include file 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Author: Pete Popov <ppopov@mvista.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright 2001 MontaVista Software Inc. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define MAC_IOSIZE 0x10000 13*4882a593Smuzhiyun #define NUM_RX_DMA 4 /* Au1x00 has 4 rx hardware descriptors */ 14*4882a593Smuzhiyun #define NUM_TX_DMA 4 /* Au1x00 has 4 tx hardware descriptors */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define NUM_RX_BUFFS 4 17*4882a593Smuzhiyun #define NUM_TX_BUFFS 4 18*4882a593Smuzhiyun #define MAX_BUF_SIZE 2048 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define ETH_TX_TIMEOUT (HZ/4) 21*4882a593Smuzhiyun #define MAC_MIN_PKT_SIZE 64 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define MULTICAST_FILTER_LIMIT 64 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* 26*4882a593Smuzhiyun * Data Buffer Descriptor. Data buffers must be aligned on 32 byte 27*4882a593Smuzhiyun * boundary for both, receive and transmit. 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun struct db_dest { 30*4882a593Smuzhiyun struct db_dest *pnext; 31*4882a593Smuzhiyun u32 *vaddr; 32*4882a593Smuzhiyun dma_addr_t dma_addr; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* 36*4882a593Smuzhiyun * The transmit and receive descriptors are memory 37*4882a593Smuzhiyun * mapped registers. 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun struct tx_dma { 40*4882a593Smuzhiyun u32 status; 41*4882a593Smuzhiyun u32 buff_stat; 42*4882a593Smuzhiyun u32 len; 43*4882a593Smuzhiyun u32 pad; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun struct rx_dma { 47*4882a593Smuzhiyun u32 status; 48*4882a593Smuzhiyun u32 buff_stat; 49*4882a593Smuzhiyun u32 pad[2]; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* 54*4882a593Smuzhiyun * MAC control registers, memory mapped. 55*4882a593Smuzhiyun */ 56*4882a593Smuzhiyun struct mac_reg { 57*4882a593Smuzhiyun u32 control; 58*4882a593Smuzhiyun u32 mac_addr_high; 59*4882a593Smuzhiyun u32 mac_addr_low; 60*4882a593Smuzhiyun u32 multi_hash_high; 61*4882a593Smuzhiyun u32 multi_hash_low; 62*4882a593Smuzhiyun u32 mii_control; 63*4882a593Smuzhiyun u32 mii_data; 64*4882a593Smuzhiyun u32 flow_control; 65*4882a593Smuzhiyun u32 vlan1_tag; 66*4882a593Smuzhiyun u32 vlan2_tag; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun struct au1000_private { 71*4882a593Smuzhiyun struct db_dest *pDBfree; 72*4882a593Smuzhiyun struct db_dest db[NUM_RX_BUFFS+NUM_TX_BUFFS]; 73*4882a593Smuzhiyun struct rx_dma *rx_dma_ring[NUM_RX_DMA]; 74*4882a593Smuzhiyun struct tx_dma *tx_dma_ring[NUM_TX_DMA]; 75*4882a593Smuzhiyun struct db_dest *rx_db_inuse[NUM_RX_DMA]; 76*4882a593Smuzhiyun struct db_dest *tx_db_inuse[NUM_TX_DMA]; 77*4882a593Smuzhiyun u32 rx_head; 78*4882a593Smuzhiyun u32 tx_head; 79*4882a593Smuzhiyun u32 tx_tail; 80*4882a593Smuzhiyun u32 tx_full; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun int mac_id; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun int mac_enabled; /* whether MAC is currently enabled and running 85*4882a593Smuzhiyun * (req. for mdio) 86*4882a593Smuzhiyun */ 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun int old_link; /* used by au1000_adjust_link */ 89*4882a593Smuzhiyun int old_speed; 90*4882a593Smuzhiyun int old_duplex; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun struct mii_bus *mii_bus; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* PHY configuration */ 95*4882a593Smuzhiyun int phy_static_config; 96*4882a593Smuzhiyun int phy_search_highest_addr; 97*4882a593Smuzhiyun int phy1_search_mac0; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun int phy_addr; 100*4882a593Smuzhiyun int phy_busid; 101*4882a593Smuzhiyun int phy_irq; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* These variables are just for quick access 104*4882a593Smuzhiyun * to certain regs addresses. 105*4882a593Smuzhiyun */ 106*4882a593Smuzhiyun struct mac_reg *mac; /* mac registers */ 107*4882a593Smuzhiyun u32 *enable; /* address of MAC Enable Register */ 108*4882a593Smuzhiyun void __iomem *macdma; /* base of MAC DMA port */ 109*4882a593Smuzhiyun u32 vaddr; /* virtual address of rx/tx buffers */ 110*4882a593Smuzhiyun dma_addr_t dma_addr; /* dma address of rx/tx buffers */ 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun spinlock_t lock; /* Serialise access to device */ 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun u32 msg_enable; 115*4882a593Smuzhiyun }; 116