xref: /OK3568_Linux_fs/kernel/drivers/net/ethernet/amazon/ena/ena_com.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #ifndef ENA_COM
7*4882a593Smuzhiyun #define ENA_COM
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/compiler.h>
10*4882a593Smuzhiyun #include <linux/delay.h>
11*4882a593Smuzhiyun #include <linux/dma-mapping.h>
12*4882a593Smuzhiyun #include <linux/gfp.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <linux/prefetch.h>
15*4882a593Smuzhiyun #include <linux/sched.h>
16*4882a593Smuzhiyun #include <linux/sizes.h>
17*4882a593Smuzhiyun #include <linux/spinlock.h>
18*4882a593Smuzhiyun #include <linux/types.h>
19*4882a593Smuzhiyun #include <linux/wait.h>
20*4882a593Smuzhiyun #include <linux/netdevice.h>
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #include "ena_common_defs.h"
23*4882a593Smuzhiyun #include "ena_admin_defs.h"
24*4882a593Smuzhiyun #include "ena_eth_io_defs.h"
25*4882a593Smuzhiyun #include "ena_regs_defs.h"
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #undef pr_fmt
28*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define ENA_MAX_NUM_IO_QUEUES 128U
31*4882a593Smuzhiyun /* We need to queues for each IO (on for Tx and one for Rx) */
32*4882a593Smuzhiyun #define ENA_TOTAL_NUM_QUEUES (2 * (ENA_MAX_NUM_IO_QUEUES))
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #define ENA_MAX_HANDLERS 256
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #define ENA_MAX_PHYS_ADDR_SIZE_BITS 48
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun /* Unit in usec */
39*4882a593Smuzhiyun #define ENA_REG_READ_TIMEOUT 200000
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #define ADMIN_SQ_SIZE(depth)	((depth) * sizeof(struct ena_admin_aq_entry))
42*4882a593Smuzhiyun #define ADMIN_CQ_SIZE(depth)	((depth) * sizeof(struct ena_admin_acq_entry))
43*4882a593Smuzhiyun #define ADMIN_AENQ_SIZE(depth)	((depth) * sizeof(struct ena_admin_aenq_entry))
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun /*****************************************************************************/
46*4882a593Smuzhiyun /*****************************************************************************/
47*4882a593Smuzhiyun /* ENA adaptive interrupt moderation settings */
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun #define ENA_INTR_INITIAL_TX_INTERVAL_USECS 64
50*4882a593Smuzhiyun #define ENA_INTR_INITIAL_RX_INTERVAL_USECS 0
51*4882a593Smuzhiyun #define ENA_DEFAULT_INTR_DELAY_RESOLUTION 1
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun #define ENA_HASH_KEY_SIZE 40
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun #define ENA_HW_HINTS_NO_TIMEOUT	0xFFFF
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun #define ENA_FEATURE_MAX_QUEUE_EXT_VER 1
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun struct ena_llq_configurations {
60*4882a593Smuzhiyun 	enum ena_admin_llq_header_location llq_header_location;
61*4882a593Smuzhiyun 	enum ena_admin_llq_ring_entry_size llq_ring_entry_size;
62*4882a593Smuzhiyun 	enum ena_admin_llq_stride_ctrl  llq_stride_ctrl;
63*4882a593Smuzhiyun 	enum ena_admin_llq_num_descs_before_header llq_num_decs_before_header;
64*4882a593Smuzhiyun 	u16 llq_ring_entry_size_value;
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun enum queue_direction {
68*4882a593Smuzhiyun 	ENA_COM_IO_QUEUE_DIRECTION_TX,
69*4882a593Smuzhiyun 	ENA_COM_IO_QUEUE_DIRECTION_RX
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun struct ena_com_buf {
73*4882a593Smuzhiyun 	dma_addr_t paddr; /**< Buffer physical address */
74*4882a593Smuzhiyun 	u16 len; /**< Buffer length in bytes */
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun struct ena_com_rx_buf_info {
78*4882a593Smuzhiyun 	u16 len;
79*4882a593Smuzhiyun 	u16 req_id;
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun struct ena_com_io_desc_addr {
83*4882a593Smuzhiyun 	u8 __iomem *pbuf_dev_addr; /* LLQ address */
84*4882a593Smuzhiyun 	u8 *virt_addr;
85*4882a593Smuzhiyun 	dma_addr_t phys_addr;
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun struct ena_com_tx_meta {
89*4882a593Smuzhiyun 	u16 mss;
90*4882a593Smuzhiyun 	u16 l3_hdr_len;
91*4882a593Smuzhiyun 	u16 l3_hdr_offset;
92*4882a593Smuzhiyun 	u16 l4_hdr_len; /* In words */
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun struct ena_com_llq_info {
96*4882a593Smuzhiyun 	u16 header_location_ctrl;
97*4882a593Smuzhiyun 	u16 desc_stride_ctrl;
98*4882a593Smuzhiyun 	u16 desc_list_entry_size_ctrl;
99*4882a593Smuzhiyun 	u16 desc_list_entry_size;
100*4882a593Smuzhiyun 	u16 descs_num_before_header;
101*4882a593Smuzhiyun 	u16 descs_per_entry;
102*4882a593Smuzhiyun 	u16 max_entries_in_tx_burst;
103*4882a593Smuzhiyun 	bool disable_meta_caching;
104*4882a593Smuzhiyun };
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun struct ena_com_io_cq {
107*4882a593Smuzhiyun 	struct ena_com_io_desc_addr cdesc_addr;
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	/* Interrupt unmask register */
110*4882a593Smuzhiyun 	u32 __iomem *unmask_reg;
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	/* The completion queue head doorbell register */
113*4882a593Smuzhiyun 	u32 __iomem *cq_head_db_reg;
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	/* numa configuration register (for TPH) */
116*4882a593Smuzhiyun 	u32 __iomem *numa_node_cfg_reg;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	/* The value to write to the above register to unmask
119*4882a593Smuzhiyun 	 * the interrupt of this queue
120*4882a593Smuzhiyun 	 */
121*4882a593Smuzhiyun 	u32 msix_vector;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	enum queue_direction direction;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	/* holds the number of cdesc of the current packet */
126*4882a593Smuzhiyun 	u16 cur_rx_pkt_cdesc_count;
127*4882a593Smuzhiyun 	/* save the firt cdesc idx of the current packet */
128*4882a593Smuzhiyun 	u16 cur_rx_pkt_cdesc_start_idx;
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	u16 q_depth;
131*4882a593Smuzhiyun 	/* Caller qid */
132*4882a593Smuzhiyun 	u16 qid;
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	/* Device queue index */
135*4882a593Smuzhiyun 	u16 idx;
136*4882a593Smuzhiyun 	u16 head;
137*4882a593Smuzhiyun 	u16 last_head_update;
138*4882a593Smuzhiyun 	u8 phase;
139*4882a593Smuzhiyun 	u8 cdesc_entry_size_in_bytes;
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun } ____cacheline_aligned;
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun struct ena_com_io_bounce_buffer_control {
144*4882a593Smuzhiyun 	u8 *base_buffer;
145*4882a593Smuzhiyun 	u16 next_to_use;
146*4882a593Smuzhiyun 	u16 buffer_size;
147*4882a593Smuzhiyun 	u16 buffers_num;  /* Must be a power of 2 */
148*4882a593Smuzhiyun };
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun /* This struct is to keep tracking the current location of the next llq entry */
151*4882a593Smuzhiyun struct ena_com_llq_pkt_ctrl {
152*4882a593Smuzhiyun 	u8 *curr_bounce_buf;
153*4882a593Smuzhiyun 	u16 idx;
154*4882a593Smuzhiyun 	u16 descs_left_in_line;
155*4882a593Smuzhiyun };
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun struct ena_com_io_sq {
158*4882a593Smuzhiyun 	struct ena_com_io_desc_addr desc_addr;
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	u32 __iomem *db_addr;
161*4882a593Smuzhiyun 	u8 __iomem *header_addr;
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	enum queue_direction direction;
164*4882a593Smuzhiyun 	enum ena_admin_placement_policy_type mem_queue_type;
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun 	bool disable_meta_caching;
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	u32 msix_vector;
169*4882a593Smuzhiyun 	struct ena_com_tx_meta cached_tx_meta;
170*4882a593Smuzhiyun 	struct ena_com_llq_info llq_info;
171*4882a593Smuzhiyun 	struct ena_com_llq_pkt_ctrl llq_buf_ctrl;
172*4882a593Smuzhiyun 	struct ena_com_io_bounce_buffer_control bounce_buf_ctrl;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	u16 q_depth;
175*4882a593Smuzhiyun 	u16 qid;
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	u16 idx;
178*4882a593Smuzhiyun 	u16 tail;
179*4882a593Smuzhiyun 	u16 next_to_comp;
180*4882a593Smuzhiyun 	u16 llq_last_copy_tail;
181*4882a593Smuzhiyun 	u32 tx_max_header_size;
182*4882a593Smuzhiyun 	u8 phase;
183*4882a593Smuzhiyun 	u8 desc_entry_size;
184*4882a593Smuzhiyun 	u8 dma_addr_bits;
185*4882a593Smuzhiyun 	u16 entries_in_tx_burst_left;
186*4882a593Smuzhiyun } ____cacheline_aligned;
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun struct ena_com_admin_cq {
189*4882a593Smuzhiyun 	struct ena_admin_acq_entry *entries;
190*4882a593Smuzhiyun 	dma_addr_t dma_addr;
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 	u16 head;
193*4882a593Smuzhiyun 	u8 phase;
194*4882a593Smuzhiyun };
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun struct ena_com_admin_sq {
197*4882a593Smuzhiyun 	struct ena_admin_aq_entry *entries;
198*4882a593Smuzhiyun 	dma_addr_t dma_addr;
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	u32 __iomem *db_addr;
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	u16 head;
203*4882a593Smuzhiyun 	u16 tail;
204*4882a593Smuzhiyun 	u8 phase;
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun };
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun struct ena_com_stats_admin {
209*4882a593Smuzhiyun 	u64 aborted_cmd;
210*4882a593Smuzhiyun 	u64 submitted_cmd;
211*4882a593Smuzhiyun 	u64 completed_cmd;
212*4882a593Smuzhiyun 	u64 out_of_space;
213*4882a593Smuzhiyun 	u64 no_completion;
214*4882a593Smuzhiyun };
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun struct ena_com_admin_queue {
217*4882a593Smuzhiyun 	void *q_dmadev;
218*4882a593Smuzhiyun 	struct ena_com_dev *ena_dev;
219*4882a593Smuzhiyun 	spinlock_t q_lock; /* spinlock for the admin queue */
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 	struct ena_comp_ctx *comp_ctx;
222*4882a593Smuzhiyun 	u32 completion_timeout;
223*4882a593Smuzhiyun 	u16 q_depth;
224*4882a593Smuzhiyun 	struct ena_com_admin_cq cq;
225*4882a593Smuzhiyun 	struct ena_com_admin_sq sq;
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun 	/* Indicate if the admin queue should poll for completion */
228*4882a593Smuzhiyun 	bool polling;
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun 	/* Define if fallback to polling mode should occur */
231*4882a593Smuzhiyun 	bool auto_polling;
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun 	u16 curr_cmd_id;
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun 	/* Indicate that the ena was initialized and can
236*4882a593Smuzhiyun 	 * process new admin commands
237*4882a593Smuzhiyun 	 */
238*4882a593Smuzhiyun 	bool running_state;
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun 	/* Count the number of outstanding admin commands */
241*4882a593Smuzhiyun 	atomic_t outstanding_cmds;
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	struct ena_com_stats_admin stats;
244*4882a593Smuzhiyun };
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun struct ena_aenq_handlers;
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun struct ena_com_aenq {
249*4882a593Smuzhiyun 	u16 head;
250*4882a593Smuzhiyun 	u8 phase;
251*4882a593Smuzhiyun 	struct ena_admin_aenq_entry *entries;
252*4882a593Smuzhiyun 	dma_addr_t dma_addr;
253*4882a593Smuzhiyun 	u16 q_depth;
254*4882a593Smuzhiyun 	struct ena_aenq_handlers *aenq_handlers;
255*4882a593Smuzhiyun };
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun struct ena_com_mmio_read {
258*4882a593Smuzhiyun 	struct ena_admin_ena_mmio_req_read_less_resp *read_resp;
259*4882a593Smuzhiyun 	dma_addr_t read_resp_dma_addr;
260*4882a593Smuzhiyun 	u32 reg_read_to; /* in us */
261*4882a593Smuzhiyun 	u16 seq_num;
262*4882a593Smuzhiyun 	bool readless_supported;
263*4882a593Smuzhiyun 	/* spin lock to ensure a single outstanding read */
264*4882a593Smuzhiyun 	spinlock_t lock;
265*4882a593Smuzhiyun };
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun struct ena_rss {
268*4882a593Smuzhiyun 	/* Indirect table */
269*4882a593Smuzhiyun 	u16 *host_rss_ind_tbl;
270*4882a593Smuzhiyun 	struct ena_admin_rss_ind_table_entry *rss_ind_tbl;
271*4882a593Smuzhiyun 	dma_addr_t rss_ind_tbl_dma_addr;
272*4882a593Smuzhiyun 	u16 tbl_log_size;
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun 	/* Hash key */
275*4882a593Smuzhiyun 	enum ena_admin_hash_functions hash_func;
276*4882a593Smuzhiyun 	struct ena_admin_feature_rss_flow_hash_control *hash_key;
277*4882a593Smuzhiyun 	dma_addr_t hash_key_dma_addr;
278*4882a593Smuzhiyun 	u32 hash_init_val;
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun 	/* Flow Control */
281*4882a593Smuzhiyun 	struct ena_admin_feature_rss_hash_control *hash_ctrl;
282*4882a593Smuzhiyun 	dma_addr_t hash_ctrl_dma_addr;
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun };
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun struct ena_host_attribute {
287*4882a593Smuzhiyun 	/* Debug area */
288*4882a593Smuzhiyun 	u8 *debug_area_virt_addr;
289*4882a593Smuzhiyun 	dma_addr_t debug_area_dma_addr;
290*4882a593Smuzhiyun 	u32 debug_area_size;
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 	/* Host information */
293*4882a593Smuzhiyun 	struct ena_admin_host_info *host_info;
294*4882a593Smuzhiyun 	dma_addr_t host_info_dma_addr;
295*4882a593Smuzhiyun };
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun /* Each ena_dev is a PCI function. */
298*4882a593Smuzhiyun struct ena_com_dev {
299*4882a593Smuzhiyun 	struct ena_com_admin_queue admin_queue;
300*4882a593Smuzhiyun 	struct ena_com_aenq aenq;
301*4882a593Smuzhiyun 	struct ena_com_io_cq io_cq_queues[ENA_TOTAL_NUM_QUEUES];
302*4882a593Smuzhiyun 	struct ena_com_io_sq io_sq_queues[ENA_TOTAL_NUM_QUEUES];
303*4882a593Smuzhiyun 	u8 __iomem *reg_bar;
304*4882a593Smuzhiyun 	void __iomem *mem_bar;
305*4882a593Smuzhiyun 	void *dmadev;
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 	enum ena_admin_placement_policy_type tx_mem_queue_type;
308*4882a593Smuzhiyun 	u32 tx_max_header_size;
309*4882a593Smuzhiyun 	u16 stats_func; /* Selected function for extended statistic dump */
310*4882a593Smuzhiyun 	u16 stats_queue; /* Selected queue for extended statistic dump */
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	struct ena_com_mmio_read mmio_read;
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun 	struct ena_rss rss;
315*4882a593Smuzhiyun 	u32 supported_features;
316*4882a593Smuzhiyun 	u32 dma_addr_bits;
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun 	struct ena_host_attribute host_attr;
319*4882a593Smuzhiyun 	bool adaptive_coalescing;
320*4882a593Smuzhiyun 	u16 intr_delay_resolution;
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun 	/* interrupt moderation intervals are in usec divided by
323*4882a593Smuzhiyun 	 * intr_delay_resolution, which is supplied by the device.
324*4882a593Smuzhiyun 	 */
325*4882a593Smuzhiyun 	u32 intr_moder_tx_interval;
326*4882a593Smuzhiyun 	u32 intr_moder_rx_interval;
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun 	struct ena_intr_moder_entry *intr_moder_tbl;
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun 	struct ena_com_llq_info llq_info;
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun 	u32 ena_min_poll_delay_us;
333*4882a593Smuzhiyun };
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun struct ena_com_dev_get_features_ctx {
336*4882a593Smuzhiyun 	struct ena_admin_queue_feature_desc max_queues;
337*4882a593Smuzhiyun 	struct ena_admin_queue_ext_feature_desc max_queue_ext;
338*4882a593Smuzhiyun 	struct ena_admin_device_attr_feature_desc dev_attr;
339*4882a593Smuzhiyun 	struct ena_admin_feature_aenq_desc aenq;
340*4882a593Smuzhiyun 	struct ena_admin_feature_offload_desc offload;
341*4882a593Smuzhiyun 	struct ena_admin_ena_hw_hints hw_hints;
342*4882a593Smuzhiyun 	struct ena_admin_feature_llq_desc llq;
343*4882a593Smuzhiyun };
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun struct ena_com_create_io_ctx {
346*4882a593Smuzhiyun 	enum ena_admin_placement_policy_type mem_queue_type;
347*4882a593Smuzhiyun 	enum queue_direction direction;
348*4882a593Smuzhiyun 	int numa_node;
349*4882a593Smuzhiyun 	u32 msix_vector;
350*4882a593Smuzhiyun 	u16 queue_size;
351*4882a593Smuzhiyun 	u16 qid;
352*4882a593Smuzhiyun };
353*4882a593Smuzhiyun 
354*4882a593Smuzhiyun typedef void (*ena_aenq_handler)(void *data,
355*4882a593Smuzhiyun 	struct ena_admin_aenq_entry *aenq_e);
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun /* Holds aenq handlers. Indexed by AENQ event group */
358*4882a593Smuzhiyun struct ena_aenq_handlers {
359*4882a593Smuzhiyun 	ena_aenq_handler handlers[ENA_MAX_HANDLERS];
360*4882a593Smuzhiyun 	ena_aenq_handler unimplemented_handler;
361*4882a593Smuzhiyun };
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun /*****************************************************************************/
364*4882a593Smuzhiyun /*****************************************************************************/
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun /* ena_com_mmio_reg_read_request_init - Init the mmio reg read mechanism
367*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
368*4882a593Smuzhiyun  *
369*4882a593Smuzhiyun  * Initialize the register read mechanism.
370*4882a593Smuzhiyun  *
371*4882a593Smuzhiyun  * @note: This method must be the first stage in the initialization sequence.
372*4882a593Smuzhiyun  *
373*4882a593Smuzhiyun  * @return - 0 on success, negative value on failure.
374*4882a593Smuzhiyun  */
375*4882a593Smuzhiyun int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev);
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun /* ena_com_set_mmio_read_mode - Enable/disable the indirect mmio reg read mechanism
378*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
379*4882a593Smuzhiyun  * @readless_supported: readless mode (enable/disable)
380*4882a593Smuzhiyun  */
381*4882a593Smuzhiyun void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev,
382*4882a593Smuzhiyun 				bool readless_supported);
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun /* ena_com_mmio_reg_read_request_write_dev_addr - Write the mmio reg read return
385*4882a593Smuzhiyun  * value physical address.
386*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
387*4882a593Smuzhiyun  */
388*4882a593Smuzhiyun void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev);
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun /* ena_com_mmio_reg_read_request_destroy - Destroy the mmio reg read mechanism
391*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
392*4882a593Smuzhiyun  */
393*4882a593Smuzhiyun void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev);
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun /* ena_com_admin_init - Init the admin and the async queues
396*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
397*4882a593Smuzhiyun  * @aenq_handlers: Those handlers to be called upon event.
398*4882a593Smuzhiyun  *
399*4882a593Smuzhiyun  * Initialize the admin submission and completion queues.
400*4882a593Smuzhiyun  * Initialize the asynchronous events notification queues.
401*4882a593Smuzhiyun  *
402*4882a593Smuzhiyun  * @return - 0 on success, negative value on failure.
403*4882a593Smuzhiyun  */
404*4882a593Smuzhiyun int ena_com_admin_init(struct ena_com_dev *ena_dev,
405*4882a593Smuzhiyun 		       struct ena_aenq_handlers *aenq_handlers);
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun /* ena_com_admin_destroy - Destroy the admin and the async events queues.
408*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
409*4882a593Smuzhiyun  *
410*4882a593Smuzhiyun  * @note: Before calling this method, the caller must validate that the device
411*4882a593Smuzhiyun  * won't send any additional admin completions/aenq.
412*4882a593Smuzhiyun  * To achieve that, a FLR is recommended.
413*4882a593Smuzhiyun  */
414*4882a593Smuzhiyun void ena_com_admin_destroy(struct ena_com_dev *ena_dev);
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun /* ena_com_dev_reset - Perform device FLR to the device.
417*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
418*4882a593Smuzhiyun  * @reset_reason: Specify what is the trigger for the reset in case of an error.
419*4882a593Smuzhiyun  *
420*4882a593Smuzhiyun  * @return - 0 on success, negative value on failure.
421*4882a593Smuzhiyun  */
422*4882a593Smuzhiyun int ena_com_dev_reset(struct ena_com_dev *ena_dev,
423*4882a593Smuzhiyun 		      enum ena_regs_reset_reason_types reset_reason);
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun /* ena_com_create_io_queue - Create io queue.
426*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
427*4882a593Smuzhiyun  * @ctx - create context structure
428*4882a593Smuzhiyun  *
429*4882a593Smuzhiyun  * Create the submission and the completion queues.
430*4882a593Smuzhiyun  *
431*4882a593Smuzhiyun  * @return - 0 on success, negative value on failure.
432*4882a593Smuzhiyun  */
433*4882a593Smuzhiyun int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
434*4882a593Smuzhiyun 			    struct ena_com_create_io_ctx *ctx);
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun /* ena_com_destroy_io_queue - Destroy IO queue with the queue id - qid.
437*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
438*4882a593Smuzhiyun  * @qid - the caller virtual queue id.
439*4882a593Smuzhiyun  */
440*4882a593Smuzhiyun void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid);
441*4882a593Smuzhiyun 
442*4882a593Smuzhiyun /* ena_com_get_io_handlers - Return the io queue handlers
443*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
444*4882a593Smuzhiyun  * @qid - the caller virtual queue id.
445*4882a593Smuzhiyun  * @io_sq - IO submission queue handler
446*4882a593Smuzhiyun  * @io_cq - IO completion queue handler.
447*4882a593Smuzhiyun  *
448*4882a593Smuzhiyun  * @return - 0 on success, negative value on failure.
449*4882a593Smuzhiyun  */
450*4882a593Smuzhiyun int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
451*4882a593Smuzhiyun 			    struct ena_com_io_sq **io_sq,
452*4882a593Smuzhiyun 			    struct ena_com_io_cq **io_cq);
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun /* ena_com_admin_aenq_enable - ENAble asynchronous event notifications
455*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
456*4882a593Smuzhiyun  *
457*4882a593Smuzhiyun  * After this method, aenq event can be received via AENQ.
458*4882a593Smuzhiyun  */
459*4882a593Smuzhiyun void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev);
460*4882a593Smuzhiyun 
461*4882a593Smuzhiyun /* ena_com_set_admin_running_state - Set the state of the admin queue
462*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
463*4882a593Smuzhiyun  *
464*4882a593Smuzhiyun  * Change the state of the admin queue (enable/disable)
465*4882a593Smuzhiyun  */
466*4882a593Smuzhiyun void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state);
467*4882a593Smuzhiyun 
468*4882a593Smuzhiyun /* ena_com_get_admin_running_state - Get the admin queue state
469*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
470*4882a593Smuzhiyun  *
471*4882a593Smuzhiyun  * Retrieve the state of the admin queue (enable/disable)
472*4882a593Smuzhiyun  *
473*4882a593Smuzhiyun  * @return - current polling mode (enable/disable)
474*4882a593Smuzhiyun  */
475*4882a593Smuzhiyun bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev);
476*4882a593Smuzhiyun 
477*4882a593Smuzhiyun /* ena_com_set_admin_polling_mode - Set the admin completion queue polling mode
478*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
479*4882a593Smuzhiyun  * @polling: ENAble/Disable polling mode
480*4882a593Smuzhiyun  *
481*4882a593Smuzhiyun  * Set the admin completion mode.
482*4882a593Smuzhiyun  */
483*4882a593Smuzhiyun void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling);
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun /* ena_com_set_admin_auto_polling_mode - Enable autoswitch to polling mode
486*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
487*4882a593Smuzhiyun  * @polling: Enable/Disable polling mode
488*4882a593Smuzhiyun  *
489*4882a593Smuzhiyun  * Set the autopolling mode.
490*4882a593Smuzhiyun  * If autopolling is on:
491*4882a593Smuzhiyun  * In case of missing interrupt when data is available switch to polling.
492*4882a593Smuzhiyun  */
493*4882a593Smuzhiyun void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev,
494*4882a593Smuzhiyun 					 bool polling);
495*4882a593Smuzhiyun 
496*4882a593Smuzhiyun /* ena_com_admin_q_comp_intr_handler - admin queue interrupt handler
497*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
498*4882a593Smuzhiyun  *
499*4882a593Smuzhiyun  * This method goes over the admin completion queue and wakes up all the pending
500*4882a593Smuzhiyun  * threads that wait on the commands wait event.
501*4882a593Smuzhiyun  *
502*4882a593Smuzhiyun  * @note: Should be called after MSI-X interrupt.
503*4882a593Smuzhiyun  */
504*4882a593Smuzhiyun void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev);
505*4882a593Smuzhiyun 
506*4882a593Smuzhiyun /* ena_com_aenq_intr_handler - AENQ interrupt handler
507*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
508*4882a593Smuzhiyun  *
509*4882a593Smuzhiyun  * This method goes over the async event notification queue and calls the proper
510*4882a593Smuzhiyun  * aenq handler.
511*4882a593Smuzhiyun  */
512*4882a593Smuzhiyun void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data);
513*4882a593Smuzhiyun 
514*4882a593Smuzhiyun /* ena_com_abort_admin_commands - Abort all the outstanding admin commands.
515*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
516*4882a593Smuzhiyun  *
517*4882a593Smuzhiyun  * This method aborts all the outstanding admin commands.
518*4882a593Smuzhiyun  * The caller should then call ena_com_wait_for_abort_completion to make sure
519*4882a593Smuzhiyun  * all the commands were completed.
520*4882a593Smuzhiyun  */
521*4882a593Smuzhiyun void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev);
522*4882a593Smuzhiyun 
523*4882a593Smuzhiyun /* ena_com_wait_for_abort_completion - Wait for admin commands abort.
524*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
525*4882a593Smuzhiyun  *
526*4882a593Smuzhiyun  * This method waits until all the outstanding admin commands are completed.
527*4882a593Smuzhiyun  */
528*4882a593Smuzhiyun void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev);
529*4882a593Smuzhiyun 
530*4882a593Smuzhiyun /* ena_com_validate_version - Validate the device parameters
531*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
532*4882a593Smuzhiyun  *
533*4882a593Smuzhiyun  * This method verifies the device parameters are the same as the saved
534*4882a593Smuzhiyun  * parameters in ena_dev.
535*4882a593Smuzhiyun  * This method is useful after device reset, to validate the device mac address
536*4882a593Smuzhiyun  * and the device offloads are the same as before the reset.
537*4882a593Smuzhiyun  *
538*4882a593Smuzhiyun  * @return - 0 on success negative value otherwise.
539*4882a593Smuzhiyun  */
540*4882a593Smuzhiyun int ena_com_validate_version(struct ena_com_dev *ena_dev);
541*4882a593Smuzhiyun 
542*4882a593Smuzhiyun /* ena_com_get_link_params - Retrieve physical link parameters.
543*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
544*4882a593Smuzhiyun  * @resp: Link parameters
545*4882a593Smuzhiyun  *
546*4882a593Smuzhiyun  * Retrieve the physical link parameters,
547*4882a593Smuzhiyun  * like speed, auto-negotiation and full duplex support.
548*4882a593Smuzhiyun  *
549*4882a593Smuzhiyun  * @return - 0 on Success negative value otherwise.
550*4882a593Smuzhiyun  */
551*4882a593Smuzhiyun int ena_com_get_link_params(struct ena_com_dev *ena_dev,
552*4882a593Smuzhiyun 			    struct ena_admin_get_feat_resp *resp);
553*4882a593Smuzhiyun 
554*4882a593Smuzhiyun /* ena_com_get_dma_width - Retrieve physical dma address width the device
555*4882a593Smuzhiyun  * supports.
556*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
557*4882a593Smuzhiyun  *
558*4882a593Smuzhiyun  * Retrieve the maximum physical address bits the device can handle.
559*4882a593Smuzhiyun  *
560*4882a593Smuzhiyun  * @return: > 0 on Success and negative value otherwise.
561*4882a593Smuzhiyun  */
562*4882a593Smuzhiyun int ena_com_get_dma_width(struct ena_com_dev *ena_dev);
563*4882a593Smuzhiyun 
564*4882a593Smuzhiyun /* ena_com_set_aenq_config - Set aenq groups configurations
565*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
566*4882a593Smuzhiyun  * @groups flag: bit fields flags of enum ena_admin_aenq_group.
567*4882a593Smuzhiyun  *
568*4882a593Smuzhiyun  * Configure which aenq event group the driver would like to receive.
569*4882a593Smuzhiyun  *
570*4882a593Smuzhiyun  * @return: 0 on Success and negative value otherwise.
571*4882a593Smuzhiyun  */
572*4882a593Smuzhiyun int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag);
573*4882a593Smuzhiyun 
574*4882a593Smuzhiyun /* ena_com_get_dev_attr_feat - Get device features
575*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
576*4882a593Smuzhiyun  * @get_feat_ctx: returned context that contain the get features.
577*4882a593Smuzhiyun  *
578*4882a593Smuzhiyun  * @return: 0 on Success and negative value otherwise.
579*4882a593Smuzhiyun  */
580*4882a593Smuzhiyun int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
581*4882a593Smuzhiyun 			      struct ena_com_dev_get_features_ctx *get_feat_ctx);
582*4882a593Smuzhiyun 
583*4882a593Smuzhiyun /* ena_com_get_dev_basic_stats - Get device basic statistics
584*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
585*4882a593Smuzhiyun  * @stats: stats return value
586*4882a593Smuzhiyun  *
587*4882a593Smuzhiyun  * @return: 0 on Success and negative value otherwise.
588*4882a593Smuzhiyun  */
589*4882a593Smuzhiyun int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
590*4882a593Smuzhiyun 				struct ena_admin_basic_stats *stats);
591*4882a593Smuzhiyun 
592*4882a593Smuzhiyun /* ena_com_get_eni_stats - Get extended network interface statistics
593*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
594*4882a593Smuzhiyun  * @stats: stats return value
595*4882a593Smuzhiyun  *
596*4882a593Smuzhiyun  * @return: 0 on Success and negative value otherwise.
597*4882a593Smuzhiyun  */
598*4882a593Smuzhiyun int ena_com_get_eni_stats(struct ena_com_dev *ena_dev,
599*4882a593Smuzhiyun 			  struct ena_admin_eni_stats *stats);
600*4882a593Smuzhiyun 
601*4882a593Smuzhiyun /* ena_com_set_dev_mtu - Configure the device mtu.
602*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
603*4882a593Smuzhiyun  * @mtu: mtu value
604*4882a593Smuzhiyun  *
605*4882a593Smuzhiyun  * @return: 0 on Success and negative value otherwise.
606*4882a593Smuzhiyun  */
607*4882a593Smuzhiyun int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu);
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun /* ena_com_get_offload_settings - Retrieve the device offloads capabilities
610*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
611*4882a593Smuzhiyun  * @offlad: offload return value
612*4882a593Smuzhiyun  *
613*4882a593Smuzhiyun  * @return: 0 on Success and negative value otherwise.
614*4882a593Smuzhiyun  */
615*4882a593Smuzhiyun int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
616*4882a593Smuzhiyun 				 struct ena_admin_feature_offload_desc *offload);
617*4882a593Smuzhiyun 
618*4882a593Smuzhiyun /* ena_com_rss_init - Init RSS
619*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
620*4882a593Smuzhiyun  * @log_size: indirection log size
621*4882a593Smuzhiyun  *
622*4882a593Smuzhiyun  * Allocate RSS/RFS resources.
623*4882a593Smuzhiyun  * The caller then can configure rss using ena_com_set_hash_function,
624*4882a593Smuzhiyun  * ena_com_set_hash_ctrl and ena_com_indirect_table_set.
625*4882a593Smuzhiyun  *
626*4882a593Smuzhiyun  * @return: 0 on Success and negative value otherwise.
627*4882a593Smuzhiyun  */
628*4882a593Smuzhiyun int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 log_size);
629*4882a593Smuzhiyun 
630*4882a593Smuzhiyun /* ena_com_rss_destroy - Destroy rss
631*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
632*4882a593Smuzhiyun  *
633*4882a593Smuzhiyun  * Free all the RSS/RFS resources.
634*4882a593Smuzhiyun  */
635*4882a593Smuzhiyun void ena_com_rss_destroy(struct ena_com_dev *ena_dev);
636*4882a593Smuzhiyun 
637*4882a593Smuzhiyun /* ena_com_get_current_hash_function - Get RSS hash function
638*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
639*4882a593Smuzhiyun  *
640*4882a593Smuzhiyun  * Return the current hash function.
641*4882a593Smuzhiyun  * @return: 0 or one of the ena_admin_hash_functions values.
642*4882a593Smuzhiyun  */
643*4882a593Smuzhiyun int ena_com_get_current_hash_function(struct ena_com_dev *ena_dev);
644*4882a593Smuzhiyun 
645*4882a593Smuzhiyun /* ena_com_fill_hash_function - Fill RSS hash function
646*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
647*4882a593Smuzhiyun  * @func: The hash function (Toeplitz or crc)
648*4882a593Smuzhiyun  * @key: Hash key (for toeplitz hash)
649*4882a593Smuzhiyun  * @key_len: key length (max length 10 DW)
650*4882a593Smuzhiyun  * @init_val: initial value for the hash function
651*4882a593Smuzhiyun  *
652*4882a593Smuzhiyun  * Fill the ena_dev resources with the desire hash function, hash key, key_len
653*4882a593Smuzhiyun  * and key initial value (if needed by the hash function).
654*4882a593Smuzhiyun  * To flush the key into the device the caller should call
655*4882a593Smuzhiyun  * ena_com_set_hash_function.
656*4882a593Smuzhiyun  *
657*4882a593Smuzhiyun  * @return: 0 on Success and negative value otherwise.
658*4882a593Smuzhiyun  */
659*4882a593Smuzhiyun int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
660*4882a593Smuzhiyun 			       enum ena_admin_hash_functions func,
661*4882a593Smuzhiyun 			       const u8 *key, u16 key_len, u32 init_val);
662*4882a593Smuzhiyun 
663*4882a593Smuzhiyun /* ena_com_set_hash_function - Flush the hash function and it dependencies to
664*4882a593Smuzhiyun  * the device.
665*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
666*4882a593Smuzhiyun  *
667*4882a593Smuzhiyun  * Flush the hash function and it dependencies (key, key length and
668*4882a593Smuzhiyun  * initial value) if needed.
669*4882a593Smuzhiyun  *
670*4882a593Smuzhiyun  * @note: Prior to this method the caller should call ena_com_fill_hash_function
671*4882a593Smuzhiyun  *
672*4882a593Smuzhiyun  * @return: 0 on Success and negative value otherwise.
673*4882a593Smuzhiyun  */
674*4882a593Smuzhiyun int ena_com_set_hash_function(struct ena_com_dev *ena_dev);
675*4882a593Smuzhiyun 
676*4882a593Smuzhiyun /* ena_com_get_hash_function - Retrieve the hash function from the device.
677*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
678*4882a593Smuzhiyun  * @func: hash function
679*4882a593Smuzhiyun  *
680*4882a593Smuzhiyun  * Retrieve the hash function from the device.
681*4882a593Smuzhiyun  *
682*4882a593Smuzhiyun  * @note: If the caller called ena_com_fill_hash_function but didn't flush
683*4882a593Smuzhiyun  * it to the device, the new configuration will be lost.
684*4882a593Smuzhiyun  *
685*4882a593Smuzhiyun  * @return: 0 on Success and negative value otherwise.
686*4882a593Smuzhiyun  */
687*4882a593Smuzhiyun int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
688*4882a593Smuzhiyun 			      enum ena_admin_hash_functions *func);
689*4882a593Smuzhiyun 
690*4882a593Smuzhiyun /* ena_com_get_hash_key - Retrieve the hash key
691*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
692*4882a593Smuzhiyun  * @key: hash key
693*4882a593Smuzhiyun  *
694*4882a593Smuzhiyun  * Retrieve the hash key.
695*4882a593Smuzhiyun  *
696*4882a593Smuzhiyun  * @note: If the caller called ena_com_fill_hash_key but didn't flush
697*4882a593Smuzhiyun  * it to the device, the new configuration will be lost.
698*4882a593Smuzhiyun  *
699*4882a593Smuzhiyun  * @return: 0 on Success and negative value otherwise.
700*4882a593Smuzhiyun  */
701*4882a593Smuzhiyun int ena_com_get_hash_key(struct ena_com_dev *ena_dev, u8 *key);
702*4882a593Smuzhiyun /* ena_com_fill_hash_ctrl - Fill RSS hash control
703*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct.
704*4882a593Smuzhiyun  * @proto: The protocol to configure.
705*4882a593Smuzhiyun  * @hash_fields: bit mask of ena_admin_flow_hash_fields
706*4882a593Smuzhiyun  *
707*4882a593Smuzhiyun  * Fill the ena_dev resources with the desire hash control (the ethernet
708*4882a593Smuzhiyun  * fields that take part of the hash) for a specific protocol.
709*4882a593Smuzhiyun  * To flush the hash control to the device, the caller should call
710*4882a593Smuzhiyun  * ena_com_set_hash_ctrl.
711*4882a593Smuzhiyun  *
712*4882a593Smuzhiyun  * @return: 0 on Success and negative value otherwise.
713*4882a593Smuzhiyun  */
714*4882a593Smuzhiyun int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
715*4882a593Smuzhiyun 			   enum ena_admin_flow_hash_proto proto,
716*4882a593Smuzhiyun 			   u16 hash_fields);
717*4882a593Smuzhiyun 
718*4882a593Smuzhiyun /* ena_com_set_hash_ctrl - Flush the hash control resources to the device.
719*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
720*4882a593Smuzhiyun  *
721*4882a593Smuzhiyun  * Flush the hash control (the ethernet fields that take part of the hash)
722*4882a593Smuzhiyun  *
723*4882a593Smuzhiyun  * @note: Prior to this method the caller should call ena_com_fill_hash_ctrl.
724*4882a593Smuzhiyun  *
725*4882a593Smuzhiyun  * @return: 0 on Success and negative value otherwise.
726*4882a593Smuzhiyun  */
727*4882a593Smuzhiyun int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev);
728*4882a593Smuzhiyun 
729*4882a593Smuzhiyun /* ena_com_get_hash_ctrl - Retrieve the hash control from the device.
730*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
731*4882a593Smuzhiyun  * @proto: The protocol to retrieve.
732*4882a593Smuzhiyun  * @fields: bit mask of ena_admin_flow_hash_fields.
733*4882a593Smuzhiyun  *
734*4882a593Smuzhiyun  * Retrieve the hash control from the device.
735*4882a593Smuzhiyun  *
736*4882a593Smuzhiyun  * @note: If the caller called ena_com_fill_hash_ctrl but didn't flush
737*4882a593Smuzhiyun  * it to the device, the new configuration will be lost.
738*4882a593Smuzhiyun  *
739*4882a593Smuzhiyun  * @return: 0 on Success and negative value otherwise.
740*4882a593Smuzhiyun  */
741*4882a593Smuzhiyun int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
742*4882a593Smuzhiyun 			  enum ena_admin_flow_hash_proto proto,
743*4882a593Smuzhiyun 			  u16 *fields);
744*4882a593Smuzhiyun 
745*4882a593Smuzhiyun /* ena_com_set_default_hash_ctrl - Set the hash control to a default
746*4882a593Smuzhiyun  * configuration.
747*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
748*4882a593Smuzhiyun  *
749*4882a593Smuzhiyun  * Fill the ena_dev resources with the default hash control configuration.
750*4882a593Smuzhiyun  * To flush the hash control to the device, the caller should call
751*4882a593Smuzhiyun  * ena_com_set_hash_ctrl.
752*4882a593Smuzhiyun  *
753*4882a593Smuzhiyun  * @return: 0 on Success and negative value otherwise.
754*4882a593Smuzhiyun  */
755*4882a593Smuzhiyun int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev);
756*4882a593Smuzhiyun 
757*4882a593Smuzhiyun /* ena_com_indirect_table_fill_entry - Fill a single entry in the RSS
758*4882a593Smuzhiyun  * indirection table
759*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct.
760*4882a593Smuzhiyun  * @entry_idx - indirection table entry.
761*4882a593Smuzhiyun  * @entry_value - redirection value
762*4882a593Smuzhiyun  *
763*4882a593Smuzhiyun  * Fill a single entry of the RSS indirection table in the ena_dev resources.
764*4882a593Smuzhiyun  * To flush the indirection table to the device, the called should call
765*4882a593Smuzhiyun  * ena_com_indirect_table_set.
766*4882a593Smuzhiyun  *
767*4882a593Smuzhiyun  * @return: 0 on Success and negative value otherwise.
768*4882a593Smuzhiyun  */
769*4882a593Smuzhiyun int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
770*4882a593Smuzhiyun 				      u16 entry_idx, u16 entry_value);
771*4882a593Smuzhiyun 
772*4882a593Smuzhiyun /* ena_com_indirect_table_set - Flush the indirection table to the device.
773*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
774*4882a593Smuzhiyun  *
775*4882a593Smuzhiyun  * Flush the indirection hash control to the device.
776*4882a593Smuzhiyun  * Prior to this method the caller should call ena_com_indirect_table_fill_entry
777*4882a593Smuzhiyun  *
778*4882a593Smuzhiyun  * @return: 0 on Success and negative value otherwise.
779*4882a593Smuzhiyun  */
780*4882a593Smuzhiyun int ena_com_indirect_table_set(struct ena_com_dev *ena_dev);
781*4882a593Smuzhiyun 
782*4882a593Smuzhiyun /* ena_com_indirect_table_get - Retrieve the indirection table from the device.
783*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
784*4882a593Smuzhiyun  * @ind_tbl: indirection table
785*4882a593Smuzhiyun  *
786*4882a593Smuzhiyun  * Retrieve the RSS indirection table from the device.
787*4882a593Smuzhiyun  *
788*4882a593Smuzhiyun  * @note: If the caller called ena_com_indirect_table_fill_entry but didn't flush
789*4882a593Smuzhiyun  * it to the device, the new configuration will be lost.
790*4882a593Smuzhiyun  *
791*4882a593Smuzhiyun  * @return: 0 on Success and negative value otherwise.
792*4882a593Smuzhiyun  */
793*4882a593Smuzhiyun int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl);
794*4882a593Smuzhiyun 
795*4882a593Smuzhiyun /* ena_com_allocate_host_info - Allocate host info resources.
796*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
797*4882a593Smuzhiyun  *
798*4882a593Smuzhiyun  * @return: 0 on Success and negative value otherwise.
799*4882a593Smuzhiyun  */
800*4882a593Smuzhiyun int ena_com_allocate_host_info(struct ena_com_dev *ena_dev);
801*4882a593Smuzhiyun 
802*4882a593Smuzhiyun /* ena_com_allocate_debug_area - Allocate debug area.
803*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
804*4882a593Smuzhiyun  * @debug_area_size - debug area size.
805*4882a593Smuzhiyun  *
806*4882a593Smuzhiyun  * @return: 0 on Success and negative value otherwise.
807*4882a593Smuzhiyun  */
808*4882a593Smuzhiyun int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
809*4882a593Smuzhiyun 				u32 debug_area_size);
810*4882a593Smuzhiyun 
811*4882a593Smuzhiyun /* ena_com_delete_debug_area - Free the debug area resources.
812*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
813*4882a593Smuzhiyun  *
814*4882a593Smuzhiyun  * Free the allocated debug area.
815*4882a593Smuzhiyun  */
816*4882a593Smuzhiyun void ena_com_delete_debug_area(struct ena_com_dev *ena_dev);
817*4882a593Smuzhiyun 
818*4882a593Smuzhiyun /* ena_com_delete_host_info - Free the host info resources.
819*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
820*4882a593Smuzhiyun  *
821*4882a593Smuzhiyun  * Free the allocated host info.
822*4882a593Smuzhiyun  */
823*4882a593Smuzhiyun void ena_com_delete_host_info(struct ena_com_dev *ena_dev);
824*4882a593Smuzhiyun 
825*4882a593Smuzhiyun /* ena_com_set_host_attributes - Update the device with the host
826*4882a593Smuzhiyun  * attributes (debug area and host info) base address.
827*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
828*4882a593Smuzhiyun  *
829*4882a593Smuzhiyun  * @return: 0 on Success and negative value otherwise.
830*4882a593Smuzhiyun  */
831*4882a593Smuzhiyun int ena_com_set_host_attributes(struct ena_com_dev *ena_dev);
832*4882a593Smuzhiyun 
833*4882a593Smuzhiyun /* ena_com_create_io_cq - Create io completion queue.
834*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
835*4882a593Smuzhiyun  * @io_cq - io completion queue handler
836*4882a593Smuzhiyun 
837*4882a593Smuzhiyun  * Create IO completion queue.
838*4882a593Smuzhiyun  *
839*4882a593Smuzhiyun  * @return - 0 on success, negative value on failure.
840*4882a593Smuzhiyun  */
841*4882a593Smuzhiyun int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
842*4882a593Smuzhiyun 			 struct ena_com_io_cq *io_cq);
843*4882a593Smuzhiyun 
844*4882a593Smuzhiyun /* ena_com_destroy_io_cq - Destroy io completion queue.
845*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
846*4882a593Smuzhiyun  * @io_cq - io completion queue handler
847*4882a593Smuzhiyun 
848*4882a593Smuzhiyun  * Destroy IO completion queue.
849*4882a593Smuzhiyun  *
850*4882a593Smuzhiyun  * @return - 0 on success, negative value on failure.
851*4882a593Smuzhiyun  */
852*4882a593Smuzhiyun int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
853*4882a593Smuzhiyun 			  struct ena_com_io_cq *io_cq);
854*4882a593Smuzhiyun 
855*4882a593Smuzhiyun /* ena_com_execute_admin_command - Execute admin command
856*4882a593Smuzhiyun  * @admin_queue: admin queue.
857*4882a593Smuzhiyun  * @cmd: the admin command to execute.
858*4882a593Smuzhiyun  * @cmd_size: the command size.
859*4882a593Smuzhiyun  * @cmd_completion: command completion return value.
860*4882a593Smuzhiyun  * @cmd_comp_size: command completion size.
861*4882a593Smuzhiyun 
862*4882a593Smuzhiyun  * Submit an admin command and then wait until the device returns a
863*4882a593Smuzhiyun  * completion.
864*4882a593Smuzhiyun  * The completion will be copied into cmd_comp.
865*4882a593Smuzhiyun  *
866*4882a593Smuzhiyun  * @return - 0 on success, negative value on failure.
867*4882a593Smuzhiyun  */
868*4882a593Smuzhiyun int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
869*4882a593Smuzhiyun 				  struct ena_admin_aq_entry *cmd,
870*4882a593Smuzhiyun 				  size_t cmd_size,
871*4882a593Smuzhiyun 				  struct ena_admin_acq_entry *cmd_comp,
872*4882a593Smuzhiyun 				  size_t cmd_comp_size);
873*4882a593Smuzhiyun 
874*4882a593Smuzhiyun /* ena_com_init_interrupt_moderation - Init interrupt moderation
875*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
876*4882a593Smuzhiyun  *
877*4882a593Smuzhiyun  * @return - 0 on success, negative value on failure.
878*4882a593Smuzhiyun  */
879*4882a593Smuzhiyun int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev);
880*4882a593Smuzhiyun 
881*4882a593Smuzhiyun /* ena_com_interrupt_moderation_supported - Return if interrupt moderation
882*4882a593Smuzhiyun  * capability is supported by the device.
883*4882a593Smuzhiyun  *
884*4882a593Smuzhiyun  * @return - supported or not.
885*4882a593Smuzhiyun  */
886*4882a593Smuzhiyun bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev);
887*4882a593Smuzhiyun 
888*4882a593Smuzhiyun /* ena_com_update_nonadaptive_moderation_interval_tx - Update the
889*4882a593Smuzhiyun  * non-adaptive interval in Tx direction.
890*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
891*4882a593Smuzhiyun  * @tx_coalesce_usecs: Interval in usec.
892*4882a593Smuzhiyun  *
893*4882a593Smuzhiyun  * @return - 0 on success, negative value on failure.
894*4882a593Smuzhiyun  */
895*4882a593Smuzhiyun int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
896*4882a593Smuzhiyun 						      u32 tx_coalesce_usecs);
897*4882a593Smuzhiyun 
898*4882a593Smuzhiyun /* ena_com_update_nonadaptive_moderation_interval_rx - Update the
899*4882a593Smuzhiyun  * non-adaptive interval in Rx direction.
900*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
901*4882a593Smuzhiyun  * @rx_coalesce_usecs: Interval in usec.
902*4882a593Smuzhiyun  *
903*4882a593Smuzhiyun  * @return - 0 on success, negative value on failure.
904*4882a593Smuzhiyun  */
905*4882a593Smuzhiyun int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
906*4882a593Smuzhiyun 						      u32 rx_coalesce_usecs);
907*4882a593Smuzhiyun 
908*4882a593Smuzhiyun /* ena_com_get_nonadaptive_moderation_interval_tx - Retrieve the
909*4882a593Smuzhiyun  * non-adaptive interval in Tx direction.
910*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
911*4882a593Smuzhiyun  *
912*4882a593Smuzhiyun  * @return - interval in usec
913*4882a593Smuzhiyun  */
914*4882a593Smuzhiyun unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev);
915*4882a593Smuzhiyun 
916*4882a593Smuzhiyun /* ena_com_get_nonadaptive_moderation_interval_rx - Retrieve the
917*4882a593Smuzhiyun  * non-adaptive interval in Rx direction.
918*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
919*4882a593Smuzhiyun  *
920*4882a593Smuzhiyun  * @return - interval in usec
921*4882a593Smuzhiyun  */
922*4882a593Smuzhiyun unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev);
923*4882a593Smuzhiyun 
924*4882a593Smuzhiyun /* ena_com_config_dev_mode - Configure the placement policy of the device.
925*4882a593Smuzhiyun  * @ena_dev: ENA communication layer struct
926*4882a593Smuzhiyun  * @llq_features: LLQ feature descriptor, retrieve via
927*4882a593Smuzhiyun  *		   ena_com_get_dev_attr_feat.
928*4882a593Smuzhiyun  * @ena_llq_config: The default driver LLQ parameters configurations
929*4882a593Smuzhiyun  */
930*4882a593Smuzhiyun int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
931*4882a593Smuzhiyun 			    struct ena_admin_feature_llq_desc *llq_features,
932*4882a593Smuzhiyun 			    struct ena_llq_configurations *llq_default_config);
933*4882a593Smuzhiyun 
ena_com_get_adaptive_moderation_enabled(struct ena_com_dev * ena_dev)934*4882a593Smuzhiyun static inline bool ena_com_get_adaptive_moderation_enabled(struct ena_com_dev *ena_dev)
935*4882a593Smuzhiyun {
936*4882a593Smuzhiyun 	return ena_dev->adaptive_coalescing;
937*4882a593Smuzhiyun }
938*4882a593Smuzhiyun 
ena_com_enable_adaptive_moderation(struct ena_com_dev * ena_dev)939*4882a593Smuzhiyun static inline void ena_com_enable_adaptive_moderation(struct ena_com_dev *ena_dev)
940*4882a593Smuzhiyun {
941*4882a593Smuzhiyun 	ena_dev->adaptive_coalescing = true;
942*4882a593Smuzhiyun }
943*4882a593Smuzhiyun 
ena_com_disable_adaptive_moderation(struct ena_com_dev * ena_dev)944*4882a593Smuzhiyun static inline void ena_com_disable_adaptive_moderation(struct ena_com_dev *ena_dev)
945*4882a593Smuzhiyun {
946*4882a593Smuzhiyun 	ena_dev->adaptive_coalescing = false;
947*4882a593Smuzhiyun }
948*4882a593Smuzhiyun 
949*4882a593Smuzhiyun /* ena_com_update_intr_reg - Prepare interrupt register
950*4882a593Smuzhiyun  * @intr_reg: interrupt register to update.
951*4882a593Smuzhiyun  * @rx_delay_interval: Rx interval in usecs
952*4882a593Smuzhiyun  * @tx_delay_interval: Tx interval in usecs
953*4882a593Smuzhiyun  * @unmask: unmask enable/disable
954*4882a593Smuzhiyun  *
955*4882a593Smuzhiyun  * Prepare interrupt update register with the supplied parameters.
956*4882a593Smuzhiyun  */
ena_com_update_intr_reg(struct ena_eth_io_intr_reg * intr_reg,u32 rx_delay_interval,u32 tx_delay_interval,bool unmask)957*4882a593Smuzhiyun static inline void ena_com_update_intr_reg(struct ena_eth_io_intr_reg *intr_reg,
958*4882a593Smuzhiyun 					   u32 rx_delay_interval,
959*4882a593Smuzhiyun 					   u32 tx_delay_interval,
960*4882a593Smuzhiyun 					   bool unmask)
961*4882a593Smuzhiyun {
962*4882a593Smuzhiyun 	intr_reg->intr_control = 0;
963*4882a593Smuzhiyun 	intr_reg->intr_control |= rx_delay_interval &
964*4882a593Smuzhiyun 		ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK;
965*4882a593Smuzhiyun 
966*4882a593Smuzhiyun 	intr_reg->intr_control |=
967*4882a593Smuzhiyun 		(tx_delay_interval << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT)
968*4882a593Smuzhiyun 		& ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK;
969*4882a593Smuzhiyun 
970*4882a593Smuzhiyun 	if (unmask)
971*4882a593Smuzhiyun 		intr_reg->intr_control |= ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK;
972*4882a593Smuzhiyun }
973*4882a593Smuzhiyun 
ena_com_get_next_bounce_buffer(struct ena_com_io_bounce_buffer_control * bounce_buf_ctrl)974*4882a593Smuzhiyun static inline u8 *ena_com_get_next_bounce_buffer(struct ena_com_io_bounce_buffer_control *bounce_buf_ctrl)
975*4882a593Smuzhiyun {
976*4882a593Smuzhiyun 	u16 size, buffers_num;
977*4882a593Smuzhiyun 	u8 *buf;
978*4882a593Smuzhiyun 
979*4882a593Smuzhiyun 	size = bounce_buf_ctrl->buffer_size;
980*4882a593Smuzhiyun 	buffers_num = bounce_buf_ctrl->buffers_num;
981*4882a593Smuzhiyun 
982*4882a593Smuzhiyun 	buf = bounce_buf_ctrl->base_buffer +
983*4882a593Smuzhiyun 		(bounce_buf_ctrl->next_to_use++ & (buffers_num - 1)) * size;
984*4882a593Smuzhiyun 
985*4882a593Smuzhiyun 	prefetchw(bounce_buf_ctrl->base_buffer +
986*4882a593Smuzhiyun 		(bounce_buf_ctrl->next_to_use & (buffers_num - 1)) * size);
987*4882a593Smuzhiyun 
988*4882a593Smuzhiyun 	return buf;
989*4882a593Smuzhiyun }
990*4882a593Smuzhiyun 
991*4882a593Smuzhiyun #endif /* !(ENA_COM) */
992