1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* Altera TSE SGDMA and MSGDMA Linux driver 3*4882a593Smuzhiyun * Copyright (C) 2014 Altera Corporation. All rights reserved 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __ALTERA_SGDMAHW_H__ 7*4882a593Smuzhiyun #define __ALTERA_SGDMAHW_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* SGDMA descriptor structure */ 10*4882a593Smuzhiyun struct sgdma_descrip { 11*4882a593Smuzhiyun u32 raddr; /* address of data to be read */ 12*4882a593Smuzhiyun u32 pad1; 13*4882a593Smuzhiyun u32 waddr; 14*4882a593Smuzhiyun u32 pad2; 15*4882a593Smuzhiyun u32 next; 16*4882a593Smuzhiyun u32 pad3; 17*4882a593Smuzhiyun u16 bytes; 18*4882a593Smuzhiyun u8 rburst; 19*4882a593Smuzhiyun u8 wburst; 20*4882a593Smuzhiyun u16 bytes_xferred; /* 16 bits, bytes xferred */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* bit 0: error 23*4882a593Smuzhiyun * bit 1: length error 24*4882a593Smuzhiyun * bit 2: crc error 25*4882a593Smuzhiyun * bit 3: truncated error 26*4882a593Smuzhiyun * bit 4: phy error 27*4882a593Smuzhiyun * bit 5: collision error 28*4882a593Smuzhiyun * bit 6: reserved 29*4882a593Smuzhiyun * bit 7: status eop for recv case 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun u8 status; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* bit 0: eop 34*4882a593Smuzhiyun * bit 1: read_fixed 35*4882a593Smuzhiyun * bit 2: write fixed 36*4882a593Smuzhiyun * bits 3,4,5,6: Channel (always 0) 37*4882a593Smuzhiyun * bit 7: hardware owned 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun u8 control; 40*4882a593Smuzhiyun } __packed; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define SGDMA_DESC_LEN sizeof(struct sgdma_descrip) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define SGDMA_STATUS_ERR BIT(0) 45*4882a593Smuzhiyun #define SGDMA_STATUS_LENGTH_ERR BIT(1) 46*4882a593Smuzhiyun #define SGDMA_STATUS_CRC_ERR BIT(2) 47*4882a593Smuzhiyun #define SGDMA_STATUS_TRUNC_ERR BIT(3) 48*4882a593Smuzhiyun #define SGDMA_STATUS_PHY_ERR BIT(4) 49*4882a593Smuzhiyun #define SGDMA_STATUS_COLL_ERR BIT(5) 50*4882a593Smuzhiyun #define SGDMA_STATUS_EOP BIT(7) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define SGDMA_CONTROL_EOP BIT(0) 53*4882a593Smuzhiyun #define SGDMA_CONTROL_RD_FIXED BIT(1) 54*4882a593Smuzhiyun #define SGDMA_CONTROL_WR_FIXED BIT(2) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* Channel is always 0, so just zero initialize it */ 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define SGDMA_CONTROL_HW_OWNED BIT(7) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* SGDMA register space */ 61*4882a593Smuzhiyun struct sgdma_csr { 62*4882a593Smuzhiyun /* bit 0: error 63*4882a593Smuzhiyun * bit 1: eop 64*4882a593Smuzhiyun * bit 2: descriptor completed 65*4882a593Smuzhiyun * bit 3: chain completed 66*4882a593Smuzhiyun * bit 4: busy 67*4882a593Smuzhiyun * remainder reserved 68*4882a593Smuzhiyun */ 69*4882a593Smuzhiyun u32 status; 70*4882a593Smuzhiyun u32 pad1[3]; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* bit 0: interrupt on error 73*4882a593Smuzhiyun * bit 1: interrupt on eop 74*4882a593Smuzhiyun * bit 2: interrupt after every descriptor 75*4882a593Smuzhiyun * bit 3: interrupt after last descrip in a chain 76*4882a593Smuzhiyun * bit 4: global interrupt enable 77*4882a593Smuzhiyun * bit 5: starts descriptor processing 78*4882a593Smuzhiyun * bit 6: stop core on dma error 79*4882a593Smuzhiyun * bit 7: interrupt on max descriptors 80*4882a593Smuzhiyun * bits 8-15: max descriptors to generate interrupt 81*4882a593Smuzhiyun * bit 16: Software reset 82*4882a593Smuzhiyun * bit 17: clears owned by hardware if 0, does not clear otherwise 83*4882a593Smuzhiyun * bit 18: enables descriptor polling mode 84*4882a593Smuzhiyun * bit 19-26: clocks before polling again 85*4882a593Smuzhiyun * bit 27-30: reserved 86*4882a593Smuzhiyun * bit 31: clear interrupt 87*4882a593Smuzhiyun */ 88*4882a593Smuzhiyun u32 control; 89*4882a593Smuzhiyun u32 pad2[3]; 90*4882a593Smuzhiyun u32 next_descrip; 91*4882a593Smuzhiyun u32 pad3[3]; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define sgdma_csroffs(a) (offsetof(struct sgdma_csr, a)) 95*4882a593Smuzhiyun #define sgdma_descroffs(a) (offsetof(struct sgdma_descrip, a)) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define SGDMA_STSREG_ERR BIT(0) /* Error */ 98*4882a593Smuzhiyun #define SGDMA_STSREG_EOP BIT(1) /* EOP */ 99*4882a593Smuzhiyun #define SGDMA_STSREG_DESCRIP BIT(2) /* Descriptor completed */ 100*4882a593Smuzhiyun #define SGDMA_STSREG_CHAIN BIT(3) /* Chain completed */ 101*4882a593Smuzhiyun #define SGDMA_STSREG_BUSY BIT(4) /* Controller busy */ 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define SGDMA_CTRLREG_IOE BIT(0) /* Interrupt on error */ 104*4882a593Smuzhiyun #define SGDMA_CTRLREG_IOEOP BIT(1) /* Interrupt on EOP */ 105*4882a593Smuzhiyun #define SGDMA_CTRLREG_IDESCRIP BIT(2) /* Interrupt after every descriptor */ 106*4882a593Smuzhiyun #define SGDMA_CTRLREG_ILASTD BIT(3) /* Interrupt after last descriptor */ 107*4882a593Smuzhiyun #define SGDMA_CTRLREG_INTEN BIT(4) /* Global Interrupt enable */ 108*4882a593Smuzhiyun #define SGDMA_CTRLREG_START BIT(5) /* starts descriptor processing */ 109*4882a593Smuzhiyun #define SGDMA_CTRLREG_STOPERR BIT(6) /* stop on dma error */ 110*4882a593Smuzhiyun #define SGDMA_CTRLREG_INTMAX BIT(7) /* Interrupt on max descriptors */ 111*4882a593Smuzhiyun #define SGDMA_CTRLREG_RESET BIT(16)/* Software reset */ 112*4882a593Smuzhiyun #define SGDMA_CTRLREG_COBHW BIT(17)/* Clears owned by hardware */ 113*4882a593Smuzhiyun #define SGDMA_CTRLREG_POLL BIT(18)/* enables descriptor polling mode */ 114*4882a593Smuzhiyun #define SGDMA_CTRLREG_CLRINT BIT(31)/* Clears interrupt */ 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #endif /* __ALTERA_SGDMAHW_H__ */ 117