1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Allwinner EMAC Fast Ethernet driver for Linux. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2012 Stefan Roese <sr@denx.de> 5*4882a593Smuzhiyun * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Based on the Linux driver provided by Allwinner: 8*4882a593Smuzhiyun * Copyright (C) 1997 Sten Wang 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public 11*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any 12*4882a593Smuzhiyun * warranty of any kind, whether express or implied. 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifndef _SUN4I_EMAC_H_ 16*4882a593Smuzhiyun #define _SUN4I_EMAC_H_ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define EMAC_CTL_REG (0x00) 19*4882a593Smuzhiyun #define EMAC_CTL_RESET (1 << 0) 20*4882a593Smuzhiyun #define EMAC_CTL_TX_EN (1 << 1) 21*4882a593Smuzhiyun #define EMAC_CTL_RX_EN (1 << 2) 22*4882a593Smuzhiyun #define EMAC_TX_MODE_REG (0x04) 23*4882a593Smuzhiyun #define EMAC_TX_MODE_ABORTED_FRAME_EN (1 << 0) 24*4882a593Smuzhiyun #define EMAC_TX_MODE_DMA_EN (1 << 1) 25*4882a593Smuzhiyun #define EMAC_TX_FLOW_REG (0x08) 26*4882a593Smuzhiyun #define EMAC_TX_CTL0_REG (0x0c) 27*4882a593Smuzhiyun #define EMAC_TX_CTL1_REG (0x10) 28*4882a593Smuzhiyun #define EMAC_TX_INS_REG (0x14) 29*4882a593Smuzhiyun #define EMAC_TX_PL0_REG (0x18) 30*4882a593Smuzhiyun #define EMAC_TX_PL1_REG (0x1c) 31*4882a593Smuzhiyun #define EMAC_TX_STA_REG (0x20) 32*4882a593Smuzhiyun #define EMAC_TX_IO_DATA_REG (0x24) 33*4882a593Smuzhiyun #define EMAC_TX_IO_DATA1_REG (0x28) 34*4882a593Smuzhiyun #define EMAC_TX_TSVL0_REG (0x2c) 35*4882a593Smuzhiyun #define EMAC_TX_TSVH0_REG (0x30) 36*4882a593Smuzhiyun #define EMAC_TX_TSVL1_REG (0x34) 37*4882a593Smuzhiyun #define EMAC_TX_TSVH1_REG (0x38) 38*4882a593Smuzhiyun #define EMAC_RX_CTL_REG (0x3c) 39*4882a593Smuzhiyun #define EMAC_RX_CTL_AUTO_DRQ_EN (1 << 1) 40*4882a593Smuzhiyun #define EMAC_RX_CTL_DMA_EN (1 << 2) 41*4882a593Smuzhiyun #define EMAC_RX_CTL_PASS_ALL_EN (1 << 4) 42*4882a593Smuzhiyun #define EMAC_RX_CTL_PASS_CTL_EN (1 << 5) 43*4882a593Smuzhiyun #define EMAC_RX_CTL_PASS_CRC_ERR_EN (1 << 6) 44*4882a593Smuzhiyun #define EMAC_RX_CTL_PASS_LEN_ERR_EN (1 << 7) 45*4882a593Smuzhiyun #define EMAC_RX_CTL_PASS_LEN_OOR_EN (1 << 8) 46*4882a593Smuzhiyun #define EMAC_RX_CTL_ACCEPT_UNICAST_EN (1 << 16) 47*4882a593Smuzhiyun #define EMAC_RX_CTL_DA_FILTER_EN (1 << 17) 48*4882a593Smuzhiyun #define EMAC_RX_CTL_ACCEPT_MULTICAST_EN (1 << 20) 49*4882a593Smuzhiyun #define EMAC_RX_CTL_HASH_FILTER_EN (1 << 21) 50*4882a593Smuzhiyun #define EMAC_RX_CTL_ACCEPT_BROADCAST_EN (1 << 22) 51*4882a593Smuzhiyun #define EMAC_RX_CTL_SA_FILTER_EN (1 << 24) 52*4882a593Smuzhiyun #define EMAC_RX_CTL_SA_FILTER_INVERT_EN (1 << 25) 53*4882a593Smuzhiyun #define EMAC_RX_HASH0_REG (0x40) 54*4882a593Smuzhiyun #define EMAC_RX_HASH1_REG (0x44) 55*4882a593Smuzhiyun #define EMAC_RX_STA_REG (0x48) 56*4882a593Smuzhiyun #define EMAC_RX_IO_DATA_REG (0x4c) 57*4882a593Smuzhiyun #define EMAC_RX_IO_DATA_LEN(x) (x & 0xffff) 58*4882a593Smuzhiyun #define EMAC_RX_IO_DATA_STATUS(x) ((x >> 16) & 0xffff) 59*4882a593Smuzhiyun #define EMAC_RX_IO_DATA_STATUS_CRC_ERR (1 << 4) 60*4882a593Smuzhiyun #define EMAC_RX_IO_DATA_STATUS_LEN_ERR (3 << 5) 61*4882a593Smuzhiyun #define EMAC_RX_IO_DATA_STATUS_OK (1 << 7) 62*4882a593Smuzhiyun #define EMAC_RX_FBC_REG (0x50) 63*4882a593Smuzhiyun #define EMAC_INT_CTL_REG (0x54) 64*4882a593Smuzhiyun #define EMAC_INT_STA_REG (0x58) 65*4882a593Smuzhiyun #define EMAC_MAC_CTL0_REG (0x5c) 66*4882a593Smuzhiyun #define EMAC_MAC_CTL0_RX_FLOW_CTL_EN (1 << 2) 67*4882a593Smuzhiyun #define EMAC_MAC_CTL0_TX_FLOW_CTL_EN (1 << 3) 68*4882a593Smuzhiyun #define EMAC_MAC_CTL0_SOFT_RESET (1 << 15) 69*4882a593Smuzhiyun #define EMAC_MAC_CTL1_REG (0x60) 70*4882a593Smuzhiyun #define EMAC_MAC_CTL1_DUPLEX_EN (1 << 0) 71*4882a593Smuzhiyun #define EMAC_MAC_CTL1_LEN_CHECK_EN (1 << 1) 72*4882a593Smuzhiyun #define EMAC_MAC_CTL1_HUGE_FRAME_EN (1 << 2) 73*4882a593Smuzhiyun #define EMAC_MAC_CTL1_DELAYED_CRC_EN (1 << 3) 74*4882a593Smuzhiyun #define EMAC_MAC_CTL1_CRC_EN (1 << 4) 75*4882a593Smuzhiyun #define EMAC_MAC_CTL1_PAD_EN (1 << 5) 76*4882a593Smuzhiyun #define EMAC_MAC_CTL1_PAD_CRC_EN (1 << 6) 77*4882a593Smuzhiyun #define EMAC_MAC_CTL1_AD_SHORT_FRAME_EN (1 << 7) 78*4882a593Smuzhiyun #define EMAC_MAC_CTL1_BACKOFF_DIS (1 << 12) 79*4882a593Smuzhiyun #define EMAC_MAC_IPGT_REG (0x64) 80*4882a593Smuzhiyun #define EMAC_MAC_IPGT_HALF_DUPLEX (0x12) 81*4882a593Smuzhiyun #define EMAC_MAC_IPGT_FULL_DUPLEX (0x15) 82*4882a593Smuzhiyun #define EMAC_MAC_IPGR_REG (0x68) 83*4882a593Smuzhiyun #define EMAC_MAC_IPGR_IPG1 (0x0c) 84*4882a593Smuzhiyun #define EMAC_MAC_IPGR_IPG2 (0x12) 85*4882a593Smuzhiyun #define EMAC_MAC_CLRT_REG (0x6c) 86*4882a593Smuzhiyun #define EMAC_MAC_CLRT_COLLISION_WINDOW (0x37) 87*4882a593Smuzhiyun #define EMAC_MAC_CLRT_RM (0x0f) 88*4882a593Smuzhiyun #define EMAC_MAC_MAXF_REG (0x70) 89*4882a593Smuzhiyun #define EMAC_MAC_SUPP_REG (0x74) 90*4882a593Smuzhiyun #define EMAC_MAC_TEST_REG (0x78) 91*4882a593Smuzhiyun #define EMAC_MAC_MCFG_REG (0x7c) 92*4882a593Smuzhiyun #define EMAC_MAC_A0_REG (0x98) 93*4882a593Smuzhiyun #define EMAC_MAC_A1_REG (0x9c) 94*4882a593Smuzhiyun #define EMAC_MAC_A2_REG (0xa0) 95*4882a593Smuzhiyun #define EMAC_SAFX_L_REG0 (0xa4) 96*4882a593Smuzhiyun #define EMAC_SAFX_H_REG0 (0xa8) 97*4882a593Smuzhiyun #define EMAC_SAFX_L_REG1 (0xac) 98*4882a593Smuzhiyun #define EMAC_SAFX_H_REG1 (0xb0) 99*4882a593Smuzhiyun #define EMAC_SAFX_L_REG2 (0xb4) 100*4882a593Smuzhiyun #define EMAC_SAFX_H_REG2 (0xb8) 101*4882a593Smuzhiyun #define EMAC_SAFX_L_REG3 (0xbc) 102*4882a593Smuzhiyun #define EMAC_SAFX_H_REG3 (0xc0) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define EMAC_PHY_DUPLEX (1 << 8) 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #define EMAC_EEPROM_MAGIC (0x444d394b) 107*4882a593Smuzhiyun #define EMAC_UNDOCUMENTED_MAGIC (0x0143414d) 108*4882a593Smuzhiyun #endif /* _SUN4I_EMAC_H_ */ 109