1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef GRETH_H 3*4882a593Smuzhiyun #define GRETH_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <linux/phy.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* Register bits and masks */ 8*4882a593Smuzhiyun #define GRETH_RESET 0x40 9*4882a593Smuzhiyun #define GRETH_MII_BUSY 0x8 10*4882a593Smuzhiyun #define GRETH_MII_NVALID 0x10 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define GRETH_CTRL_FD 0x10 13*4882a593Smuzhiyun #define GRETH_CTRL_PR 0x20 14*4882a593Smuzhiyun #define GRETH_CTRL_SP 0x80 15*4882a593Smuzhiyun #define GRETH_CTRL_GB 0x100 16*4882a593Smuzhiyun #define GRETH_CTRL_PSTATIEN 0x400 17*4882a593Smuzhiyun #define GRETH_CTRL_MCEN 0x800 18*4882a593Smuzhiyun #define GRETH_CTRL_DISDUPLEX 0x1000 19*4882a593Smuzhiyun #define GRETH_STATUS_PHYSTAT 0x100 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define GRETH_BD_EN 0x800 22*4882a593Smuzhiyun #define GRETH_BD_WR 0x1000 23*4882a593Smuzhiyun #define GRETH_BD_IE 0x2000 24*4882a593Smuzhiyun #define GRETH_BD_LEN 0x7FF 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define GRETH_TXEN 0x1 27*4882a593Smuzhiyun #define GRETH_INT_TE 0x2 28*4882a593Smuzhiyun #define GRETH_INT_TX 0x8 29*4882a593Smuzhiyun #define GRETH_TXI 0x4 30*4882a593Smuzhiyun #define GRETH_TXBD_STATUS 0x0001C000 31*4882a593Smuzhiyun #define GRETH_TXBD_MORE 0x20000 32*4882a593Smuzhiyun #define GRETH_TXBD_IPCS 0x40000 33*4882a593Smuzhiyun #define GRETH_TXBD_TCPCS 0x80000 34*4882a593Smuzhiyun #define GRETH_TXBD_UDPCS 0x100000 35*4882a593Smuzhiyun #define GRETH_TXBD_CSALL (GRETH_TXBD_IPCS | GRETH_TXBD_TCPCS | GRETH_TXBD_UDPCS) 36*4882a593Smuzhiyun #define GRETH_TXBD_ERR_LC 0x10000 37*4882a593Smuzhiyun #define GRETH_TXBD_ERR_UE 0x4000 38*4882a593Smuzhiyun #define GRETH_TXBD_ERR_AL 0x8000 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define GRETH_INT_RE 0x1 41*4882a593Smuzhiyun #define GRETH_INT_RX 0x4 42*4882a593Smuzhiyun #define GRETH_RXEN 0x2 43*4882a593Smuzhiyun #define GRETH_RXI 0x8 44*4882a593Smuzhiyun #define GRETH_RXBD_STATUS 0xFFFFC000 45*4882a593Smuzhiyun #define GRETH_RXBD_ERR_AE 0x4000 46*4882a593Smuzhiyun #define GRETH_RXBD_ERR_FT 0x8000 47*4882a593Smuzhiyun #define GRETH_RXBD_ERR_CRC 0x10000 48*4882a593Smuzhiyun #define GRETH_RXBD_ERR_OE 0x20000 49*4882a593Smuzhiyun #define GRETH_RXBD_ERR_LE 0x40000 50*4882a593Smuzhiyun #define GRETH_RXBD_IP 0x80000 51*4882a593Smuzhiyun #define GRETH_RXBD_IP_CSERR 0x100000 52*4882a593Smuzhiyun #define GRETH_RXBD_UDP 0x200000 53*4882a593Smuzhiyun #define GRETH_RXBD_UDP_CSERR 0x400000 54*4882a593Smuzhiyun #define GRETH_RXBD_TCP 0x800000 55*4882a593Smuzhiyun #define GRETH_RXBD_TCP_CSERR 0x1000000 56*4882a593Smuzhiyun #define GRETH_RXBD_IP_FRAG 0x2000000 57*4882a593Smuzhiyun #define GRETH_RXBD_MCAST 0x4000000 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* Descriptor parameters */ 60*4882a593Smuzhiyun #define GRETH_TXBD_NUM 128 61*4882a593Smuzhiyun #define GRETH_TXBD_NUM_MASK (GRETH_TXBD_NUM-1) 62*4882a593Smuzhiyun #define GRETH_TX_BUF_SIZE 2048 63*4882a593Smuzhiyun #define GRETH_RXBD_NUM 128 64*4882a593Smuzhiyun #define GRETH_RXBD_NUM_MASK (GRETH_RXBD_NUM-1) 65*4882a593Smuzhiyun #define GRETH_RX_BUF_SIZE 2048 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* Buffers per page */ 68*4882a593Smuzhiyun #define GRETH_RX_BUF_PPGAE (PAGE_SIZE/GRETH_RX_BUF_SIZE) 69*4882a593Smuzhiyun #define GRETH_TX_BUF_PPGAE (PAGE_SIZE/GRETH_TX_BUF_SIZE) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* How many pages are needed for buffers */ 72*4882a593Smuzhiyun #define GRETH_RX_BUF_PAGE_NUM (GRETH_RXBD_NUM/GRETH_RX_BUF_PPGAE) 73*4882a593Smuzhiyun #define GRETH_TX_BUF_PAGE_NUM (GRETH_TXBD_NUM/GRETH_TX_BUF_PPGAE) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* Buffer size. 76*4882a593Smuzhiyun * Gbit MAC uses tagged maximum frame size which is 1518 excluding CRC. 77*4882a593Smuzhiyun * Set to 1520 to make all buffers word aligned for non-gbit MAC. 78*4882a593Smuzhiyun */ 79*4882a593Smuzhiyun #define MAX_FRAME_SIZE 1520 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* GRETH APB registers */ 82*4882a593Smuzhiyun struct greth_regs { 83*4882a593Smuzhiyun u32 control; 84*4882a593Smuzhiyun u32 status; 85*4882a593Smuzhiyun u32 esa_msb; 86*4882a593Smuzhiyun u32 esa_lsb; 87*4882a593Smuzhiyun u32 mdio; 88*4882a593Smuzhiyun u32 tx_desc_p; 89*4882a593Smuzhiyun u32 rx_desc_p; 90*4882a593Smuzhiyun u32 edclip; 91*4882a593Smuzhiyun u32 hash_msb; 92*4882a593Smuzhiyun u32 hash_lsb; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* GRETH buffer descriptor */ 96*4882a593Smuzhiyun struct greth_bd { 97*4882a593Smuzhiyun u32 stat; 98*4882a593Smuzhiyun u32 addr; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun struct greth_private { 102*4882a593Smuzhiyun struct sk_buff *rx_skbuff[GRETH_RXBD_NUM]; 103*4882a593Smuzhiyun struct sk_buff *tx_skbuff[GRETH_TXBD_NUM]; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun unsigned char *tx_bufs[GRETH_TXBD_NUM]; 106*4882a593Smuzhiyun unsigned char *rx_bufs[GRETH_RXBD_NUM]; 107*4882a593Smuzhiyun u16 tx_bufs_length[GRETH_TXBD_NUM]; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun u16 tx_next; 110*4882a593Smuzhiyun u16 tx_last; 111*4882a593Smuzhiyun u16 tx_free; /* only used on 10/100Mbit */ 112*4882a593Smuzhiyun u16 rx_cur; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun struct greth_regs *regs; /* Address of controller registers. */ 115*4882a593Smuzhiyun struct greth_bd *rx_bd_base; /* Address of Rx BDs. */ 116*4882a593Smuzhiyun struct greth_bd *tx_bd_base; /* Address of Tx BDs. */ 117*4882a593Smuzhiyun dma_addr_t rx_bd_base_phys; 118*4882a593Smuzhiyun dma_addr_t tx_bd_base_phys; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun int irq; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun struct device *dev; /* Pointer to platform_device->dev */ 123*4882a593Smuzhiyun struct net_device *netdev; 124*4882a593Smuzhiyun struct napi_struct napi; 125*4882a593Smuzhiyun spinlock_t devlock; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun struct mii_bus *mdio; 128*4882a593Smuzhiyun unsigned int link; 129*4882a593Smuzhiyun unsigned int speed; 130*4882a593Smuzhiyun unsigned int duplex; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun u32 msg_enable; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun u8 phyaddr; 135*4882a593Smuzhiyun u8 multicast; 136*4882a593Smuzhiyun u8 gbit_mac; 137*4882a593Smuzhiyun u8 mdio_int_en; 138*4882a593Smuzhiyun u8 edcl; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #endif 142