1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Aeroflex Gaisler GRETH 10/100/1G Ethernet MAC.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * 2005-2010 (c) Aeroflex Gaisler AB
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * This driver supports GRETH 10/100 and GRETH 10/100/1G Ethernet MACs
8*4882a593Smuzhiyun * available in the GRLIB VHDL IP core library.
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Full documentation of both cores can be found here:
11*4882a593Smuzhiyun * https://www.gaisler.com/products/grlib/grip.pdf
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * The Gigabit version supports scatter/gather DMA, any alignment of
14*4882a593Smuzhiyun * buffers and checksum offloading.
15*4882a593Smuzhiyun *
16*4882a593Smuzhiyun * Contributors: Kristoffer Glembo
17*4882a593Smuzhiyun * Daniel Hellstrom
18*4882a593Smuzhiyun * Marko Isomaki
19*4882a593Smuzhiyun */
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include <linux/dma-mapping.h>
22*4882a593Smuzhiyun #include <linux/module.h>
23*4882a593Smuzhiyun #include <linux/uaccess.h>
24*4882a593Smuzhiyun #include <linux/interrupt.h>
25*4882a593Smuzhiyun #include <linux/netdevice.h>
26*4882a593Smuzhiyun #include <linux/etherdevice.h>
27*4882a593Smuzhiyun #include <linux/ethtool.h>
28*4882a593Smuzhiyun #include <linux/skbuff.h>
29*4882a593Smuzhiyun #include <linux/io.h>
30*4882a593Smuzhiyun #include <linux/crc32.h>
31*4882a593Smuzhiyun #include <linux/mii.h>
32*4882a593Smuzhiyun #include <linux/of_device.h>
33*4882a593Smuzhiyun #include <linux/of_net.h>
34*4882a593Smuzhiyun #include <linux/of_platform.h>
35*4882a593Smuzhiyun #include <linux/slab.h>
36*4882a593Smuzhiyun #include <asm/cacheflush.h>
37*4882a593Smuzhiyun #include <asm/byteorder.h>
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #ifdef CONFIG_SPARC
40*4882a593Smuzhiyun #include <asm/idprom.h>
41*4882a593Smuzhiyun #endif
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #include "greth.h"
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #define GRETH_DEF_MSG_ENABLE \
46*4882a593Smuzhiyun (NETIF_MSG_DRV | \
47*4882a593Smuzhiyun NETIF_MSG_PROBE | \
48*4882a593Smuzhiyun NETIF_MSG_LINK | \
49*4882a593Smuzhiyun NETIF_MSG_IFDOWN | \
50*4882a593Smuzhiyun NETIF_MSG_IFUP | \
51*4882a593Smuzhiyun NETIF_MSG_RX_ERR | \
52*4882a593Smuzhiyun NETIF_MSG_TX_ERR)
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun static int greth_debug = -1; /* -1 == use GRETH_DEF_MSG_ENABLE as value */
55*4882a593Smuzhiyun module_param(greth_debug, int, 0);
56*4882a593Smuzhiyun MODULE_PARM_DESC(greth_debug, "GRETH bitmapped debugging message enable value");
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* Accept MAC address of the form macaddr=0x08,0x00,0x20,0x30,0x40,0x50 */
59*4882a593Smuzhiyun static int macaddr[6];
60*4882a593Smuzhiyun module_param_array(macaddr, int, NULL, 0);
61*4882a593Smuzhiyun MODULE_PARM_DESC(macaddr, "GRETH Ethernet MAC address");
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun static int greth_edcl = 1;
64*4882a593Smuzhiyun module_param(greth_edcl, int, 0);
65*4882a593Smuzhiyun MODULE_PARM_DESC(greth_edcl, "GRETH EDCL usage indicator. Set to 1 if EDCL is used.");
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun static int greth_open(struct net_device *dev);
68*4882a593Smuzhiyun static netdev_tx_t greth_start_xmit(struct sk_buff *skb,
69*4882a593Smuzhiyun struct net_device *dev);
70*4882a593Smuzhiyun static netdev_tx_t greth_start_xmit_gbit(struct sk_buff *skb,
71*4882a593Smuzhiyun struct net_device *dev);
72*4882a593Smuzhiyun static int greth_rx(struct net_device *dev, int limit);
73*4882a593Smuzhiyun static int greth_rx_gbit(struct net_device *dev, int limit);
74*4882a593Smuzhiyun static void greth_clean_tx(struct net_device *dev);
75*4882a593Smuzhiyun static void greth_clean_tx_gbit(struct net_device *dev);
76*4882a593Smuzhiyun static irqreturn_t greth_interrupt(int irq, void *dev_id);
77*4882a593Smuzhiyun static int greth_close(struct net_device *dev);
78*4882a593Smuzhiyun static int greth_set_mac_add(struct net_device *dev, void *p);
79*4882a593Smuzhiyun static void greth_set_multicast_list(struct net_device *dev);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun #define GRETH_REGLOAD(a) (be32_to_cpu(__raw_readl(&(a))))
82*4882a593Smuzhiyun #define GRETH_REGSAVE(a, v) (__raw_writel(cpu_to_be32(v), &(a)))
83*4882a593Smuzhiyun #define GRETH_REGORIN(a, v) (GRETH_REGSAVE(a, (GRETH_REGLOAD(a) | (v))))
84*4882a593Smuzhiyun #define GRETH_REGANDIN(a, v) (GRETH_REGSAVE(a, (GRETH_REGLOAD(a) & (v))))
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun #define NEXT_TX(N) (((N) + 1) & GRETH_TXBD_NUM_MASK)
87*4882a593Smuzhiyun #define SKIP_TX(N, C) (((N) + C) & GRETH_TXBD_NUM_MASK)
88*4882a593Smuzhiyun #define NEXT_RX(N) (((N) + 1) & GRETH_RXBD_NUM_MASK)
89*4882a593Smuzhiyun
greth_print_rx_packet(void * addr,int len)90*4882a593Smuzhiyun static void greth_print_rx_packet(void *addr, int len)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun print_hex_dump(KERN_DEBUG, "RX: ", DUMP_PREFIX_OFFSET, 16, 1,
93*4882a593Smuzhiyun addr, len, true);
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
greth_print_tx_packet(struct sk_buff * skb)96*4882a593Smuzhiyun static void greth_print_tx_packet(struct sk_buff *skb)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun int i;
99*4882a593Smuzhiyun int length;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun if (skb_shinfo(skb)->nr_frags == 0)
102*4882a593Smuzhiyun length = skb->len;
103*4882a593Smuzhiyun else
104*4882a593Smuzhiyun length = skb_headlen(skb);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun print_hex_dump(KERN_DEBUG, "TX: ", DUMP_PREFIX_OFFSET, 16, 1,
107*4882a593Smuzhiyun skb->data, length, true);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun print_hex_dump(KERN_DEBUG, "TX: ", DUMP_PREFIX_OFFSET, 16, 1,
112*4882a593Smuzhiyun skb_frag_address(&skb_shinfo(skb)->frags[i]),
113*4882a593Smuzhiyun skb_frag_size(&skb_shinfo(skb)->frags[i]), true);
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
greth_enable_tx(struct greth_private * greth)117*4882a593Smuzhiyun static inline void greth_enable_tx(struct greth_private *greth)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun wmb();
120*4882a593Smuzhiyun GRETH_REGORIN(greth->regs->control, GRETH_TXEN);
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
greth_enable_tx_and_irq(struct greth_private * greth)123*4882a593Smuzhiyun static inline void greth_enable_tx_and_irq(struct greth_private *greth)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun wmb(); /* BDs must been written to memory before enabling TX */
126*4882a593Smuzhiyun GRETH_REGORIN(greth->regs->control, GRETH_TXEN | GRETH_TXI);
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
greth_disable_tx(struct greth_private * greth)129*4882a593Smuzhiyun static inline void greth_disable_tx(struct greth_private *greth)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun GRETH_REGANDIN(greth->regs->control, ~GRETH_TXEN);
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
greth_enable_rx(struct greth_private * greth)134*4882a593Smuzhiyun static inline void greth_enable_rx(struct greth_private *greth)
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun wmb();
137*4882a593Smuzhiyun GRETH_REGORIN(greth->regs->control, GRETH_RXEN);
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
greth_disable_rx(struct greth_private * greth)140*4882a593Smuzhiyun static inline void greth_disable_rx(struct greth_private *greth)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun GRETH_REGANDIN(greth->regs->control, ~GRETH_RXEN);
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
greth_enable_irqs(struct greth_private * greth)145*4882a593Smuzhiyun static inline void greth_enable_irqs(struct greth_private *greth)
146*4882a593Smuzhiyun {
147*4882a593Smuzhiyun GRETH_REGORIN(greth->regs->control, GRETH_RXI | GRETH_TXI);
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
greth_disable_irqs(struct greth_private * greth)150*4882a593Smuzhiyun static inline void greth_disable_irqs(struct greth_private *greth)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun GRETH_REGANDIN(greth->regs->control, ~(GRETH_RXI|GRETH_TXI));
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun
greth_write_bd(u32 * bd,u32 val)155*4882a593Smuzhiyun static inline void greth_write_bd(u32 *bd, u32 val)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun __raw_writel(cpu_to_be32(val), bd);
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun
greth_read_bd(u32 * bd)160*4882a593Smuzhiyun static inline u32 greth_read_bd(u32 *bd)
161*4882a593Smuzhiyun {
162*4882a593Smuzhiyun return be32_to_cpu(__raw_readl(bd));
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun
greth_clean_rings(struct greth_private * greth)165*4882a593Smuzhiyun static void greth_clean_rings(struct greth_private *greth)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun int i;
168*4882a593Smuzhiyun struct greth_bd *rx_bdp = greth->rx_bd_base;
169*4882a593Smuzhiyun struct greth_bd *tx_bdp = greth->tx_bd_base;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun if (greth->gbit_mac) {
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun /* Free and unmap RX buffers */
174*4882a593Smuzhiyun for (i = 0; i < GRETH_RXBD_NUM; i++, rx_bdp++) {
175*4882a593Smuzhiyun if (greth->rx_skbuff[i] != NULL) {
176*4882a593Smuzhiyun dev_kfree_skb(greth->rx_skbuff[i]);
177*4882a593Smuzhiyun dma_unmap_single(greth->dev,
178*4882a593Smuzhiyun greth_read_bd(&rx_bdp->addr),
179*4882a593Smuzhiyun MAX_FRAME_SIZE+NET_IP_ALIGN,
180*4882a593Smuzhiyun DMA_FROM_DEVICE);
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun /* TX buffers */
185*4882a593Smuzhiyun while (greth->tx_free < GRETH_TXBD_NUM) {
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun struct sk_buff *skb = greth->tx_skbuff[greth->tx_last];
188*4882a593Smuzhiyun int nr_frags = skb_shinfo(skb)->nr_frags;
189*4882a593Smuzhiyun tx_bdp = greth->tx_bd_base + greth->tx_last;
190*4882a593Smuzhiyun greth->tx_last = NEXT_TX(greth->tx_last);
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun dma_unmap_single(greth->dev,
193*4882a593Smuzhiyun greth_read_bd(&tx_bdp->addr),
194*4882a593Smuzhiyun skb_headlen(skb),
195*4882a593Smuzhiyun DMA_TO_DEVICE);
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun for (i = 0; i < nr_frags; i++) {
198*4882a593Smuzhiyun skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
199*4882a593Smuzhiyun tx_bdp = greth->tx_bd_base + greth->tx_last;
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun dma_unmap_page(greth->dev,
202*4882a593Smuzhiyun greth_read_bd(&tx_bdp->addr),
203*4882a593Smuzhiyun skb_frag_size(frag),
204*4882a593Smuzhiyun DMA_TO_DEVICE);
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun greth->tx_last = NEXT_TX(greth->tx_last);
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun greth->tx_free += nr_frags+1;
209*4882a593Smuzhiyun dev_kfree_skb(skb);
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun } else { /* 10/100 Mbps MAC */
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun for (i = 0; i < GRETH_RXBD_NUM; i++, rx_bdp++) {
216*4882a593Smuzhiyun kfree(greth->rx_bufs[i]);
217*4882a593Smuzhiyun dma_unmap_single(greth->dev,
218*4882a593Smuzhiyun greth_read_bd(&rx_bdp->addr),
219*4882a593Smuzhiyun MAX_FRAME_SIZE,
220*4882a593Smuzhiyun DMA_FROM_DEVICE);
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun for (i = 0; i < GRETH_TXBD_NUM; i++, tx_bdp++) {
223*4882a593Smuzhiyun kfree(greth->tx_bufs[i]);
224*4882a593Smuzhiyun dma_unmap_single(greth->dev,
225*4882a593Smuzhiyun greth_read_bd(&tx_bdp->addr),
226*4882a593Smuzhiyun MAX_FRAME_SIZE,
227*4882a593Smuzhiyun DMA_TO_DEVICE);
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun
greth_init_rings(struct greth_private * greth)232*4882a593Smuzhiyun static int greth_init_rings(struct greth_private *greth)
233*4882a593Smuzhiyun {
234*4882a593Smuzhiyun struct sk_buff *skb;
235*4882a593Smuzhiyun struct greth_bd *rx_bd, *tx_bd;
236*4882a593Smuzhiyun u32 dma_addr;
237*4882a593Smuzhiyun int i;
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun rx_bd = greth->rx_bd_base;
240*4882a593Smuzhiyun tx_bd = greth->tx_bd_base;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun /* Initialize descriptor rings and buffers */
243*4882a593Smuzhiyun if (greth->gbit_mac) {
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun for (i = 0; i < GRETH_RXBD_NUM; i++) {
246*4882a593Smuzhiyun skb = netdev_alloc_skb(greth->netdev, MAX_FRAME_SIZE+NET_IP_ALIGN);
247*4882a593Smuzhiyun if (skb == NULL) {
248*4882a593Smuzhiyun if (netif_msg_ifup(greth))
249*4882a593Smuzhiyun dev_err(greth->dev, "Error allocating DMA ring.\n");
250*4882a593Smuzhiyun goto cleanup;
251*4882a593Smuzhiyun }
252*4882a593Smuzhiyun skb_reserve(skb, NET_IP_ALIGN);
253*4882a593Smuzhiyun dma_addr = dma_map_single(greth->dev,
254*4882a593Smuzhiyun skb->data,
255*4882a593Smuzhiyun MAX_FRAME_SIZE+NET_IP_ALIGN,
256*4882a593Smuzhiyun DMA_FROM_DEVICE);
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun if (dma_mapping_error(greth->dev, dma_addr)) {
259*4882a593Smuzhiyun if (netif_msg_ifup(greth))
260*4882a593Smuzhiyun dev_err(greth->dev, "Could not create initial DMA mapping\n");
261*4882a593Smuzhiyun dev_kfree_skb(skb);
262*4882a593Smuzhiyun goto cleanup;
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun greth->rx_skbuff[i] = skb;
265*4882a593Smuzhiyun greth_write_bd(&rx_bd[i].addr, dma_addr);
266*4882a593Smuzhiyun greth_write_bd(&rx_bd[i].stat, GRETH_BD_EN | GRETH_BD_IE);
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun } else {
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun /* 10/100 MAC uses a fixed set of buffers and copy to/from SKBs */
272*4882a593Smuzhiyun for (i = 0; i < GRETH_RXBD_NUM; i++) {
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun greth->rx_bufs[i] = kmalloc(MAX_FRAME_SIZE, GFP_KERNEL);
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun if (greth->rx_bufs[i] == NULL) {
277*4882a593Smuzhiyun if (netif_msg_ifup(greth))
278*4882a593Smuzhiyun dev_err(greth->dev, "Error allocating DMA ring.\n");
279*4882a593Smuzhiyun goto cleanup;
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun dma_addr = dma_map_single(greth->dev,
283*4882a593Smuzhiyun greth->rx_bufs[i],
284*4882a593Smuzhiyun MAX_FRAME_SIZE,
285*4882a593Smuzhiyun DMA_FROM_DEVICE);
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun if (dma_mapping_error(greth->dev, dma_addr)) {
288*4882a593Smuzhiyun if (netif_msg_ifup(greth))
289*4882a593Smuzhiyun dev_err(greth->dev, "Could not create initial DMA mapping\n");
290*4882a593Smuzhiyun goto cleanup;
291*4882a593Smuzhiyun }
292*4882a593Smuzhiyun greth_write_bd(&rx_bd[i].addr, dma_addr);
293*4882a593Smuzhiyun greth_write_bd(&rx_bd[i].stat, GRETH_BD_EN | GRETH_BD_IE);
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun for (i = 0; i < GRETH_TXBD_NUM; i++) {
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun greth->tx_bufs[i] = kmalloc(MAX_FRAME_SIZE, GFP_KERNEL);
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun if (greth->tx_bufs[i] == NULL) {
300*4882a593Smuzhiyun if (netif_msg_ifup(greth))
301*4882a593Smuzhiyun dev_err(greth->dev, "Error allocating DMA ring.\n");
302*4882a593Smuzhiyun goto cleanup;
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun dma_addr = dma_map_single(greth->dev,
306*4882a593Smuzhiyun greth->tx_bufs[i],
307*4882a593Smuzhiyun MAX_FRAME_SIZE,
308*4882a593Smuzhiyun DMA_TO_DEVICE);
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun if (dma_mapping_error(greth->dev, dma_addr)) {
311*4882a593Smuzhiyun if (netif_msg_ifup(greth))
312*4882a593Smuzhiyun dev_err(greth->dev, "Could not create initial DMA mapping\n");
313*4882a593Smuzhiyun goto cleanup;
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun greth_write_bd(&tx_bd[i].addr, dma_addr);
316*4882a593Smuzhiyun greth_write_bd(&tx_bd[i].stat, 0);
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun greth_write_bd(&rx_bd[GRETH_RXBD_NUM - 1].stat,
320*4882a593Smuzhiyun greth_read_bd(&rx_bd[GRETH_RXBD_NUM - 1].stat) | GRETH_BD_WR);
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun /* Initialize pointers. */
323*4882a593Smuzhiyun greth->rx_cur = 0;
324*4882a593Smuzhiyun greth->tx_next = 0;
325*4882a593Smuzhiyun greth->tx_last = 0;
326*4882a593Smuzhiyun greth->tx_free = GRETH_TXBD_NUM;
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun /* Initialize descriptor base address */
329*4882a593Smuzhiyun GRETH_REGSAVE(greth->regs->tx_desc_p, greth->tx_bd_base_phys);
330*4882a593Smuzhiyun GRETH_REGSAVE(greth->regs->rx_desc_p, greth->rx_bd_base_phys);
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun return 0;
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun cleanup:
335*4882a593Smuzhiyun greth_clean_rings(greth);
336*4882a593Smuzhiyun return -ENOMEM;
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun
greth_open(struct net_device * dev)339*4882a593Smuzhiyun static int greth_open(struct net_device *dev)
340*4882a593Smuzhiyun {
341*4882a593Smuzhiyun struct greth_private *greth = netdev_priv(dev);
342*4882a593Smuzhiyun int err;
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun err = greth_init_rings(greth);
345*4882a593Smuzhiyun if (err) {
346*4882a593Smuzhiyun if (netif_msg_ifup(greth))
347*4882a593Smuzhiyun dev_err(&dev->dev, "Could not allocate memory for DMA rings\n");
348*4882a593Smuzhiyun return err;
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun err = request_irq(greth->irq, greth_interrupt, 0, "eth", (void *) dev);
352*4882a593Smuzhiyun if (err) {
353*4882a593Smuzhiyun if (netif_msg_ifup(greth))
354*4882a593Smuzhiyun dev_err(&dev->dev, "Could not allocate interrupt %d\n", dev->irq);
355*4882a593Smuzhiyun greth_clean_rings(greth);
356*4882a593Smuzhiyun return err;
357*4882a593Smuzhiyun }
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun if (netif_msg_ifup(greth))
360*4882a593Smuzhiyun dev_dbg(&dev->dev, " starting queue\n");
361*4882a593Smuzhiyun netif_start_queue(dev);
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun GRETH_REGSAVE(greth->regs->status, 0xFF);
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun napi_enable(&greth->napi);
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun greth_enable_irqs(greth);
368*4882a593Smuzhiyun greth_enable_tx(greth);
369*4882a593Smuzhiyun greth_enable_rx(greth);
370*4882a593Smuzhiyun return 0;
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun }
373*4882a593Smuzhiyun
greth_close(struct net_device * dev)374*4882a593Smuzhiyun static int greth_close(struct net_device *dev)
375*4882a593Smuzhiyun {
376*4882a593Smuzhiyun struct greth_private *greth = netdev_priv(dev);
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun napi_disable(&greth->napi);
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun greth_disable_irqs(greth);
381*4882a593Smuzhiyun greth_disable_tx(greth);
382*4882a593Smuzhiyun greth_disable_rx(greth);
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun netif_stop_queue(dev);
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun free_irq(greth->irq, (void *) dev);
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun greth_clean_rings(greth);
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun return 0;
391*4882a593Smuzhiyun }
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun static netdev_tx_t
greth_start_xmit(struct sk_buff * skb,struct net_device * dev)394*4882a593Smuzhiyun greth_start_xmit(struct sk_buff *skb, struct net_device *dev)
395*4882a593Smuzhiyun {
396*4882a593Smuzhiyun struct greth_private *greth = netdev_priv(dev);
397*4882a593Smuzhiyun struct greth_bd *bdp;
398*4882a593Smuzhiyun int err = NETDEV_TX_OK;
399*4882a593Smuzhiyun u32 status, dma_addr, ctrl;
400*4882a593Smuzhiyun unsigned long flags;
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun /* Clean TX Ring */
403*4882a593Smuzhiyun greth_clean_tx(greth->netdev);
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun if (unlikely(greth->tx_free <= 0)) {
406*4882a593Smuzhiyun spin_lock_irqsave(&greth->devlock, flags);/*save from poll/irq*/
407*4882a593Smuzhiyun ctrl = GRETH_REGLOAD(greth->regs->control);
408*4882a593Smuzhiyun /* Enable TX IRQ only if not already in poll() routine */
409*4882a593Smuzhiyun if (ctrl & GRETH_RXI)
410*4882a593Smuzhiyun GRETH_REGSAVE(greth->regs->control, ctrl | GRETH_TXI);
411*4882a593Smuzhiyun netif_stop_queue(dev);
412*4882a593Smuzhiyun spin_unlock_irqrestore(&greth->devlock, flags);
413*4882a593Smuzhiyun return NETDEV_TX_BUSY;
414*4882a593Smuzhiyun }
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun if (netif_msg_pktdata(greth))
417*4882a593Smuzhiyun greth_print_tx_packet(skb);
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun if (unlikely(skb->len > MAX_FRAME_SIZE)) {
421*4882a593Smuzhiyun dev->stats.tx_errors++;
422*4882a593Smuzhiyun goto out;
423*4882a593Smuzhiyun }
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun bdp = greth->tx_bd_base + greth->tx_next;
426*4882a593Smuzhiyun dma_addr = greth_read_bd(&bdp->addr);
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun memcpy((unsigned char *) phys_to_virt(dma_addr), skb->data, skb->len);
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun dma_sync_single_for_device(greth->dev, dma_addr, skb->len, DMA_TO_DEVICE);
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun status = GRETH_BD_EN | GRETH_BD_IE | (skb->len & GRETH_BD_LEN);
433*4882a593Smuzhiyun greth->tx_bufs_length[greth->tx_next] = skb->len & GRETH_BD_LEN;
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun /* Wrap around descriptor ring */
436*4882a593Smuzhiyun if (greth->tx_next == GRETH_TXBD_NUM_MASK) {
437*4882a593Smuzhiyun status |= GRETH_BD_WR;
438*4882a593Smuzhiyun }
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun greth->tx_next = NEXT_TX(greth->tx_next);
441*4882a593Smuzhiyun greth->tx_free--;
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun /* Write descriptor control word and enable transmission */
444*4882a593Smuzhiyun greth_write_bd(&bdp->stat, status);
445*4882a593Smuzhiyun spin_lock_irqsave(&greth->devlock, flags); /*save from poll/irq*/
446*4882a593Smuzhiyun greth_enable_tx(greth);
447*4882a593Smuzhiyun spin_unlock_irqrestore(&greth->devlock, flags);
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun out:
450*4882a593Smuzhiyun dev_kfree_skb(skb);
451*4882a593Smuzhiyun return err;
452*4882a593Smuzhiyun }
453*4882a593Smuzhiyun
greth_num_free_bds(u16 tx_last,u16 tx_next)454*4882a593Smuzhiyun static inline u16 greth_num_free_bds(u16 tx_last, u16 tx_next)
455*4882a593Smuzhiyun {
456*4882a593Smuzhiyun if (tx_next < tx_last)
457*4882a593Smuzhiyun return (tx_last - tx_next) - 1;
458*4882a593Smuzhiyun else
459*4882a593Smuzhiyun return GRETH_TXBD_NUM - (tx_next - tx_last) - 1;
460*4882a593Smuzhiyun }
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun static netdev_tx_t
greth_start_xmit_gbit(struct sk_buff * skb,struct net_device * dev)463*4882a593Smuzhiyun greth_start_xmit_gbit(struct sk_buff *skb, struct net_device *dev)
464*4882a593Smuzhiyun {
465*4882a593Smuzhiyun struct greth_private *greth = netdev_priv(dev);
466*4882a593Smuzhiyun struct greth_bd *bdp;
467*4882a593Smuzhiyun u32 status, dma_addr;
468*4882a593Smuzhiyun int curr_tx, nr_frags, i, err = NETDEV_TX_OK;
469*4882a593Smuzhiyun unsigned long flags;
470*4882a593Smuzhiyun u16 tx_last;
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun nr_frags = skb_shinfo(skb)->nr_frags;
473*4882a593Smuzhiyun tx_last = greth->tx_last;
474*4882a593Smuzhiyun rmb(); /* tx_last is updated by the poll task */
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun if (greth_num_free_bds(tx_last, greth->tx_next) < nr_frags + 1) {
477*4882a593Smuzhiyun netif_stop_queue(dev);
478*4882a593Smuzhiyun err = NETDEV_TX_BUSY;
479*4882a593Smuzhiyun goto out;
480*4882a593Smuzhiyun }
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun if (netif_msg_pktdata(greth))
483*4882a593Smuzhiyun greth_print_tx_packet(skb);
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun if (unlikely(skb->len > MAX_FRAME_SIZE)) {
486*4882a593Smuzhiyun dev->stats.tx_errors++;
487*4882a593Smuzhiyun goto out;
488*4882a593Smuzhiyun }
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun /* Save skb pointer. */
491*4882a593Smuzhiyun greth->tx_skbuff[greth->tx_next] = skb;
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun /* Linear buf */
494*4882a593Smuzhiyun if (nr_frags != 0)
495*4882a593Smuzhiyun status = GRETH_TXBD_MORE;
496*4882a593Smuzhiyun else
497*4882a593Smuzhiyun status = GRETH_BD_IE;
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun if (skb->ip_summed == CHECKSUM_PARTIAL)
500*4882a593Smuzhiyun status |= GRETH_TXBD_CSALL;
501*4882a593Smuzhiyun status |= skb_headlen(skb) & GRETH_BD_LEN;
502*4882a593Smuzhiyun if (greth->tx_next == GRETH_TXBD_NUM_MASK)
503*4882a593Smuzhiyun status |= GRETH_BD_WR;
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun bdp = greth->tx_bd_base + greth->tx_next;
507*4882a593Smuzhiyun greth_write_bd(&bdp->stat, status);
508*4882a593Smuzhiyun dma_addr = dma_map_single(greth->dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
509*4882a593Smuzhiyun
510*4882a593Smuzhiyun if (unlikely(dma_mapping_error(greth->dev, dma_addr)))
511*4882a593Smuzhiyun goto map_error;
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun greth_write_bd(&bdp->addr, dma_addr);
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun curr_tx = NEXT_TX(greth->tx_next);
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun /* Frags */
518*4882a593Smuzhiyun for (i = 0; i < nr_frags; i++) {
519*4882a593Smuzhiyun skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
520*4882a593Smuzhiyun greth->tx_skbuff[curr_tx] = NULL;
521*4882a593Smuzhiyun bdp = greth->tx_bd_base + curr_tx;
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun status = GRETH_BD_EN;
524*4882a593Smuzhiyun if (skb->ip_summed == CHECKSUM_PARTIAL)
525*4882a593Smuzhiyun status |= GRETH_TXBD_CSALL;
526*4882a593Smuzhiyun status |= skb_frag_size(frag) & GRETH_BD_LEN;
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun /* Wrap around descriptor ring */
529*4882a593Smuzhiyun if (curr_tx == GRETH_TXBD_NUM_MASK)
530*4882a593Smuzhiyun status |= GRETH_BD_WR;
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun /* More fragments left */
533*4882a593Smuzhiyun if (i < nr_frags - 1)
534*4882a593Smuzhiyun status |= GRETH_TXBD_MORE;
535*4882a593Smuzhiyun else
536*4882a593Smuzhiyun status |= GRETH_BD_IE; /* enable IRQ on last fragment */
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun greth_write_bd(&bdp->stat, status);
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun dma_addr = skb_frag_dma_map(greth->dev, frag, 0, skb_frag_size(frag),
541*4882a593Smuzhiyun DMA_TO_DEVICE);
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun if (unlikely(dma_mapping_error(greth->dev, dma_addr)))
544*4882a593Smuzhiyun goto frag_map_error;
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun greth_write_bd(&bdp->addr, dma_addr);
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun curr_tx = NEXT_TX(curr_tx);
549*4882a593Smuzhiyun }
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun wmb();
552*4882a593Smuzhiyun
553*4882a593Smuzhiyun /* Enable the descriptor chain by enabling the first descriptor */
554*4882a593Smuzhiyun bdp = greth->tx_bd_base + greth->tx_next;
555*4882a593Smuzhiyun greth_write_bd(&bdp->stat,
556*4882a593Smuzhiyun greth_read_bd(&bdp->stat) | GRETH_BD_EN);
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun spin_lock_irqsave(&greth->devlock, flags); /*save from poll/irq*/
559*4882a593Smuzhiyun greth->tx_next = curr_tx;
560*4882a593Smuzhiyun greth_enable_tx_and_irq(greth);
561*4882a593Smuzhiyun spin_unlock_irqrestore(&greth->devlock, flags);
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun return NETDEV_TX_OK;
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun frag_map_error:
566*4882a593Smuzhiyun /* Unmap SKB mappings that succeeded and disable descriptor */
567*4882a593Smuzhiyun for (i = 0; greth->tx_next + i != curr_tx; i++) {
568*4882a593Smuzhiyun bdp = greth->tx_bd_base + greth->tx_next + i;
569*4882a593Smuzhiyun dma_unmap_single(greth->dev,
570*4882a593Smuzhiyun greth_read_bd(&bdp->addr),
571*4882a593Smuzhiyun greth_read_bd(&bdp->stat) & GRETH_BD_LEN,
572*4882a593Smuzhiyun DMA_TO_DEVICE);
573*4882a593Smuzhiyun greth_write_bd(&bdp->stat, 0);
574*4882a593Smuzhiyun }
575*4882a593Smuzhiyun map_error:
576*4882a593Smuzhiyun if (net_ratelimit())
577*4882a593Smuzhiyun dev_warn(greth->dev, "Could not create TX DMA mapping\n");
578*4882a593Smuzhiyun dev_kfree_skb(skb);
579*4882a593Smuzhiyun out:
580*4882a593Smuzhiyun return err;
581*4882a593Smuzhiyun }
582*4882a593Smuzhiyun
greth_interrupt(int irq,void * dev_id)583*4882a593Smuzhiyun static irqreturn_t greth_interrupt(int irq, void *dev_id)
584*4882a593Smuzhiyun {
585*4882a593Smuzhiyun struct net_device *dev = dev_id;
586*4882a593Smuzhiyun struct greth_private *greth;
587*4882a593Smuzhiyun u32 status, ctrl;
588*4882a593Smuzhiyun irqreturn_t retval = IRQ_NONE;
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun greth = netdev_priv(dev);
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun spin_lock(&greth->devlock);
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun /* Get the interrupt events that caused us to be here. */
595*4882a593Smuzhiyun status = GRETH_REGLOAD(greth->regs->status);
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun /* Must see if interrupts are enabled also, INT_TX|INT_RX flags may be
598*4882a593Smuzhiyun * set regardless of whether IRQ is enabled or not. Especially
599*4882a593Smuzhiyun * important when shared IRQ.
600*4882a593Smuzhiyun */
601*4882a593Smuzhiyun ctrl = GRETH_REGLOAD(greth->regs->control);
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun /* Handle rx and tx interrupts through poll */
604*4882a593Smuzhiyun if (((status & (GRETH_INT_RE | GRETH_INT_RX)) && (ctrl & GRETH_RXI)) ||
605*4882a593Smuzhiyun ((status & (GRETH_INT_TE | GRETH_INT_TX)) && (ctrl & GRETH_TXI))) {
606*4882a593Smuzhiyun retval = IRQ_HANDLED;
607*4882a593Smuzhiyun
608*4882a593Smuzhiyun /* Disable interrupts and schedule poll() */
609*4882a593Smuzhiyun greth_disable_irqs(greth);
610*4882a593Smuzhiyun napi_schedule(&greth->napi);
611*4882a593Smuzhiyun }
612*4882a593Smuzhiyun
613*4882a593Smuzhiyun spin_unlock(&greth->devlock);
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun return retval;
616*4882a593Smuzhiyun }
617*4882a593Smuzhiyun
greth_clean_tx(struct net_device * dev)618*4882a593Smuzhiyun static void greth_clean_tx(struct net_device *dev)
619*4882a593Smuzhiyun {
620*4882a593Smuzhiyun struct greth_private *greth;
621*4882a593Smuzhiyun struct greth_bd *bdp;
622*4882a593Smuzhiyun u32 stat;
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun greth = netdev_priv(dev);
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun while (1) {
627*4882a593Smuzhiyun bdp = greth->tx_bd_base + greth->tx_last;
628*4882a593Smuzhiyun GRETH_REGSAVE(greth->regs->status, GRETH_INT_TE | GRETH_INT_TX);
629*4882a593Smuzhiyun mb();
630*4882a593Smuzhiyun stat = greth_read_bd(&bdp->stat);
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun if (unlikely(stat & GRETH_BD_EN))
633*4882a593Smuzhiyun break;
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun if (greth->tx_free == GRETH_TXBD_NUM)
636*4882a593Smuzhiyun break;
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun /* Check status for errors */
639*4882a593Smuzhiyun if (unlikely(stat & GRETH_TXBD_STATUS)) {
640*4882a593Smuzhiyun dev->stats.tx_errors++;
641*4882a593Smuzhiyun if (stat & GRETH_TXBD_ERR_AL)
642*4882a593Smuzhiyun dev->stats.tx_aborted_errors++;
643*4882a593Smuzhiyun if (stat & GRETH_TXBD_ERR_UE)
644*4882a593Smuzhiyun dev->stats.tx_fifo_errors++;
645*4882a593Smuzhiyun }
646*4882a593Smuzhiyun dev->stats.tx_packets++;
647*4882a593Smuzhiyun dev->stats.tx_bytes += greth->tx_bufs_length[greth->tx_last];
648*4882a593Smuzhiyun greth->tx_last = NEXT_TX(greth->tx_last);
649*4882a593Smuzhiyun greth->tx_free++;
650*4882a593Smuzhiyun }
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun if (greth->tx_free > 0) {
653*4882a593Smuzhiyun netif_wake_queue(dev);
654*4882a593Smuzhiyun }
655*4882a593Smuzhiyun }
656*4882a593Smuzhiyun
greth_update_tx_stats(struct net_device * dev,u32 stat)657*4882a593Smuzhiyun static inline void greth_update_tx_stats(struct net_device *dev, u32 stat)
658*4882a593Smuzhiyun {
659*4882a593Smuzhiyun /* Check status for errors */
660*4882a593Smuzhiyun if (unlikely(stat & GRETH_TXBD_STATUS)) {
661*4882a593Smuzhiyun dev->stats.tx_errors++;
662*4882a593Smuzhiyun if (stat & GRETH_TXBD_ERR_AL)
663*4882a593Smuzhiyun dev->stats.tx_aborted_errors++;
664*4882a593Smuzhiyun if (stat & GRETH_TXBD_ERR_UE)
665*4882a593Smuzhiyun dev->stats.tx_fifo_errors++;
666*4882a593Smuzhiyun if (stat & GRETH_TXBD_ERR_LC)
667*4882a593Smuzhiyun dev->stats.tx_aborted_errors++;
668*4882a593Smuzhiyun }
669*4882a593Smuzhiyun dev->stats.tx_packets++;
670*4882a593Smuzhiyun }
671*4882a593Smuzhiyun
greth_clean_tx_gbit(struct net_device * dev)672*4882a593Smuzhiyun static void greth_clean_tx_gbit(struct net_device *dev)
673*4882a593Smuzhiyun {
674*4882a593Smuzhiyun struct greth_private *greth;
675*4882a593Smuzhiyun struct greth_bd *bdp, *bdp_last_frag;
676*4882a593Smuzhiyun struct sk_buff *skb = NULL;
677*4882a593Smuzhiyun u32 stat;
678*4882a593Smuzhiyun int nr_frags, i;
679*4882a593Smuzhiyun u16 tx_last;
680*4882a593Smuzhiyun
681*4882a593Smuzhiyun greth = netdev_priv(dev);
682*4882a593Smuzhiyun tx_last = greth->tx_last;
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun while (tx_last != greth->tx_next) {
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun skb = greth->tx_skbuff[tx_last];
687*4882a593Smuzhiyun
688*4882a593Smuzhiyun nr_frags = skb_shinfo(skb)->nr_frags;
689*4882a593Smuzhiyun
690*4882a593Smuzhiyun /* We only clean fully completed SKBs */
691*4882a593Smuzhiyun bdp_last_frag = greth->tx_bd_base + SKIP_TX(tx_last, nr_frags);
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun GRETH_REGSAVE(greth->regs->status, GRETH_INT_TE | GRETH_INT_TX);
694*4882a593Smuzhiyun mb();
695*4882a593Smuzhiyun stat = greth_read_bd(&bdp_last_frag->stat);
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun if (stat & GRETH_BD_EN)
698*4882a593Smuzhiyun break;
699*4882a593Smuzhiyun
700*4882a593Smuzhiyun greth->tx_skbuff[tx_last] = NULL;
701*4882a593Smuzhiyun
702*4882a593Smuzhiyun greth_update_tx_stats(dev, stat);
703*4882a593Smuzhiyun dev->stats.tx_bytes += skb->len;
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun bdp = greth->tx_bd_base + tx_last;
706*4882a593Smuzhiyun
707*4882a593Smuzhiyun tx_last = NEXT_TX(tx_last);
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun dma_unmap_single(greth->dev,
710*4882a593Smuzhiyun greth_read_bd(&bdp->addr),
711*4882a593Smuzhiyun skb_headlen(skb),
712*4882a593Smuzhiyun DMA_TO_DEVICE);
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun for (i = 0; i < nr_frags; i++) {
715*4882a593Smuzhiyun skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
716*4882a593Smuzhiyun bdp = greth->tx_bd_base + tx_last;
717*4882a593Smuzhiyun
718*4882a593Smuzhiyun dma_unmap_page(greth->dev,
719*4882a593Smuzhiyun greth_read_bd(&bdp->addr),
720*4882a593Smuzhiyun skb_frag_size(frag),
721*4882a593Smuzhiyun DMA_TO_DEVICE);
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun tx_last = NEXT_TX(tx_last);
724*4882a593Smuzhiyun }
725*4882a593Smuzhiyun dev_kfree_skb(skb);
726*4882a593Smuzhiyun }
727*4882a593Smuzhiyun if (skb) { /* skb is set only if the above while loop was entered */
728*4882a593Smuzhiyun wmb();
729*4882a593Smuzhiyun greth->tx_last = tx_last;
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun if (netif_queue_stopped(dev) &&
732*4882a593Smuzhiyun (greth_num_free_bds(tx_last, greth->tx_next) >
733*4882a593Smuzhiyun (MAX_SKB_FRAGS+1)))
734*4882a593Smuzhiyun netif_wake_queue(dev);
735*4882a593Smuzhiyun }
736*4882a593Smuzhiyun }
737*4882a593Smuzhiyun
greth_rx(struct net_device * dev,int limit)738*4882a593Smuzhiyun static int greth_rx(struct net_device *dev, int limit)
739*4882a593Smuzhiyun {
740*4882a593Smuzhiyun struct greth_private *greth;
741*4882a593Smuzhiyun struct greth_bd *bdp;
742*4882a593Smuzhiyun struct sk_buff *skb;
743*4882a593Smuzhiyun int pkt_len;
744*4882a593Smuzhiyun int bad, count;
745*4882a593Smuzhiyun u32 status, dma_addr;
746*4882a593Smuzhiyun unsigned long flags;
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun greth = netdev_priv(dev);
749*4882a593Smuzhiyun
750*4882a593Smuzhiyun for (count = 0; count < limit; ++count) {
751*4882a593Smuzhiyun
752*4882a593Smuzhiyun bdp = greth->rx_bd_base + greth->rx_cur;
753*4882a593Smuzhiyun GRETH_REGSAVE(greth->regs->status, GRETH_INT_RE | GRETH_INT_RX);
754*4882a593Smuzhiyun mb();
755*4882a593Smuzhiyun status = greth_read_bd(&bdp->stat);
756*4882a593Smuzhiyun
757*4882a593Smuzhiyun if (unlikely(status & GRETH_BD_EN)) {
758*4882a593Smuzhiyun break;
759*4882a593Smuzhiyun }
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun dma_addr = greth_read_bd(&bdp->addr);
762*4882a593Smuzhiyun bad = 0;
763*4882a593Smuzhiyun
764*4882a593Smuzhiyun /* Check status for errors. */
765*4882a593Smuzhiyun if (unlikely(status & GRETH_RXBD_STATUS)) {
766*4882a593Smuzhiyun if (status & GRETH_RXBD_ERR_FT) {
767*4882a593Smuzhiyun dev->stats.rx_length_errors++;
768*4882a593Smuzhiyun bad = 1;
769*4882a593Smuzhiyun }
770*4882a593Smuzhiyun if (status & (GRETH_RXBD_ERR_AE | GRETH_RXBD_ERR_OE)) {
771*4882a593Smuzhiyun dev->stats.rx_frame_errors++;
772*4882a593Smuzhiyun bad = 1;
773*4882a593Smuzhiyun }
774*4882a593Smuzhiyun if (status & GRETH_RXBD_ERR_CRC) {
775*4882a593Smuzhiyun dev->stats.rx_crc_errors++;
776*4882a593Smuzhiyun bad = 1;
777*4882a593Smuzhiyun }
778*4882a593Smuzhiyun }
779*4882a593Smuzhiyun if (unlikely(bad)) {
780*4882a593Smuzhiyun dev->stats.rx_errors++;
781*4882a593Smuzhiyun
782*4882a593Smuzhiyun } else {
783*4882a593Smuzhiyun
784*4882a593Smuzhiyun pkt_len = status & GRETH_BD_LEN;
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun skb = netdev_alloc_skb(dev, pkt_len + NET_IP_ALIGN);
787*4882a593Smuzhiyun
788*4882a593Smuzhiyun if (unlikely(skb == NULL)) {
789*4882a593Smuzhiyun
790*4882a593Smuzhiyun if (net_ratelimit())
791*4882a593Smuzhiyun dev_warn(&dev->dev, "low on memory - " "packet dropped\n");
792*4882a593Smuzhiyun
793*4882a593Smuzhiyun dev->stats.rx_dropped++;
794*4882a593Smuzhiyun
795*4882a593Smuzhiyun } else {
796*4882a593Smuzhiyun skb_reserve(skb, NET_IP_ALIGN);
797*4882a593Smuzhiyun
798*4882a593Smuzhiyun dma_sync_single_for_cpu(greth->dev,
799*4882a593Smuzhiyun dma_addr,
800*4882a593Smuzhiyun pkt_len,
801*4882a593Smuzhiyun DMA_FROM_DEVICE);
802*4882a593Smuzhiyun
803*4882a593Smuzhiyun if (netif_msg_pktdata(greth))
804*4882a593Smuzhiyun greth_print_rx_packet(phys_to_virt(dma_addr), pkt_len);
805*4882a593Smuzhiyun
806*4882a593Smuzhiyun skb_put_data(skb, phys_to_virt(dma_addr),
807*4882a593Smuzhiyun pkt_len);
808*4882a593Smuzhiyun
809*4882a593Smuzhiyun skb->protocol = eth_type_trans(skb, dev);
810*4882a593Smuzhiyun dev->stats.rx_bytes += pkt_len;
811*4882a593Smuzhiyun dev->stats.rx_packets++;
812*4882a593Smuzhiyun netif_receive_skb(skb);
813*4882a593Smuzhiyun }
814*4882a593Smuzhiyun }
815*4882a593Smuzhiyun
816*4882a593Smuzhiyun status = GRETH_BD_EN | GRETH_BD_IE;
817*4882a593Smuzhiyun if (greth->rx_cur == GRETH_RXBD_NUM_MASK) {
818*4882a593Smuzhiyun status |= GRETH_BD_WR;
819*4882a593Smuzhiyun }
820*4882a593Smuzhiyun
821*4882a593Smuzhiyun wmb();
822*4882a593Smuzhiyun greth_write_bd(&bdp->stat, status);
823*4882a593Smuzhiyun
824*4882a593Smuzhiyun dma_sync_single_for_device(greth->dev, dma_addr, MAX_FRAME_SIZE, DMA_FROM_DEVICE);
825*4882a593Smuzhiyun
826*4882a593Smuzhiyun spin_lock_irqsave(&greth->devlock, flags); /* save from XMIT */
827*4882a593Smuzhiyun greth_enable_rx(greth);
828*4882a593Smuzhiyun spin_unlock_irqrestore(&greth->devlock, flags);
829*4882a593Smuzhiyun
830*4882a593Smuzhiyun greth->rx_cur = NEXT_RX(greth->rx_cur);
831*4882a593Smuzhiyun }
832*4882a593Smuzhiyun
833*4882a593Smuzhiyun return count;
834*4882a593Smuzhiyun }
835*4882a593Smuzhiyun
hw_checksummed(u32 status)836*4882a593Smuzhiyun static inline int hw_checksummed(u32 status)
837*4882a593Smuzhiyun {
838*4882a593Smuzhiyun
839*4882a593Smuzhiyun if (status & GRETH_RXBD_IP_FRAG)
840*4882a593Smuzhiyun return 0;
841*4882a593Smuzhiyun
842*4882a593Smuzhiyun if (status & GRETH_RXBD_IP && status & GRETH_RXBD_IP_CSERR)
843*4882a593Smuzhiyun return 0;
844*4882a593Smuzhiyun
845*4882a593Smuzhiyun if (status & GRETH_RXBD_UDP && status & GRETH_RXBD_UDP_CSERR)
846*4882a593Smuzhiyun return 0;
847*4882a593Smuzhiyun
848*4882a593Smuzhiyun if (status & GRETH_RXBD_TCP && status & GRETH_RXBD_TCP_CSERR)
849*4882a593Smuzhiyun return 0;
850*4882a593Smuzhiyun
851*4882a593Smuzhiyun return 1;
852*4882a593Smuzhiyun }
853*4882a593Smuzhiyun
greth_rx_gbit(struct net_device * dev,int limit)854*4882a593Smuzhiyun static int greth_rx_gbit(struct net_device *dev, int limit)
855*4882a593Smuzhiyun {
856*4882a593Smuzhiyun struct greth_private *greth;
857*4882a593Smuzhiyun struct greth_bd *bdp;
858*4882a593Smuzhiyun struct sk_buff *skb, *newskb;
859*4882a593Smuzhiyun int pkt_len;
860*4882a593Smuzhiyun int bad, count = 0;
861*4882a593Smuzhiyun u32 status, dma_addr;
862*4882a593Smuzhiyun unsigned long flags;
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun greth = netdev_priv(dev);
865*4882a593Smuzhiyun
866*4882a593Smuzhiyun for (count = 0; count < limit; ++count) {
867*4882a593Smuzhiyun
868*4882a593Smuzhiyun bdp = greth->rx_bd_base + greth->rx_cur;
869*4882a593Smuzhiyun skb = greth->rx_skbuff[greth->rx_cur];
870*4882a593Smuzhiyun GRETH_REGSAVE(greth->regs->status, GRETH_INT_RE | GRETH_INT_RX);
871*4882a593Smuzhiyun mb();
872*4882a593Smuzhiyun status = greth_read_bd(&bdp->stat);
873*4882a593Smuzhiyun bad = 0;
874*4882a593Smuzhiyun
875*4882a593Smuzhiyun if (status & GRETH_BD_EN)
876*4882a593Smuzhiyun break;
877*4882a593Smuzhiyun
878*4882a593Smuzhiyun /* Check status for errors. */
879*4882a593Smuzhiyun if (unlikely(status & GRETH_RXBD_STATUS)) {
880*4882a593Smuzhiyun
881*4882a593Smuzhiyun if (status & GRETH_RXBD_ERR_FT) {
882*4882a593Smuzhiyun dev->stats.rx_length_errors++;
883*4882a593Smuzhiyun bad = 1;
884*4882a593Smuzhiyun } else if (status &
885*4882a593Smuzhiyun (GRETH_RXBD_ERR_AE | GRETH_RXBD_ERR_OE | GRETH_RXBD_ERR_LE)) {
886*4882a593Smuzhiyun dev->stats.rx_frame_errors++;
887*4882a593Smuzhiyun bad = 1;
888*4882a593Smuzhiyun } else if (status & GRETH_RXBD_ERR_CRC) {
889*4882a593Smuzhiyun dev->stats.rx_crc_errors++;
890*4882a593Smuzhiyun bad = 1;
891*4882a593Smuzhiyun }
892*4882a593Smuzhiyun }
893*4882a593Smuzhiyun
894*4882a593Smuzhiyun /* Allocate new skb to replace current, not needed if the
895*4882a593Smuzhiyun * current skb can be reused */
896*4882a593Smuzhiyun if (!bad && (newskb=netdev_alloc_skb(dev, MAX_FRAME_SIZE + NET_IP_ALIGN))) {
897*4882a593Smuzhiyun skb_reserve(newskb, NET_IP_ALIGN);
898*4882a593Smuzhiyun
899*4882a593Smuzhiyun dma_addr = dma_map_single(greth->dev,
900*4882a593Smuzhiyun newskb->data,
901*4882a593Smuzhiyun MAX_FRAME_SIZE + NET_IP_ALIGN,
902*4882a593Smuzhiyun DMA_FROM_DEVICE);
903*4882a593Smuzhiyun
904*4882a593Smuzhiyun if (!dma_mapping_error(greth->dev, dma_addr)) {
905*4882a593Smuzhiyun /* Process the incoming frame. */
906*4882a593Smuzhiyun pkt_len = status & GRETH_BD_LEN;
907*4882a593Smuzhiyun
908*4882a593Smuzhiyun dma_unmap_single(greth->dev,
909*4882a593Smuzhiyun greth_read_bd(&bdp->addr),
910*4882a593Smuzhiyun MAX_FRAME_SIZE + NET_IP_ALIGN,
911*4882a593Smuzhiyun DMA_FROM_DEVICE);
912*4882a593Smuzhiyun
913*4882a593Smuzhiyun if (netif_msg_pktdata(greth))
914*4882a593Smuzhiyun greth_print_rx_packet(phys_to_virt(greth_read_bd(&bdp->addr)), pkt_len);
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun skb_put(skb, pkt_len);
917*4882a593Smuzhiyun
918*4882a593Smuzhiyun if (dev->features & NETIF_F_RXCSUM && hw_checksummed(status))
919*4882a593Smuzhiyun skb->ip_summed = CHECKSUM_UNNECESSARY;
920*4882a593Smuzhiyun else
921*4882a593Smuzhiyun skb_checksum_none_assert(skb);
922*4882a593Smuzhiyun
923*4882a593Smuzhiyun skb->protocol = eth_type_trans(skb, dev);
924*4882a593Smuzhiyun dev->stats.rx_packets++;
925*4882a593Smuzhiyun dev->stats.rx_bytes += pkt_len;
926*4882a593Smuzhiyun netif_receive_skb(skb);
927*4882a593Smuzhiyun
928*4882a593Smuzhiyun greth->rx_skbuff[greth->rx_cur] = newskb;
929*4882a593Smuzhiyun greth_write_bd(&bdp->addr, dma_addr);
930*4882a593Smuzhiyun } else {
931*4882a593Smuzhiyun if (net_ratelimit())
932*4882a593Smuzhiyun dev_warn(greth->dev, "Could not create DMA mapping, dropping packet\n");
933*4882a593Smuzhiyun dev_kfree_skb(newskb);
934*4882a593Smuzhiyun /* reusing current skb, so it is a drop */
935*4882a593Smuzhiyun dev->stats.rx_dropped++;
936*4882a593Smuzhiyun }
937*4882a593Smuzhiyun } else if (bad) {
938*4882a593Smuzhiyun /* Bad Frame transfer, the skb is reused */
939*4882a593Smuzhiyun dev->stats.rx_dropped++;
940*4882a593Smuzhiyun } else {
941*4882a593Smuzhiyun /* Failed Allocating a new skb. This is rather stupid
942*4882a593Smuzhiyun * but the current "filled" skb is reused, as if
943*4882a593Smuzhiyun * transfer failure. One could argue that RX descriptor
944*4882a593Smuzhiyun * table handling should be divided into cleaning and
945*4882a593Smuzhiyun * filling as the TX part of the driver
946*4882a593Smuzhiyun */
947*4882a593Smuzhiyun if (net_ratelimit())
948*4882a593Smuzhiyun dev_warn(greth->dev, "Could not allocate SKB, dropping packet\n");
949*4882a593Smuzhiyun /* reusing current skb, so it is a drop */
950*4882a593Smuzhiyun dev->stats.rx_dropped++;
951*4882a593Smuzhiyun }
952*4882a593Smuzhiyun
953*4882a593Smuzhiyun status = GRETH_BD_EN | GRETH_BD_IE;
954*4882a593Smuzhiyun if (greth->rx_cur == GRETH_RXBD_NUM_MASK) {
955*4882a593Smuzhiyun status |= GRETH_BD_WR;
956*4882a593Smuzhiyun }
957*4882a593Smuzhiyun
958*4882a593Smuzhiyun wmb();
959*4882a593Smuzhiyun greth_write_bd(&bdp->stat, status);
960*4882a593Smuzhiyun spin_lock_irqsave(&greth->devlock, flags);
961*4882a593Smuzhiyun greth_enable_rx(greth);
962*4882a593Smuzhiyun spin_unlock_irqrestore(&greth->devlock, flags);
963*4882a593Smuzhiyun greth->rx_cur = NEXT_RX(greth->rx_cur);
964*4882a593Smuzhiyun }
965*4882a593Smuzhiyun
966*4882a593Smuzhiyun return count;
967*4882a593Smuzhiyun
968*4882a593Smuzhiyun }
969*4882a593Smuzhiyun
greth_poll(struct napi_struct * napi,int budget)970*4882a593Smuzhiyun static int greth_poll(struct napi_struct *napi, int budget)
971*4882a593Smuzhiyun {
972*4882a593Smuzhiyun struct greth_private *greth;
973*4882a593Smuzhiyun int work_done = 0;
974*4882a593Smuzhiyun unsigned long flags;
975*4882a593Smuzhiyun u32 mask, ctrl;
976*4882a593Smuzhiyun greth = container_of(napi, struct greth_private, napi);
977*4882a593Smuzhiyun
978*4882a593Smuzhiyun restart_txrx_poll:
979*4882a593Smuzhiyun if (greth->gbit_mac) {
980*4882a593Smuzhiyun greth_clean_tx_gbit(greth->netdev);
981*4882a593Smuzhiyun work_done += greth_rx_gbit(greth->netdev, budget - work_done);
982*4882a593Smuzhiyun } else {
983*4882a593Smuzhiyun if (netif_queue_stopped(greth->netdev))
984*4882a593Smuzhiyun greth_clean_tx(greth->netdev);
985*4882a593Smuzhiyun work_done += greth_rx(greth->netdev, budget - work_done);
986*4882a593Smuzhiyun }
987*4882a593Smuzhiyun
988*4882a593Smuzhiyun if (work_done < budget) {
989*4882a593Smuzhiyun
990*4882a593Smuzhiyun spin_lock_irqsave(&greth->devlock, flags);
991*4882a593Smuzhiyun
992*4882a593Smuzhiyun ctrl = GRETH_REGLOAD(greth->regs->control);
993*4882a593Smuzhiyun if ((greth->gbit_mac && (greth->tx_last != greth->tx_next)) ||
994*4882a593Smuzhiyun (!greth->gbit_mac && netif_queue_stopped(greth->netdev))) {
995*4882a593Smuzhiyun GRETH_REGSAVE(greth->regs->control,
996*4882a593Smuzhiyun ctrl | GRETH_TXI | GRETH_RXI);
997*4882a593Smuzhiyun mask = GRETH_INT_RX | GRETH_INT_RE |
998*4882a593Smuzhiyun GRETH_INT_TX | GRETH_INT_TE;
999*4882a593Smuzhiyun } else {
1000*4882a593Smuzhiyun GRETH_REGSAVE(greth->regs->control, ctrl | GRETH_RXI);
1001*4882a593Smuzhiyun mask = GRETH_INT_RX | GRETH_INT_RE;
1002*4882a593Smuzhiyun }
1003*4882a593Smuzhiyun
1004*4882a593Smuzhiyun if (GRETH_REGLOAD(greth->regs->status) & mask) {
1005*4882a593Smuzhiyun GRETH_REGSAVE(greth->regs->control, ctrl);
1006*4882a593Smuzhiyun spin_unlock_irqrestore(&greth->devlock, flags);
1007*4882a593Smuzhiyun goto restart_txrx_poll;
1008*4882a593Smuzhiyun } else {
1009*4882a593Smuzhiyun napi_complete_done(napi, work_done);
1010*4882a593Smuzhiyun spin_unlock_irqrestore(&greth->devlock, flags);
1011*4882a593Smuzhiyun }
1012*4882a593Smuzhiyun }
1013*4882a593Smuzhiyun
1014*4882a593Smuzhiyun return work_done;
1015*4882a593Smuzhiyun }
1016*4882a593Smuzhiyun
greth_set_mac_add(struct net_device * dev,void * p)1017*4882a593Smuzhiyun static int greth_set_mac_add(struct net_device *dev, void *p)
1018*4882a593Smuzhiyun {
1019*4882a593Smuzhiyun struct sockaddr *addr = p;
1020*4882a593Smuzhiyun struct greth_private *greth;
1021*4882a593Smuzhiyun struct greth_regs *regs;
1022*4882a593Smuzhiyun
1023*4882a593Smuzhiyun greth = netdev_priv(dev);
1024*4882a593Smuzhiyun regs = greth->regs;
1025*4882a593Smuzhiyun
1026*4882a593Smuzhiyun if (!is_valid_ether_addr(addr->sa_data))
1027*4882a593Smuzhiyun return -EADDRNOTAVAIL;
1028*4882a593Smuzhiyun
1029*4882a593Smuzhiyun memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1030*4882a593Smuzhiyun GRETH_REGSAVE(regs->esa_msb, dev->dev_addr[0] << 8 | dev->dev_addr[1]);
1031*4882a593Smuzhiyun GRETH_REGSAVE(regs->esa_lsb, dev->dev_addr[2] << 24 | dev->dev_addr[3] << 16 |
1032*4882a593Smuzhiyun dev->dev_addr[4] << 8 | dev->dev_addr[5]);
1033*4882a593Smuzhiyun
1034*4882a593Smuzhiyun return 0;
1035*4882a593Smuzhiyun }
1036*4882a593Smuzhiyun
greth_hash_get_index(__u8 * addr)1037*4882a593Smuzhiyun static u32 greth_hash_get_index(__u8 *addr)
1038*4882a593Smuzhiyun {
1039*4882a593Smuzhiyun return (ether_crc(6, addr)) & 0x3F;
1040*4882a593Smuzhiyun }
1041*4882a593Smuzhiyun
greth_set_hash_filter(struct net_device * dev)1042*4882a593Smuzhiyun static void greth_set_hash_filter(struct net_device *dev)
1043*4882a593Smuzhiyun {
1044*4882a593Smuzhiyun struct netdev_hw_addr *ha;
1045*4882a593Smuzhiyun struct greth_private *greth = netdev_priv(dev);
1046*4882a593Smuzhiyun struct greth_regs *regs = greth->regs;
1047*4882a593Smuzhiyun u32 mc_filter[2];
1048*4882a593Smuzhiyun unsigned int bitnr;
1049*4882a593Smuzhiyun
1050*4882a593Smuzhiyun mc_filter[0] = mc_filter[1] = 0;
1051*4882a593Smuzhiyun
1052*4882a593Smuzhiyun netdev_for_each_mc_addr(ha, dev) {
1053*4882a593Smuzhiyun bitnr = greth_hash_get_index(ha->addr);
1054*4882a593Smuzhiyun mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1055*4882a593Smuzhiyun }
1056*4882a593Smuzhiyun
1057*4882a593Smuzhiyun GRETH_REGSAVE(regs->hash_msb, mc_filter[1]);
1058*4882a593Smuzhiyun GRETH_REGSAVE(regs->hash_lsb, mc_filter[0]);
1059*4882a593Smuzhiyun }
1060*4882a593Smuzhiyun
greth_set_multicast_list(struct net_device * dev)1061*4882a593Smuzhiyun static void greth_set_multicast_list(struct net_device *dev)
1062*4882a593Smuzhiyun {
1063*4882a593Smuzhiyun int cfg;
1064*4882a593Smuzhiyun struct greth_private *greth = netdev_priv(dev);
1065*4882a593Smuzhiyun struct greth_regs *regs = greth->regs;
1066*4882a593Smuzhiyun
1067*4882a593Smuzhiyun cfg = GRETH_REGLOAD(regs->control);
1068*4882a593Smuzhiyun if (dev->flags & IFF_PROMISC)
1069*4882a593Smuzhiyun cfg |= GRETH_CTRL_PR;
1070*4882a593Smuzhiyun else
1071*4882a593Smuzhiyun cfg &= ~GRETH_CTRL_PR;
1072*4882a593Smuzhiyun
1073*4882a593Smuzhiyun if (greth->multicast) {
1074*4882a593Smuzhiyun if (dev->flags & IFF_ALLMULTI) {
1075*4882a593Smuzhiyun GRETH_REGSAVE(regs->hash_msb, -1);
1076*4882a593Smuzhiyun GRETH_REGSAVE(regs->hash_lsb, -1);
1077*4882a593Smuzhiyun cfg |= GRETH_CTRL_MCEN;
1078*4882a593Smuzhiyun GRETH_REGSAVE(regs->control, cfg);
1079*4882a593Smuzhiyun return;
1080*4882a593Smuzhiyun }
1081*4882a593Smuzhiyun
1082*4882a593Smuzhiyun if (netdev_mc_empty(dev)) {
1083*4882a593Smuzhiyun cfg &= ~GRETH_CTRL_MCEN;
1084*4882a593Smuzhiyun GRETH_REGSAVE(regs->control, cfg);
1085*4882a593Smuzhiyun return;
1086*4882a593Smuzhiyun }
1087*4882a593Smuzhiyun
1088*4882a593Smuzhiyun /* Setup multicast filter */
1089*4882a593Smuzhiyun greth_set_hash_filter(dev);
1090*4882a593Smuzhiyun cfg |= GRETH_CTRL_MCEN;
1091*4882a593Smuzhiyun }
1092*4882a593Smuzhiyun GRETH_REGSAVE(regs->control, cfg);
1093*4882a593Smuzhiyun }
1094*4882a593Smuzhiyun
greth_get_msglevel(struct net_device * dev)1095*4882a593Smuzhiyun static u32 greth_get_msglevel(struct net_device *dev)
1096*4882a593Smuzhiyun {
1097*4882a593Smuzhiyun struct greth_private *greth = netdev_priv(dev);
1098*4882a593Smuzhiyun return greth->msg_enable;
1099*4882a593Smuzhiyun }
1100*4882a593Smuzhiyun
greth_set_msglevel(struct net_device * dev,u32 value)1101*4882a593Smuzhiyun static void greth_set_msglevel(struct net_device *dev, u32 value)
1102*4882a593Smuzhiyun {
1103*4882a593Smuzhiyun struct greth_private *greth = netdev_priv(dev);
1104*4882a593Smuzhiyun greth->msg_enable = value;
1105*4882a593Smuzhiyun }
1106*4882a593Smuzhiyun
greth_get_regs_len(struct net_device * dev)1107*4882a593Smuzhiyun static int greth_get_regs_len(struct net_device *dev)
1108*4882a593Smuzhiyun {
1109*4882a593Smuzhiyun return sizeof(struct greth_regs);
1110*4882a593Smuzhiyun }
1111*4882a593Smuzhiyun
greth_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)1112*4882a593Smuzhiyun static void greth_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1113*4882a593Smuzhiyun {
1114*4882a593Smuzhiyun struct greth_private *greth = netdev_priv(dev);
1115*4882a593Smuzhiyun
1116*4882a593Smuzhiyun strlcpy(info->driver, dev_driver_string(greth->dev),
1117*4882a593Smuzhiyun sizeof(info->driver));
1118*4882a593Smuzhiyun strlcpy(info->bus_info, greth->dev->bus->name, sizeof(info->bus_info));
1119*4882a593Smuzhiyun }
1120*4882a593Smuzhiyun
greth_get_regs(struct net_device * dev,struct ethtool_regs * regs,void * p)1121*4882a593Smuzhiyun static void greth_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *p)
1122*4882a593Smuzhiyun {
1123*4882a593Smuzhiyun int i;
1124*4882a593Smuzhiyun struct greth_private *greth = netdev_priv(dev);
1125*4882a593Smuzhiyun u32 __iomem *greth_regs = (u32 __iomem *) greth->regs;
1126*4882a593Smuzhiyun u32 *buff = p;
1127*4882a593Smuzhiyun
1128*4882a593Smuzhiyun for (i = 0; i < sizeof(struct greth_regs) / sizeof(u32); i++)
1129*4882a593Smuzhiyun buff[i] = greth_read_bd(&greth_regs[i]);
1130*4882a593Smuzhiyun }
1131*4882a593Smuzhiyun
1132*4882a593Smuzhiyun static const struct ethtool_ops greth_ethtool_ops = {
1133*4882a593Smuzhiyun .get_msglevel = greth_get_msglevel,
1134*4882a593Smuzhiyun .set_msglevel = greth_set_msglevel,
1135*4882a593Smuzhiyun .get_drvinfo = greth_get_drvinfo,
1136*4882a593Smuzhiyun .get_regs_len = greth_get_regs_len,
1137*4882a593Smuzhiyun .get_regs = greth_get_regs,
1138*4882a593Smuzhiyun .get_link = ethtool_op_get_link,
1139*4882a593Smuzhiyun .get_link_ksettings = phy_ethtool_get_link_ksettings,
1140*4882a593Smuzhiyun .set_link_ksettings = phy_ethtool_set_link_ksettings,
1141*4882a593Smuzhiyun };
1142*4882a593Smuzhiyun
1143*4882a593Smuzhiyun static struct net_device_ops greth_netdev_ops = {
1144*4882a593Smuzhiyun .ndo_open = greth_open,
1145*4882a593Smuzhiyun .ndo_stop = greth_close,
1146*4882a593Smuzhiyun .ndo_start_xmit = greth_start_xmit,
1147*4882a593Smuzhiyun .ndo_set_mac_address = greth_set_mac_add,
1148*4882a593Smuzhiyun .ndo_validate_addr = eth_validate_addr,
1149*4882a593Smuzhiyun };
1150*4882a593Smuzhiyun
wait_for_mdio(struct greth_private * greth)1151*4882a593Smuzhiyun static inline int wait_for_mdio(struct greth_private *greth)
1152*4882a593Smuzhiyun {
1153*4882a593Smuzhiyun unsigned long timeout = jiffies + 4*HZ/100;
1154*4882a593Smuzhiyun while (GRETH_REGLOAD(greth->regs->mdio) & GRETH_MII_BUSY) {
1155*4882a593Smuzhiyun if (time_after(jiffies, timeout))
1156*4882a593Smuzhiyun return 0;
1157*4882a593Smuzhiyun }
1158*4882a593Smuzhiyun return 1;
1159*4882a593Smuzhiyun }
1160*4882a593Smuzhiyun
greth_mdio_read(struct mii_bus * bus,int phy,int reg)1161*4882a593Smuzhiyun static int greth_mdio_read(struct mii_bus *bus, int phy, int reg)
1162*4882a593Smuzhiyun {
1163*4882a593Smuzhiyun struct greth_private *greth = bus->priv;
1164*4882a593Smuzhiyun int data;
1165*4882a593Smuzhiyun
1166*4882a593Smuzhiyun if (!wait_for_mdio(greth))
1167*4882a593Smuzhiyun return -EBUSY;
1168*4882a593Smuzhiyun
1169*4882a593Smuzhiyun GRETH_REGSAVE(greth->regs->mdio, ((phy & 0x1F) << 11) | ((reg & 0x1F) << 6) | 2);
1170*4882a593Smuzhiyun
1171*4882a593Smuzhiyun if (!wait_for_mdio(greth))
1172*4882a593Smuzhiyun return -EBUSY;
1173*4882a593Smuzhiyun
1174*4882a593Smuzhiyun if (!(GRETH_REGLOAD(greth->regs->mdio) & GRETH_MII_NVALID)) {
1175*4882a593Smuzhiyun data = (GRETH_REGLOAD(greth->regs->mdio) >> 16) & 0xFFFF;
1176*4882a593Smuzhiyun return data;
1177*4882a593Smuzhiyun
1178*4882a593Smuzhiyun } else {
1179*4882a593Smuzhiyun return -1;
1180*4882a593Smuzhiyun }
1181*4882a593Smuzhiyun }
1182*4882a593Smuzhiyun
greth_mdio_write(struct mii_bus * bus,int phy,int reg,u16 val)1183*4882a593Smuzhiyun static int greth_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
1184*4882a593Smuzhiyun {
1185*4882a593Smuzhiyun struct greth_private *greth = bus->priv;
1186*4882a593Smuzhiyun
1187*4882a593Smuzhiyun if (!wait_for_mdio(greth))
1188*4882a593Smuzhiyun return -EBUSY;
1189*4882a593Smuzhiyun
1190*4882a593Smuzhiyun GRETH_REGSAVE(greth->regs->mdio,
1191*4882a593Smuzhiyun ((val & 0xFFFF) << 16) | ((phy & 0x1F) << 11) | ((reg & 0x1F) << 6) | 1);
1192*4882a593Smuzhiyun
1193*4882a593Smuzhiyun if (!wait_for_mdio(greth))
1194*4882a593Smuzhiyun return -EBUSY;
1195*4882a593Smuzhiyun
1196*4882a593Smuzhiyun return 0;
1197*4882a593Smuzhiyun }
1198*4882a593Smuzhiyun
greth_link_change(struct net_device * dev)1199*4882a593Smuzhiyun static void greth_link_change(struct net_device *dev)
1200*4882a593Smuzhiyun {
1201*4882a593Smuzhiyun struct greth_private *greth = netdev_priv(dev);
1202*4882a593Smuzhiyun struct phy_device *phydev = dev->phydev;
1203*4882a593Smuzhiyun unsigned long flags;
1204*4882a593Smuzhiyun int status_change = 0;
1205*4882a593Smuzhiyun u32 ctrl;
1206*4882a593Smuzhiyun
1207*4882a593Smuzhiyun spin_lock_irqsave(&greth->devlock, flags);
1208*4882a593Smuzhiyun
1209*4882a593Smuzhiyun if (phydev->link) {
1210*4882a593Smuzhiyun
1211*4882a593Smuzhiyun if ((greth->speed != phydev->speed) || (greth->duplex != phydev->duplex)) {
1212*4882a593Smuzhiyun ctrl = GRETH_REGLOAD(greth->regs->control) &
1213*4882a593Smuzhiyun ~(GRETH_CTRL_FD | GRETH_CTRL_SP | GRETH_CTRL_GB);
1214*4882a593Smuzhiyun
1215*4882a593Smuzhiyun if (phydev->duplex)
1216*4882a593Smuzhiyun ctrl |= GRETH_CTRL_FD;
1217*4882a593Smuzhiyun
1218*4882a593Smuzhiyun if (phydev->speed == SPEED_100)
1219*4882a593Smuzhiyun ctrl |= GRETH_CTRL_SP;
1220*4882a593Smuzhiyun else if (phydev->speed == SPEED_1000)
1221*4882a593Smuzhiyun ctrl |= GRETH_CTRL_GB;
1222*4882a593Smuzhiyun
1223*4882a593Smuzhiyun GRETH_REGSAVE(greth->regs->control, ctrl);
1224*4882a593Smuzhiyun greth->speed = phydev->speed;
1225*4882a593Smuzhiyun greth->duplex = phydev->duplex;
1226*4882a593Smuzhiyun status_change = 1;
1227*4882a593Smuzhiyun }
1228*4882a593Smuzhiyun }
1229*4882a593Smuzhiyun
1230*4882a593Smuzhiyun if (phydev->link != greth->link) {
1231*4882a593Smuzhiyun if (!phydev->link) {
1232*4882a593Smuzhiyun greth->speed = 0;
1233*4882a593Smuzhiyun greth->duplex = -1;
1234*4882a593Smuzhiyun }
1235*4882a593Smuzhiyun greth->link = phydev->link;
1236*4882a593Smuzhiyun
1237*4882a593Smuzhiyun status_change = 1;
1238*4882a593Smuzhiyun }
1239*4882a593Smuzhiyun
1240*4882a593Smuzhiyun spin_unlock_irqrestore(&greth->devlock, flags);
1241*4882a593Smuzhiyun
1242*4882a593Smuzhiyun if (status_change) {
1243*4882a593Smuzhiyun if (phydev->link)
1244*4882a593Smuzhiyun pr_debug("%s: link up (%d/%s)\n",
1245*4882a593Smuzhiyun dev->name, phydev->speed,
1246*4882a593Smuzhiyun DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
1247*4882a593Smuzhiyun else
1248*4882a593Smuzhiyun pr_debug("%s: link down\n", dev->name);
1249*4882a593Smuzhiyun }
1250*4882a593Smuzhiyun }
1251*4882a593Smuzhiyun
greth_mdio_probe(struct net_device * dev)1252*4882a593Smuzhiyun static int greth_mdio_probe(struct net_device *dev)
1253*4882a593Smuzhiyun {
1254*4882a593Smuzhiyun struct greth_private *greth = netdev_priv(dev);
1255*4882a593Smuzhiyun struct phy_device *phy = NULL;
1256*4882a593Smuzhiyun int ret;
1257*4882a593Smuzhiyun
1258*4882a593Smuzhiyun /* Find the first PHY */
1259*4882a593Smuzhiyun phy = phy_find_first(greth->mdio);
1260*4882a593Smuzhiyun
1261*4882a593Smuzhiyun if (!phy) {
1262*4882a593Smuzhiyun if (netif_msg_probe(greth))
1263*4882a593Smuzhiyun dev_err(&dev->dev, "no PHY found\n");
1264*4882a593Smuzhiyun return -ENXIO;
1265*4882a593Smuzhiyun }
1266*4882a593Smuzhiyun
1267*4882a593Smuzhiyun ret = phy_connect_direct(dev, phy, &greth_link_change,
1268*4882a593Smuzhiyun greth->gbit_mac ? PHY_INTERFACE_MODE_GMII : PHY_INTERFACE_MODE_MII);
1269*4882a593Smuzhiyun if (ret) {
1270*4882a593Smuzhiyun if (netif_msg_ifup(greth))
1271*4882a593Smuzhiyun dev_err(&dev->dev, "could not attach to PHY\n");
1272*4882a593Smuzhiyun return ret;
1273*4882a593Smuzhiyun }
1274*4882a593Smuzhiyun
1275*4882a593Smuzhiyun if (greth->gbit_mac)
1276*4882a593Smuzhiyun phy_set_max_speed(phy, SPEED_1000);
1277*4882a593Smuzhiyun else
1278*4882a593Smuzhiyun phy_set_max_speed(phy, SPEED_100);
1279*4882a593Smuzhiyun
1280*4882a593Smuzhiyun linkmode_copy(phy->advertising, phy->supported);
1281*4882a593Smuzhiyun
1282*4882a593Smuzhiyun greth->link = 0;
1283*4882a593Smuzhiyun greth->speed = 0;
1284*4882a593Smuzhiyun greth->duplex = -1;
1285*4882a593Smuzhiyun
1286*4882a593Smuzhiyun return 0;
1287*4882a593Smuzhiyun }
1288*4882a593Smuzhiyun
greth_mdio_init(struct greth_private * greth)1289*4882a593Smuzhiyun static int greth_mdio_init(struct greth_private *greth)
1290*4882a593Smuzhiyun {
1291*4882a593Smuzhiyun int ret;
1292*4882a593Smuzhiyun unsigned long timeout;
1293*4882a593Smuzhiyun struct net_device *ndev = greth->netdev;
1294*4882a593Smuzhiyun
1295*4882a593Smuzhiyun greth->mdio = mdiobus_alloc();
1296*4882a593Smuzhiyun if (!greth->mdio) {
1297*4882a593Smuzhiyun return -ENOMEM;
1298*4882a593Smuzhiyun }
1299*4882a593Smuzhiyun
1300*4882a593Smuzhiyun greth->mdio->name = "greth-mdio";
1301*4882a593Smuzhiyun snprintf(greth->mdio->id, MII_BUS_ID_SIZE, "%s-%d", greth->mdio->name, greth->irq);
1302*4882a593Smuzhiyun greth->mdio->read = greth_mdio_read;
1303*4882a593Smuzhiyun greth->mdio->write = greth_mdio_write;
1304*4882a593Smuzhiyun greth->mdio->priv = greth;
1305*4882a593Smuzhiyun
1306*4882a593Smuzhiyun ret = mdiobus_register(greth->mdio);
1307*4882a593Smuzhiyun if (ret) {
1308*4882a593Smuzhiyun goto error;
1309*4882a593Smuzhiyun }
1310*4882a593Smuzhiyun
1311*4882a593Smuzhiyun ret = greth_mdio_probe(greth->netdev);
1312*4882a593Smuzhiyun if (ret) {
1313*4882a593Smuzhiyun if (netif_msg_probe(greth))
1314*4882a593Smuzhiyun dev_err(&greth->netdev->dev, "failed to probe MDIO bus\n");
1315*4882a593Smuzhiyun goto unreg_mdio;
1316*4882a593Smuzhiyun }
1317*4882a593Smuzhiyun
1318*4882a593Smuzhiyun phy_start(ndev->phydev);
1319*4882a593Smuzhiyun
1320*4882a593Smuzhiyun /* If Ethernet debug link is used make autoneg happen right away */
1321*4882a593Smuzhiyun if (greth->edcl && greth_edcl == 1) {
1322*4882a593Smuzhiyun phy_start_aneg(ndev->phydev);
1323*4882a593Smuzhiyun timeout = jiffies + 6*HZ;
1324*4882a593Smuzhiyun while (!phy_aneg_done(ndev->phydev) &&
1325*4882a593Smuzhiyun time_before(jiffies, timeout)) {
1326*4882a593Smuzhiyun }
1327*4882a593Smuzhiyun phy_read_status(ndev->phydev);
1328*4882a593Smuzhiyun greth_link_change(greth->netdev);
1329*4882a593Smuzhiyun }
1330*4882a593Smuzhiyun
1331*4882a593Smuzhiyun return 0;
1332*4882a593Smuzhiyun
1333*4882a593Smuzhiyun unreg_mdio:
1334*4882a593Smuzhiyun mdiobus_unregister(greth->mdio);
1335*4882a593Smuzhiyun error:
1336*4882a593Smuzhiyun mdiobus_free(greth->mdio);
1337*4882a593Smuzhiyun return ret;
1338*4882a593Smuzhiyun }
1339*4882a593Smuzhiyun
1340*4882a593Smuzhiyun /* Initialize the GRETH MAC */
greth_of_probe(struct platform_device * ofdev)1341*4882a593Smuzhiyun static int greth_of_probe(struct platform_device *ofdev)
1342*4882a593Smuzhiyun {
1343*4882a593Smuzhiyun struct net_device *dev;
1344*4882a593Smuzhiyun struct greth_private *greth;
1345*4882a593Smuzhiyun struct greth_regs *regs;
1346*4882a593Smuzhiyun
1347*4882a593Smuzhiyun int i;
1348*4882a593Smuzhiyun int err;
1349*4882a593Smuzhiyun int tmp;
1350*4882a593Smuzhiyun unsigned long timeout;
1351*4882a593Smuzhiyun
1352*4882a593Smuzhiyun dev = alloc_etherdev(sizeof(struct greth_private));
1353*4882a593Smuzhiyun
1354*4882a593Smuzhiyun if (dev == NULL)
1355*4882a593Smuzhiyun return -ENOMEM;
1356*4882a593Smuzhiyun
1357*4882a593Smuzhiyun greth = netdev_priv(dev);
1358*4882a593Smuzhiyun greth->netdev = dev;
1359*4882a593Smuzhiyun greth->dev = &ofdev->dev;
1360*4882a593Smuzhiyun
1361*4882a593Smuzhiyun if (greth_debug > 0)
1362*4882a593Smuzhiyun greth->msg_enable = greth_debug;
1363*4882a593Smuzhiyun else
1364*4882a593Smuzhiyun greth->msg_enable = GRETH_DEF_MSG_ENABLE;
1365*4882a593Smuzhiyun
1366*4882a593Smuzhiyun spin_lock_init(&greth->devlock);
1367*4882a593Smuzhiyun
1368*4882a593Smuzhiyun greth->regs = of_ioremap(&ofdev->resource[0], 0,
1369*4882a593Smuzhiyun resource_size(&ofdev->resource[0]),
1370*4882a593Smuzhiyun "grlib-greth regs");
1371*4882a593Smuzhiyun
1372*4882a593Smuzhiyun if (greth->regs == NULL) {
1373*4882a593Smuzhiyun if (netif_msg_probe(greth))
1374*4882a593Smuzhiyun dev_err(greth->dev, "ioremap failure.\n");
1375*4882a593Smuzhiyun err = -EIO;
1376*4882a593Smuzhiyun goto error1;
1377*4882a593Smuzhiyun }
1378*4882a593Smuzhiyun
1379*4882a593Smuzhiyun regs = greth->regs;
1380*4882a593Smuzhiyun greth->irq = ofdev->archdata.irqs[0];
1381*4882a593Smuzhiyun
1382*4882a593Smuzhiyun dev_set_drvdata(greth->dev, dev);
1383*4882a593Smuzhiyun SET_NETDEV_DEV(dev, greth->dev);
1384*4882a593Smuzhiyun
1385*4882a593Smuzhiyun if (netif_msg_probe(greth))
1386*4882a593Smuzhiyun dev_dbg(greth->dev, "resetting controller.\n");
1387*4882a593Smuzhiyun
1388*4882a593Smuzhiyun /* Reset the controller. */
1389*4882a593Smuzhiyun GRETH_REGSAVE(regs->control, GRETH_RESET);
1390*4882a593Smuzhiyun
1391*4882a593Smuzhiyun /* Wait for MAC to reset itself */
1392*4882a593Smuzhiyun timeout = jiffies + HZ/100;
1393*4882a593Smuzhiyun while (GRETH_REGLOAD(regs->control) & GRETH_RESET) {
1394*4882a593Smuzhiyun if (time_after(jiffies, timeout)) {
1395*4882a593Smuzhiyun err = -EIO;
1396*4882a593Smuzhiyun if (netif_msg_probe(greth))
1397*4882a593Smuzhiyun dev_err(greth->dev, "timeout when waiting for reset.\n");
1398*4882a593Smuzhiyun goto error2;
1399*4882a593Smuzhiyun }
1400*4882a593Smuzhiyun }
1401*4882a593Smuzhiyun
1402*4882a593Smuzhiyun /* Get default PHY address */
1403*4882a593Smuzhiyun greth->phyaddr = (GRETH_REGLOAD(regs->mdio) >> 11) & 0x1F;
1404*4882a593Smuzhiyun
1405*4882a593Smuzhiyun /* Check if we have GBIT capable MAC */
1406*4882a593Smuzhiyun tmp = GRETH_REGLOAD(regs->control);
1407*4882a593Smuzhiyun greth->gbit_mac = (tmp >> 27) & 1;
1408*4882a593Smuzhiyun
1409*4882a593Smuzhiyun /* Check for multicast capability */
1410*4882a593Smuzhiyun greth->multicast = (tmp >> 25) & 1;
1411*4882a593Smuzhiyun
1412*4882a593Smuzhiyun greth->edcl = (tmp >> 31) & 1;
1413*4882a593Smuzhiyun
1414*4882a593Smuzhiyun /* If we have EDCL we disable the EDCL speed-duplex FSM so
1415*4882a593Smuzhiyun * it doesn't interfere with the software */
1416*4882a593Smuzhiyun if (greth->edcl != 0)
1417*4882a593Smuzhiyun GRETH_REGORIN(regs->control, GRETH_CTRL_DISDUPLEX);
1418*4882a593Smuzhiyun
1419*4882a593Smuzhiyun /* Check if MAC can handle MDIO interrupts */
1420*4882a593Smuzhiyun greth->mdio_int_en = (tmp >> 26) & 1;
1421*4882a593Smuzhiyun
1422*4882a593Smuzhiyun err = greth_mdio_init(greth);
1423*4882a593Smuzhiyun if (err) {
1424*4882a593Smuzhiyun if (netif_msg_probe(greth))
1425*4882a593Smuzhiyun dev_err(greth->dev, "failed to register MDIO bus\n");
1426*4882a593Smuzhiyun goto error2;
1427*4882a593Smuzhiyun }
1428*4882a593Smuzhiyun
1429*4882a593Smuzhiyun /* Allocate TX descriptor ring in coherent memory */
1430*4882a593Smuzhiyun greth->tx_bd_base = dma_alloc_coherent(greth->dev, 1024,
1431*4882a593Smuzhiyun &greth->tx_bd_base_phys,
1432*4882a593Smuzhiyun GFP_KERNEL);
1433*4882a593Smuzhiyun if (!greth->tx_bd_base) {
1434*4882a593Smuzhiyun err = -ENOMEM;
1435*4882a593Smuzhiyun goto error3;
1436*4882a593Smuzhiyun }
1437*4882a593Smuzhiyun
1438*4882a593Smuzhiyun /* Allocate RX descriptor ring in coherent memory */
1439*4882a593Smuzhiyun greth->rx_bd_base = dma_alloc_coherent(greth->dev, 1024,
1440*4882a593Smuzhiyun &greth->rx_bd_base_phys,
1441*4882a593Smuzhiyun GFP_KERNEL);
1442*4882a593Smuzhiyun if (!greth->rx_bd_base) {
1443*4882a593Smuzhiyun err = -ENOMEM;
1444*4882a593Smuzhiyun goto error4;
1445*4882a593Smuzhiyun }
1446*4882a593Smuzhiyun
1447*4882a593Smuzhiyun /* Get MAC address from: module param, OF property or ID prom */
1448*4882a593Smuzhiyun for (i = 0; i < 6; i++) {
1449*4882a593Smuzhiyun if (macaddr[i] != 0)
1450*4882a593Smuzhiyun break;
1451*4882a593Smuzhiyun }
1452*4882a593Smuzhiyun if (i == 6) {
1453*4882a593Smuzhiyun const u8 *addr;
1454*4882a593Smuzhiyun
1455*4882a593Smuzhiyun addr = of_get_mac_address(ofdev->dev.of_node);
1456*4882a593Smuzhiyun if (!IS_ERR(addr)) {
1457*4882a593Smuzhiyun for (i = 0; i < 6; i++)
1458*4882a593Smuzhiyun macaddr[i] = (unsigned int) addr[i];
1459*4882a593Smuzhiyun } else {
1460*4882a593Smuzhiyun #ifdef CONFIG_SPARC
1461*4882a593Smuzhiyun for (i = 0; i < 6; i++)
1462*4882a593Smuzhiyun macaddr[i] = (unsigned int) idprom->id_ethaddr[i];
1463*4882a593Smuzhiyun #endif
1464*4882a593Smuzhiyun }
1465*4882a593Smuzhiyun }
1466*4882a593Smuzhiyun
1467*4882a593Smuzhiyun for (i = 0; i < 6; i++)
1468*4882a593Smuzhiyun dev->dev_addr[i] = macaddr[i];
1469*4882a593Smuzhiyun
1470*4882a593Smuzhiyun macaddr[5]++;
1471*4882a593Smuzhiyun
1472*4882a593Smuzhiyun if (!is_valid_ether_addr(&dev->dev_addr[0])) {
1473*4882a593Smuzhiyun if (netif_msg_probe(greth))
1474*4882a593Smuzhiyun dev_err(greth->dev, "no valid ethernet address, aborting.\n");
1475*4882a593Smuzhiyun err = -EINVAL;
1476*4882a593Smuzhiyun goto error5;
1477*4882a593Smuzhiyun }
1478*4882a593Smuzhiyun
1479*4882a593Smuzhiyun GRETH_REGSAVE(regs->esa_msb, dev->dev_addr[0] << 8 | dev->dev_addr[1]);
1480*4882a593Smuzhiyun GRETH_REGSAVE(regs->esa_lsb, dev->dev_addr[2] << 24 | dev->dev_addr[3] << 16 |
1481*4882a593Smuzhiyun dev->dev_addr[4] << 8 | dev->dev_addr[5]);
1482*4882a593Smuzhiyun
1483*4882a593Smuzhiyun /* Clear all pending interrupts except PHY irq */
1484*4882a593Smuzhiyun GRETH_REGSAVE(regs->status, 0xFF);
1485*4882a593Smuzhiyun
1486*4882a593Smuzhiyun if (greth->gbit_mac) {
1487*4882a593Smuzhiyun dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
1488*4882a593Smuzhiyun NETIF_F_RXCSUM;
1489*4882a593Smuzhiyun dev->features = dev->hw_features | NETIF_F_HIGHDMA;
1490*4882a593Smuzhiyun greth_netdev_ops.ndo_start_xmit = greth_start_xmit_gbit;
1491*4882a593Smuzhiyun }
1492*4882a593Smuzhiyun
1493*4882a593Smuzhiyun if (greth->multicast) {
1494*4882a593Smuzhiyun greth_netdev_ops.ndo_set_rx_mode = greth_set_multicast_list;
1495*4882a593Smuzhiyun dev->flags |= IFF_MULTICAST;
1496*4882a593Smuzhiyun } else {
1497*4882a593Smuzhiyun dev->flags &= ~IFF_MULTICAST;
1498*4882a593Smuzhiyun }
1499*4882a593Smuzhiyun
1500*4882a593Smuzhiyun dev->netdev_ops = &greth_netdev_ops;
1501*4882a593Smuzhiyun dev->ethtool_ops = &greth_ethtool_ops;
1502*4882a593Smuzhiyun
1503*4882a593Smuzhiyun err = register_netdev(dev);
1504*4882a593Smuzhiyun if (err) {
1505*4882a593Smuzhiyun if (netif_msg_probe(greth))
1506*4882a593Smuzhiyun dev_err(greth->dev, "netdevice registration failed.\n");
1507*4882a593Smuzhiyun goto error5;
1508*4882a593Smuzhiyun }
1509*4882a593Smuzhiyun
1510*4882a593Smuzhiyun /* setup NAPI */
1511*4882a593Smuzhiyun netif_napi_add(dev, &greth->napi, greth_poll, 64);
1512*4882a593Smuzhiyun
1513*4882a593Smuzhiyun return 0;
1514*4882a593Smuzhiyun
1515*4882a593Smuzhiyun error5:
1516*4882a593Smuzhiyun dma_free_coherent(greth->dev, 1024, greth->rx_bd_base, greth->rx_bd_base_phys);
1517*4882a593Smuzhiyun error4:
1518*4882a593Smuzhiyun dma_free_coherent(greth->dev, 1024, greth->tx_bd_base, greth->tx_bd_base_phys);
1519*4882a593Smuzhiyun error3:
1520*4882a593Smuzhiyun mdiobus_unregister(greth->mdio);
1521*4882a593Smuzhiyun error2:
1522*4882a593Smuzhiyun of_iounmap(&ofdev->resource[0], greth->regs, resource_size(&ofdev->resource[0]));
1523*4882a593Smuzhiyun error1:
1524*4882a593Smuzhiyun free_netdev(dev);
1525*4882a593Smuzhiyun return err;
1526*4882a593Smuzhiyun }
1527*4882a593Smuzhiyun
greth_of_remove(struct platform_device * of_dev)1528*4882a593Smuzhiyun static int greth_of_remove(struct platform_device *of_dev)
1529*4882a593Smuzhiyun {
1530*4882a593Smuzhiyun struct net_device *ndev = platform_get_drvdata(of_dev);
1531*4882a593Smuzhiyun struct greth_private *greth = netdev_priv(ndev);
1532*4882a593Smuzhiyun
1533*4882a593Smuzhiyun /* Free descriptor areas */
1534*4882a593Smuzhiyun dma_free_coherent(&of_dev->dev, 1024, greth->rx_bd_base, greth->rx_bd_base_phys);
1535*4882a593Smuzhiyun
1536*4882a593Smuzhiyun dma_free_coherent(&of_dev->dev, 1024, greth->tx_bd_base, greth->tx_bd_base_phys);
1537*4882a593Smuzhiyun
1538*4882a593Smuzhiyun if (ndev->phydev)
1539*4882a593Smuzhiyun phy_stop(ndev->phydev);
1540*4882a593Smuzhiyun mdiobus_unregister(greth->mdio);
1541*4882a593Smuzhiyun
1542*4882a593Smuzhiyun unregister_netdev(ndev);
1543*4882a593Smuzhiyun
1544*4882a593Smuzhiyun of_iounmap(&of_dev->resource[0], greth->regs, resource_size(&of_dev->resource[0]));
1545*4882a593Smuzhiyun
1546*4882a593Smuzhiyun free_netdev(ndev);
1547*4882a593Smuzhiyun
1548*4882a593Smuzhiyun return 0;
1549*4882a593Smuzhiyun }
1550*4882a593Smuzhiyun
1551*4882a593Smuzhiyun static const struct of_device_id greth_of_match[] = {
1552*4882a593Smuzhiyun {
1553*4882a593Smuzhiyun .name = "GAISLER_ETHMAC",
1554*4882a593Smuzhiyun },
1555*4882a593Smuzhiyun {
1556*4882a593Smuzhiyun .name = "01_01d",
1557*4882a593Smuzhiyun },
1558*4882a593Smuzhiyun {},
1559*4882a593Smuzhiyun };
1560*4882a593Smuzhiyun
1561*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, greth_of_match);
1562*4882a593Smuzhiyun
1563*4882a593Smuzhiyun static struct platform_driver greth_of_driver = {
1564*4882a593Smuzhiyun .driver = {
1565*4882a593Smuzhiyun .name = "grlib-greth",
1566*4882a593Smuzhiyun .of_match_table = greth_of_match,
1567*4882a593Smuzhiyun },
1568*4882a593Smuzhiyun .probe = greth_of_probe,
1569*4882a593Smuzhiyun .remove = greth_of_remove,
1570*4882a593Smuzhiyun };
1571*4882a593Smuzhiyun
1572*4882a593Smuzhiyun module_platform_driver(greth_of_driver);
1573*4882a593Smuzhiyun
1574*4882a593Smuzhiyun MODULE_AUTHOR("Aeroflex Gaisler AB.");
1575*4882a593Smuzhiyun MODULE_DESCRIPTION("Aeroflex Gaisler Ethernet MAC driver");
1576*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1577