1*4882a593Smuzhiyun /* 3c574.c: A PCMCIA ethernet driver for the 3com 3c574 "RoadRunner".
2*4882a593Smuzhiyun
3*4882a593Smuzhiyun Written 1993-1998 by
4*4882a593Smuzhiyun Donald Becker, becker@scyld.com, (driver core) and
5*4882a593Smuzhiyun David Hinds, dahinds@users.sourceforge.net (from his PC card code).
6*4882a593Smuzhiyun Locking fixes (C) Copyright 2003 Red Hat Inc
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun This software may be used and distributed according to the terms of
9*4882a593Smuzhiyun the GNU General Public License, incorporated herein by reference.
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun This driver derives from Donald Becker's 3c509 core, which has the
12*4882a593Smuzhiyun following copyright:
13*4882a593Smuzhiyun Copyright 1993 United States Government as represented by the
14*4882a593Smuzhiyun Director, National Security Agency.
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun */
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /*
20*4882a593Smuzhiyun Theory of Operation
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun I. Board Compatibility
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun This device driver is designed for the 3Com 3c574 PC card Fast Ethernet
25*4882a593Smuzhiyun Adapter.
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun II. Board-specific settings
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun None -- PC cards are autoconfigured.
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun III. Driver operation
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun The 3c574 uses a Boomerang-style interface, without the bus-master capability.
34*4882a593Smuzhiyun See the Boomerang driver and documentation for most details.
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun IV. Notes and chip documentation.
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun Two added registers are used to enhance PIO performance, RunnerRdCtrl and
39*4882a593Smuzhiyun RunnerWrCtrl. These are 11 bit down-counters that are preloaded with the
40*4882a593Smuzhiyun count of word (16 bits) reads or writes the driver is about to do to the Rx
41*4882a593Smuzhiyun or Tx FIFO. The chip is then able to hide the internal-PCI-bus to PC-card
42*4882a593Smuzhiyun translation latency by buffering the I/O operations with an 8 word FIFO.
43*4882a593Smuzhiyun Note: No other chip accesses are permitted when this buffer is used.
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun A second enhancement is that both attribute and common memory space
46*4882a593Smuzhiyun 0x0800-0x0fff can translated to the PIO FIFO. Thus memory operations (faster
47*4882a593Smuzhiyun with *some* PCcard bridges) may be used instead of I/O operations.
48*4882a593Smuzhiyun This is enabled by setting the 0x10 bit in the PCMCIA LAN COR.
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun Some slow PC card bridges work better if they never see a WAIT signal.
51*4882a593Smuzhiyun This is configured by setting the 0x20 bit in the PCMCIA LAN COR.
52*4882a593Smuzhiyun Only do this after testing that it is reliable and improves performance.
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun The upper five bits of RunnerRdCtrl are used to window into PCcard
55*4882a593Smuzhiyun configuration space registers. Window 0 is the regular Boomerang/Odie
56*4882a593Smuzhiyun register set, 1-5 are various PC card control registers, and 16-31 are
57*4882a593Smuzhiyun the (reversed!) CIS table.
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun A final note: writing the InternalConfig register in window 3 with an
60*4882a593Smuzhiyun invalid ramWidth is Very Bad.
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun V. References
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun http://www.scyld.com/expert/NWay.html
65*4882a593Smuzhiyun http://www.national.com/opf/DP/DP83840A.html
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun Thanks to Terry Murphy of 3Com for providing development information for
68*4882a593Smuzhiyun earlier 3Com products.
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun */
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun #include <linux/module.h>
75*4882a593Smuzhiyun #include <linux/kernel.h>
76*4882a593Smuzhiyun #include <linux/slab.h>
77*4882a593Smuzhiyun #include <linux/string.h>
78*4882a593Smuzhiyun #include <linux/timer.h>
79*4882a593Smuzhiyun #include <linux/interrupt.h>
80*4882a593Smuzhiyun #include <linux/in.h>
81*4882a593Smuzhiyun #include <linux/delay.h>
82*4882a593Smuzhiyun #include <linux/netdevice.h>
83*4882a593Smuzhiyun #include <linux/etherdevice.h>
84*4882a593Smuzhiyun #include <linux/skbuff.h>
85*4882a593Smuzhiyun #include <linux/if_arp.h>
86*4882a593Smuzhiyun #include <linux/ioport.h>
87*4882a593Smuzhiyun #include <linux/bitops.h>
88*4882a593Smuzhiyun #include <linux/mii.h>
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun #include <pcmcia/cistpl.h>
91*4882a593Smuzhiyun #include <pcmcia/cisreg.h>
92*4882a593Smuzhiyun #include <pcmcia/ciscode.h>
93*4882a593Smuzhiyun #include <pcmcia/ds.h>
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun #include <linux/uaccess.h>
96*4882a593Smuzhiyun #include <asm/io.h>
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun /*====================================================================*/
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun /* Module parameters */
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun MODULE_AUTHOR("David Hinds <dahinds@users.sourceforge.net>");
103*4882a593Smuzhiyun MODULE_DESCRIPTION("3Com 3c574 series PCMCIA ethernet driver");
104*4882a593Smuzhiyun MODULE_LICENSE("GPL");
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun #define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
109*4882a593Smuzhiyun INT_MODULE_PARM(max_interrupt_work, 32);
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* Force full duplex modes? */
112*4882a593Smuzhiyun INT_MODULE_PARM(full_duplex, 0);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* Autodetect link polarity reversal? */
115*4882a593Smuzhiyun INT_MODULE_PARM(auto_polarity, 1);
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun /*====================================================================*/
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun /* Time in jiffies before concluding the transmitter is hung. */
121*4882a593Smuzhiyun #define TX_TIMEOUT ((800*HZ)/1000)
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun /* To minimize the size of the driver source and make the driver more
124*4882a593Smuzhiyun readable not all constants are symbolically defined.
125*4882a593Smuzhiyun You'll need the manual if you want to understand driver details anyway. */
126*4882a593Smuzhiyun /* Offsets from base I/O address. */
127*4882a593Smuzhiyun #define EL3_DATA 0x00
128*4882a593Smuzhiyun #define EL3_CMD 0x0e
129*4882a593Smuzhiyun #define EL3_STATUS 0x0e
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun #define EL3WINDOW(win_num) outw(SelectWindow + (win_num), ioaddr + EL3_CMD)
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun /* The top five bits written to EL3_CMD are a command, the lower
134*4882a593Smuzhiyun 11 bits are the parameter, if applicable. */
135*4882a593Smuzhiyun enum el3_cmds {
136*4882a593Smuzhiyun TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
137*4882a593Smuzhiyun RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11, RxDiscard = 8<<11,
138*4882a593Smuzhiyun TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
139*4882a593Smuzhiyun FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
140*4882a593Smuzhiyun SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
141*4882a593Smuzhiyun SetTxThreshold = 18<<11, SetTxStart = 19<<11, StatsEnable = 21<<11,
142*4882a593Smuzhiyun StatsDisable = 22<<11, StopCoax = 23<<11,
143*4882a593Smuzhiyun };
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun enum elxl_status {
146*4882a593Smuzhiyun IntLatch = 0x0001, AdapterFailure = 0x0002, TxComplete = 0x0004,
147*4882a593Smuzhiyun TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
148*4882a593Smuzhiyun IntReq = 0x0040, StatsFull = 0x0080, CmdBusy = 0x1000 };
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun /* The SetRxFilter command accepts the following classes: */
151*4882a593Smuzhiyun enum RxFilter {
152*4882a593Smuzhiyun RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8
153*4882a593Smuzhiyun };
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun enum Window0 {
156*4882a593Smuzhiyun Wn0EepromCmd = 10, Wn0EepromData = 12, /* EEPROM command/address, data. */
157*4882a593Smuzhiyun IntrStatus=0x0E, /* Valid in all windows. */
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun /* These assumes the larger EEPROM. */
160*4882a593Smuzhiyun enum Win0_EEPROM_cmds {
161*4882a593Smuzhiyun EEPROM_Read = 0x200, EEPROM_WRITE = 0x100, EEPROM_ERASE = 0x300,
162*4882a593Smuzhiyun EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
163*4882a593Smuzhiyun EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
164*4882a593Smuzhiyun };
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun /* Register window 1 offsets, the window used in normal operation.
167*4882a593Smuzhiyun On the "Odie" this window is always mapped at offsets 0x10-0x1f.
168*4882a593Smuzhiyun Except for TxFree, which is overlapped by RunnerWrCtrl. */
169*4882a593Smuzhiyun enum Window1 {
170*4882a593Smuzhiyun TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
171*4882a593Smuzhiyun RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
172*4882a593Smuzhiyun TxFree = 0x0C, /* Remaining free bytes in Tx buffer. */
173*4882a593Smuzhiyun RunnerRdCtrl = 0x16, RunnerWrCtrl = 0x1c,
174*4882a593Smuzhiyun };
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun enum Window3 { /* Window 3: MAC/config bits. */
177*4882a593Smuzhiyun Wn3_Config=0, Wn3_MAC_Ctrl=6, Wn3_Options=8,
178*4882a593Smuzhiyun };
179*4882a593Smuzhiyun enum wn3_config {
180*4882a593Smuzhiyun Ram_size = 7,
181*4882a593Smuzhiyun Ram_width = 8,
182*4882a593Smuzhiyun Ram_speed = 0x30,
183*4882a593Smuzhiyun Rom_size = 0xc0,
184*4882a593Smuzhiyun Ram_split_shift = 16,
185*4882a593Smuzhiyun Ram_split = 3 << Ram_split_shift,
186*4882a593Smuzhiyun Xcvr_shift = 20,
187*4882a593Smuzhiyun Xcvr = 7 << Xcvr_shift,
188*4882a593Smuzhiyun Autoselect = 0x1000000,
189*4882a593Smuzhiyun };
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun enum Window4 { /* Window 4: Xcvr/media bits. */
192*4882a593Smuzhiyun Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
193*4882a593Smuzhiyun };
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun #define MEDIA_TP 0x00C0 /* Enable link beat and jabber for 10baseT. */
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun struct el3_private {
198*4882a593Smuzhiyun struct pcmcia_device *p_dev;
199*4882a593Smuzhiyun u16 advertising, partner; /* NWay media advertisement */
200*4882a593Smuzhiyun unsigned char phys; /* MII device address */
201*4882a593Smuzhiyun unsigned int autoselect:1, default_media:3; /* Read from the EEPROM/Wn3_Config. */
202*4882a593Smuzhiyun /* for transceiver monitoring */
203*4882a593Smuzhiyun struct timer_list media;
204*4882a593Smuzhiyun unsigned short media_status;
205*4882a593Smuzhiyun unsigned short fast_poll;
206*4882a593Smuzhiyun unsigned long last_irq;
207*4882a593Smuzhiyun spinlock_t window_lock; /* Guards the Window selection */
208*4882a593Smuzhiyun };
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun /* Set iff a MII transceiver on any interface requires mdio preamble.
211*4882a593Smuzhiyun This only set with the original DP83840 on older 3c905 boards, so the extra
212*4882a593Smuzhiyun code size of a per-interface flag is not worthwhile. */
213*4882a593Smuzhiyun static char mii_preamble_required = 0;
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun /* Index of functions. */
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun static int tc574_config(struct pcmcia_device *link);
218*4882a593Smuzhiyun static void tc574_release(struct pcmcia_device *link);
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun static void mdio_sync(unsigned int ioaddr, int bits);
221*4882a593Smuzhiyun static int mdio_read(unsigned int ioaddr, int phy_id, int location);
222*4882a593Smuzhiyun static void mdio_write(unsigned int ioaddr, int phy_id, int location,
223*4882a593Smuzhiyun int value);
224*4882a593Smuzhiyun static unsigned short read_eeprom(unsigned int ioaddr, int index);
225*4882a593Smuzhiyun static void tc574_wait_for_completion(struct net_device *dev, int cmd);
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun static void tc574_reset(struct net_device *dev);
228*4882a593Smuzhiyun static void media_check(struct timer_list *t);
229*4882a593Smuzhiyun static int el3_open(struct net_device *dev);
230*4882a593Smuzhiyun static netdev_tx_t el3_start_xmit(struct sk_buff *skb,
231*4882a593Smuzhiyun struct net_device *dev);
232*4882a593Smuzhiyun static irqreturn_t el3_interrupt(int irq, void *dev_id);
233*4882a593Smuzhiyun static void update_stats(struct net_device *dev);
234*4882a593Smuzhiyun static struct net_device_stats *el3_get_stats(struct net_device *dev);
235*4882a593Smuzhiyun static int el3_rx(struct net_device *dev, int worklimit);
236*4882a593Smuzhiyun static int el3_close(struct net_device *dev);
237*4882a593Smuzhiyun static void el3_tx_timeout(struct net_device *dev, unsigned int txqueue);
238*4882a593Smuzhiyun static int el3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
239*4882a593Smuzhiyun static void set_rx_mode(struct net_device *dev);
240*4882a593Smuzhiyun static void set_multicast_list(struct net_device *dev);
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun static void tc574_detach(struct pcmcia_device *p_dev);
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun /*
245*4882a593Smuzhiyun tc574_attach() creates an "instance" of the driver, allocating
246*4882a593Smuzhiyun local data structures for one device. The device is registered
247*4882a593Smuzhiyun with Card Services.
248*4882a593Smuzhiyun */
249*4882a593Smuzhiyun static const struct net_device_ops el3_netdev_ops = {
250*4882a593Smuzhiyun .ndo_open = el3_open,
251*4882a593Smuzhiyun .ndo_stop = el3_close,
252*4882a593Smuzhiyun .ndo_start_xmit = el3_start_xmit,
253*4882a593Smuzhiyun .ndo_tx_timeout = el3_tx_timeout,
254*4882a593Smuzhiyun .ndo_get_stats = el3_get_stats,
255*4882a593Smuzhiyun .ndo_do_ioctl = el3_ioctl,
256*4882a593Smuzhiyun .ndo_set_rx_mode = set_multicast_list,
257*4882a593Smuzhiyun .ndo_set_mac_address = eth_mac_addr,
258*4882a593Smuzhiyun .ndo_validate_addr = eth_validate_addr,
259*4882a593Smuzhiyun };
260*4882a593Smuzhiyun
tc574_probe(struct pcmcia_device * link)261*4882a593Smuzhiyun static int tc574_probe(struct pcmcia_device *link)
262*4882a593Smuzhiyun {
263*4882a593Smuzhiyun struct el3_private *lp;
264*4882a593Smuzhiyun struct net_device *dev;
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun dev_dbg(&link->dev, "3c574_attach()\n");
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun /* Create the PC card device object. */
269*4882a593Smuzhiyun dev = alloc_etherdev(sizeof(struct el3_private));
270*4882a593Smuzhiyun if (!dev)
271*4882a593Smuzhiyun return -ENOMEM;
272*4882a593Smuzhiyun lp = netdev_priv(dev);
273*4882a593Smuzhiyun link->priv = dev;
274*4882a593Smuzhiyun lp->p_dev = link;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun spin_lock_init(&lp->window_lock);
277*4882a593Smuzhiyun link->resource[0]->end = 32;
278*4882a593Smuzhiyun link->resource[0]->flags |= IO_DATA_PATH_WIDTH_16;
279*4882a593Smuzhiyun link->config_flags |= CONF_ENABLE_IRQ;
280*4882a593Smuzhiyun link->config_index = 1;
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun dev->netdev_ops = &el3_netdev_ops;
283*4882a593Smuzhiyun dev->watchdog_timeo = TX_TIMEOUT;
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun return tc574_config(link);
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun
tc574_detach(struct pcmcia_device * link)288*4882a593Smuzhiyun static void tc574_detach(struct pcmcia_device *link)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun struct net_device *dev = link->priv;
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun dev_dbg(&link->dev, "3c574_detach()\n");
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun unregister_netdev(dev);
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun tc574_release(link);
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun free_netdev(dev);
299*4882a593Smuzhiyun } /* tc574_detach */
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun static const char *ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
302*4882a593Smuzhiyun
tc574_config(struct pcmcia_device * link)303*4882a593Smuzhiyun static int tc574_config(struct pcmcia_device *link)
304*4882a593Smuzhiyun {
305*4882a593Smuzhiyun struct net_device *dev = link->priv;
306*4882a593Smuzhiyun struct el3_private *lp = netdev_priv(dev);
307*4882a593Smuzhiyun int ret, i, j;
308*4882a593Smuzhiyun unsigned int ioaddr;
309*4882a593Smuzhiyun __be16 *phys_addr;
310*4882a593Smuzhiyun char *cardname;
311*4882a593Smuzhiyun __u32 config;
312*4882a593Smuzhiyun u8 *buf;
313*4882a593Smuzhiyun size_t len;
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun phys_addr = (__be16 *)dev->dev_addr;
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun dev_dbg(&link->dev, "3c574_config()\n");
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun link->io_lines = 16;
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun for (i = j = 0; j < 0x400; j += 0x20) {
322*4882a593Smuzhiyun link->resource[0]->start = j ^ 0x300;
323*4882a593Smuzhiyun i = pcmcia_request_io(link);
324*4882a593Smuzhiyun if (i == 0)
325*4882a593Smuzhiyun break;
326*4882a593Smuzhiyun }
327*4882a593Smuzhiyun if (i != 0)
328*4882a593Smuzhiyun goto failed;
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun ret = pcmcia_request_irq(link, el3_interrupt);
331*4882a593Smuzhiyun if (ret)
332*4882a593Smuzhiyun goto failed;
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun ret = pcmcia_enable_device(link);
335*4882a593Smuzhiyun if (ret)
336*4882a593Smuzhiyun goto failed;
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun dev->irq = link->irq;
339*4882a593Smuzhiyun dev->base_addr = link->resource[0]->start;
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun ioaddr = dev->base_addr;
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun /* The 3c574 normally uses an EEPROM for configuration info, including
344*4882a593Smuzhiyun the hardware address. The future products may include a modem chip
345*4882a593Smuzhiyun and put the address in the CIS. */
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun len = pcmcia_get_tuple(link, 0x88, &buf);
348*4882a593Smuzhiyun if (buf && len >= 6) {
349*4882a593Smuzhiyun for (i = 0; i < 3; i++)
350*4882a593Smuzhiyun phys_addr[i] = htons(le16_to_cpu(buf[i * 2]));
351*4882a593Smuzhiyun kfree(buf);
352*4882a593Smuzhiyun } else {
353*4882a593Smuzhiyun kfree(buf); /* 0 < len < 6 */
354*4882a593Smuzhiyun EL3WINDOW(0);
355*4882a593Smuzhiyun for (i = 0; i < 3; i++)
356*4882a593Smuzhiyun phys_addr[i] = htons(read_eeprom(ioaddr, i + 10));
357*4882a593Smuzhiyun if (phys_addr[0] == htons(0x6060)) {
358*4882a593Smuzhiyun pr_notice("IO port conflict at 0x%03lx-0x%03lx\n",
359*4882a593Smuzhiyun dev->base_addr, dev->base_addr+15);
360*4882a593Smuzhiyun goto failed;
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun if (link->prod_id[1])
364*4882a593Smuzhiyun cardname = link->prod_id[1];
365*4882a593Smuzhiyun else
366*4882a593Smuzhiyun cardname = "3Com 3c574";
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun {
369*4882a593Smuzhiyun u_char mcr;
370*4882a593Smuzhiyun outw(2<<11, ioaddr + RunnerRdCtrl);
371*4882a593Smuzhiyun mcr = inb(ioaddr + 2);
372*4882a593Smuzhiyun outw(0<<11, ioaddr + RunnerRdCtrl);
373*4882a593Smuzhiyun pr_info(" ASIC rev %d,", mcr>>3);
374*4882a593Smuzhiyun EL3WINDOW(3);
375*4882a593Smuzhiyun config = inl(ioaddr + Wn3_Config);
376*4882a593Smuzhiyun lp->default_media = (config & Xcvr) >> Xcvr_shift;
377*4882a593Smuzhiyun lp->autoselect = config & Autoselect ? 1 : 0;
378*4882a593Smuzhiyun }
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun timer_setup(&lp->media, media_check, 0);
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun {
383*4882a593Smuzhiyun int phy;
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun /* Roadrunner only: Turn on the MII transceiver */
386*4882a593Smuzhiyun outw(0x8040, ioaddr + Wn3_Options);
387*4882a593Smuzhiyun mdelay(1);
388*4882a593Smuzhiyun outw(0xc040, ioaddr + Wn3_Options);
389*4882a593Smuzhiyun tc574_wait_for_completion(dev, TxReset);
390*4882a593Smuzhiyun tc574_wait_for_completion(dev, RxReset);
391*4882a593Smuzhiyun mdelay(1);
392*4882a593Smuzhiyun outw(0x8040, ioaddr + Wn3_Options);
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun EL3WINDOW(4);
395*4882a593Smuzhiyun for (phy = 1; phy <= 32; phy++) {
396*4882a593Smuzhiyun int mii_status;
397*4882a593Smuzhiyun mdio_sync(ioaddr, 32);
398*4882a593Smuzhiyun mii_status = mdio_read(ioaddr, phy & 0x1f, 1);
399*4882a593Smuzhiyun if (mii_status != 0xffff) {
400*4882a593Smuzhiyun lp->phys = phy & 0x1f;
401*4882a593Smuzhiyun dev_dbg(&link->dev, " MII transceiver at "
402*4882a593Smuzhiyun "index %d, status %x.\n",
403*4882a593Smuzhiyun phy, mii_status);
404*4882a593Smuzhiyun if ((mii_status & 0x0040) == 0)
405*4882a593Smuzhiyun mii_preamble_required = 1;
406*4882a593Smuzhiyun break;
407*4882a593Smuzhiyun }
408*4882a593Smuzhiyun }
409*4882a593Smuzhiyun if (phy > 32) {
410*4882a593Smuzhiyun pr_notice(" No MII transceivers found!\n");
411*4882a593Smuzhiyun goto failed;
412*4882a593Smuzhiyun }
413*4882a593Smuzhiyun i = mdio_read(ioaddr, lp->phys, 16) | 0x40;
414*4882a593Smuzhiyun mdio_write(ioaddr, lp->phys, 16, i);
415*4882a593Smuzhiyun lp->advertising = mdio_read(ioaddr, lp->phys, 4);
416*4882a593Smuzhiyun if (full_duplex) {
417*4882a593Smuzhiyun /* Only advertise the FD media types. */
418*4882a593Smuzhiyun lp->advertising &= ~0x02a0;
419*4882a593Smuzhiyun mdio_write(ioaddr, lp->phys, 4, lp->advertising);
420*4882a593Smuzhiyun }
421*4882a593Smuzhiyun }
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun SET_NETDEV_DEV(dev, &link->dev);
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun if (register_netdev(dev) != 0) {
426*4882a593Smuzhiyun pr_notice("register_netdev() failed\n");
427*4882a593Smuzhiyun goto failed;
428*4882a593Smuzhiyun }
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun netdev_info(dev, "%s at io %#3lx, irq %d, hw_addr %pM\n",
431*4882a593Smuzhiyun cardname, dev->base_addr, dev->irq, dev->dev_addr);
432*4882a593Smuzhiyun netdev_info(dev, " %dK FIFO split %s Rx:Tx, %sMII interface.\n",
433*4882a593Smuzhiyun 8 << (config & Ram_size),
434*4882a593Smuzhiyun ram_split[(config & Ram_split) >> Ram_split_shift],
435*4882a593Smuzhiyun config & Autoselect ? "autoselect " : "");
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun return 0;
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun failed:
440*4882a593Smuzhiyun tc574_release(link);
441*4882a593Smuzhiyun return -ENODEV;
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun } /* tc574_config */
444*4882a593Smuzhiyun
tc574_release(struct pcmcia_device * link)445*4882a593Smuzhiyun static void tc574_release(struct pcmcia_device *link)
446*4882a593Smuzhiyun {
447*4882a593Smuzhiyun pcmcia_disable_device(link);
448*4882a593Smuzhiyun }
449*4882a593Smuzhiyun
tc574_suspend(struct pcmcia_device * link)450*4882a593Smuzhiyun static int tc574_suspend(struct pcmcia_device *link)
451*4882a593Smuzhiyun {
452*4882a593Smuzhiyun struct net_device *dev = link->priv;
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun if (link->open)
455*4882a593Smuzhiyun netif_device_detach(dev);
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun return 0;
458*4882a593Smuzhiyun }
459*4882a593Smuzhiyun
tc574_resume(struct pcmcia_device * link)460*4882a593Smuzhiyun static int tc574_resume(struct pcmcia_device *link)
461*4882a593Smuzhiyun {
462*4882a593Smuzhiyun struct net_device *dev = link->priv;
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun if (link->open) {
465*4882a593Smuzhiyun tc574_reset(dev);
466*4882a593Smuzhiyun netif_device_attach(dev);
467*4882a593Smuzhiyun }
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun return 0;
470*4882a593Smuzhiyun }
471*4882a593Smuzhiyun
dump_status(struct net_device * dev)472*4882a593Smuzhiyun static void dump_status(struct net_device *dev)
473*4882a593Smuzhiyun {
474*4882a593Smuzhiyun unsigned int ioaddr = dev->base_addr;
475*4882a593Smuzhiyun EL3WINDOW(1);
476*4882a593Smuzhiyun netdev_info(dev, " irq status %04x, rx status %04x, tx status %02x, tx free %04x\n",
477*4882a593Smuzhiyun inw(ioaddr+EL3_STATUS),
478*4882a593Smuzhiyun inw(ioaddr+RxStatus), inb(ioaddr+TxStatus),
479*4882a593Smuzhiyun inw(ioaddr+TxFree));
480*4882a593Smuzhiyun EL3WINDOW(4);
481*4882a593Smuzhiyun netdev_info(dev, " diagnostics: fifo %04x net %04x ethernet %04x media %04x\n",
482*4882a593Smuzhiyun inw(ioaddr+0x04), inw(ioaddr+0x06),
483*4882a593Smuzhiyun inw(ioaddr+0x08), inw(ioaddr+0x0a));
484*4882a593Smuzhiyun EL3WINDOW(1);
485*4882a593Smuzhiyun }
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun /*
488*4882a593Smuzhiyun Use this for commands that may take time to finish
489*4882a593Smuzhiyun */
tc574_wait_for_completion(struct net_device * dev,int cmd)490*4882a593Smuzhiyun static void tc574_wait_for_completion(struct net_device *dev, int cmd)
491*4882a593Smuzhiyun {
492*4882a593Smuzhiyun int i = 1500;
493*4882a593Smuzhiyun outw(cmd, dev->base_addr + EL3_CMD);
494*4882a593Smuzhiyun while (--i > 0)
495*4882a593Smuzhiyun if (!(inw(dev->base_addr + EL3_STATUS) & 0x1000)) break;
496*4882a593Smuzhiyun if (i == 0)
497*4882a593Smuzhiyun netdev_notice(dev, "command 0x%04x did not complete!\n", cmd);
498*4882a593Smuzhiyun }
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun /* Read a word from the EEPROM using the regular EEPROM access register.
501*4882a593Smuzhiyun Assume that we are in register window zero.
502*4882a593Smuzhiyun */
read_eeprom(unsigned int ioaddr,int index)503*4882a593Smuzhiyun static unsigned short read_eeprom(unsigned int ioaddr, int index)
504*4882a593Smuzhiyun {
505*4882a593Smuzhiyun int timer;
506*4882a593Smuzhiyun outw(EEPROM_Read + index, ioaddr + Wn0EepromCmd);
507*4882a593Smuzhiyun /* Pause for at least 162 usec for the read to take place. */
508*4882a593Smuzhiyun for (timer = 1620; timer >= 0; timer--) {
509*4882a593Smuzhiyun if ((inw(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
510*4882a593Smuzhiyun break;
511*4882a593Smuzhiyun }
512*4882a593Smuzhiyun return inw(ioaddr + Wn0EepromData);
513*4882a593Smuzhiyun }
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun /* MII transceiver control section.
516*4882a593Smuzhiyun Read and write the MII registers using software-generated serial
517*4882a593Smuzhiyun MDIO protocol. See the MII specifications or DP83840A data sheet
518*4882a593Smuzhiyun for details.
519*4882a593Smuzhiyun The maxium data clock rate is 2.5 Mhz. The timing is easily met by the
520*4882a593Smuzhiyun slow PC card interface. */
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun #define MDIO_SHIFT_CLK 0x01
523*4882a593Smuzhiyun #define MDIO_DIR_WRITE 0x04
524*4882a593Smuzhiyun #define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
525*4882a593Smuzhiyun #define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
526*4882a593Smuzhiyun #define MDIO_DATA_READ 0x02
527*4882a593Smuzhiyun #define MDIO_ENB_IN 0x00
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun /* Generate the preamble required for initial synchronization and
530*4882a593Smuzhiyun a few older transceivers. */
mdio_sync(unsigned int ioaddr,int bits)531*4882a593Smuzhiyun static void mdio_sync(unsigned int ioaddr, int bits)
532*4882a593Smuzhiyun {
533*4882a593Smuzhiyun unsigned int mdio_addr = ioaddr + Wn4_PhysicalMgmt;
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun /* Establish sync by sending at least 32 logic ones. */
536*4882a593Smuzhiyun while (-- bits >= 0) {
537*4882a593Smuzhiyun outw(MDIO_DATA_WRITE1, mdio_addr);
538*4882a593Smuzhiyun outw(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
539*4882a593Smuzhiyun }
540*4882a593Smuzhiyun }
541*4882a593Smuzhiyun
mdio_read(unsigned int ioaddr,int phy_id,int location)542*4882a593Smuzhiyun static int mdio_read(unsigned int ioaddr, int phy_id, int location)
543*4882a593Smuzhiyun {
544*4882a593Smuzhiyun int i;
545*4882a593Smuzhiyun int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
546*4882a593Smuzhiyun unsigned int retval = 0;
547*4882a593Smuzhiyun unsigned int mdio_addr = ioaddr + Wn4_PhysicalMgmt;
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun if (mii_preamble_required)
550*4882a593Smuzhiyun mdio_sync(ioaddr, 32);
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun /* Shift the read command bits out. */
553*4882a593Smuzhiyun for (i = 14; i >= 0; i--) {
554*4882a593Smuzhiyun int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
555*4882a593Smuzhiyun outw(dataval, mdio_addr);
556*4882a593Smuzhiyun outw(dataval | MDIO_SHIFT_CLK, mdio_addr);
557*4882a593Smuzhiyun }
558*4882a593Smuzhiyun /* Read the two transition, 16 data, and wire-idle bits. */
559*4882a593Smuzhiyun for (i = 19; i > 0; i--) {
560*4882a593Smuzhiyun outw(MDIO_ENB_IN, mdio_addr);
561*4882a593Smuzhiyun retval = (retval << 1) | ((inw(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
562*4882a593Smuzhiyun outw(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
563*4882a593Smuzhiyun }
564*4882a593Smuzhiyun return (retval>>1) & 0xffff;
565*4882a593Smuzhiyun }
566*4882a593Smuzhiyun
mdio_write(unsigned int ioaddr,int phy_id,int location,int value)567*4882a593Smuzhiyun static void mdio_write(unsigned int ioaddr, int phy_id, int location, int value)
568*4882a593Smuzhiyun {
569*4882a593Smuzhiyun int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
570*4882a593Smuzhiyun unsigned int mdio_addr = ioaddr + Wn4_PhysicalMgmt;
571*4882a593Smuzhiyun int i;
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun if (mii_preamble_required)
574*4882a593Smuzhiyun mdio_sync(ioaddr, 32);
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun /* Shift the command bits out. */
577*4882a593Smuzhiyun for (i = 31; i >= 0; i--) {
578*4882a593Smuzhiyun int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
579*4882a593Smuzhiyun outw(dataval, mdio_addr);
580*4882a593Smuzhiyun outw(dataval | MDIO_SHIFT_CLK, mdio_addr);
581*4882a593Smuzhiyun }
582*4882a593Smuzhiyun /* Leave the interface idle. */
583*4882a593Smuzhiyun for (i = 1; i >= 0; i--) {
584*4882a593Smuzhiyun outw(MDIO_ENB_IN, mdio_addr);
585*4882a593Smuzhiyun outw(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
586*4882a593Smuzhiyun }
587*4882a593Smuzhiyun }
588*4882a593Smuzhiyun
589*4882a593Smuzhiyun /* Reset and restore all of the 3c574 registers. */
tc574_reset(struct net_device * dev)590*4882a593Smuzhiyun static void tc574_reset(struct net_device *dev)
591*4882a593Smuzhiyun {
592*4882a593Smuzhiyun struct el3_private *lp = netdev_priv(dev);
593*4882a593Smuzhiyun int i;
594*4882a593Smuzhiyun unsigned int ioaddr = dev->base_addr;
595*4882a593Smuzhiyun unsigned long flags;
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun tc574_wait_for_completion(dev, TotalReset|0x10);
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun spin_lock_irqsave(&lp->window_lock, flags);
600*4882a593Smuzhiyun /* Clear any transactions in progress. */
601*4882a593Smuzhiyun outw(0, ioaddr + RunnerWrCtrl);
602*4882a593Smuzhiyun outw(0, ioaddr + RunnerRdCtrl);
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun /* Set the station address and mask. */
605*4882a593Smuzhiyun EL3WINDOW(2);
606*4882a593Smuzhiyun for (i = 0; i < 6; i++)
607*4882a593Smuzhiyun outb(dev->dev_addr[i], ioaddr + i);
608*4882a593Smuzhiyun for (; i < 12; i+=2)
609*4882a593Smuzhiyun outw(0, ioaddr + i);
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun /* Reset config options */
612*4882a593Smuzhiyun EL3WINDOW(3);
613*4882a593Smuzhiyun outb((dev->mtu > 1500 ? 0x40 : 0), ioaddr + Wn3_MAC_Ctrl);
614*4882a593Smuzhiyun outl((lp->autoselect ? 0x01000000 : 0) | 0x0062001b,
615*4882a593Smuzhiyun ioaddr + Wn3_Config);
616*4882a593Smuzhiyun /* Roadrunner only: Turn on the MII transceiver. */
617*4882a593Smuzhiyun outw(0x8040, ioaddr + Wn3_Options);
618*4882a593Smuzhiyun mdelay(1);
619*4882a593Smuzhiyun outw(0xc040, ioaddr + Wn3_Options);
620*4882a593Smuzhiyun EL3WINDOW(1);
621*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->window_lock, flags);
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun tc574_wait_for_completion(dev, TxReset);
624*4882a593Smuzhiyun tc574_wait_for_completion(dev, RxReset);
625*4882a593Smuzhiyun mdelay(1);
626*4882a593Smuzhiyun spin_lock_irqsave(&lp->window_lock, flags);
627*4882a593Smuzhiyun EL3WINDOW(3);
628*4882a593Smuzhiyun outw(0x8040, ioaddr + Wn3_Options);
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun /* Switch to the stats window, and clear all stats by reading. */
631*4882a593Smuzhiyun outw(StatsDisable, ioaddr + EL3_CMD);
632*4882a593Smuzhiyun EL3WINDOW(6);
633*4882a593Smuzhiyun for (i = 0; i < 10; i++)
634*4882a593Smuzhiyun inb(ioaddr + i);
635*4882a593Smuzhiyun inw(ioaddr + 10);
636*4882a593Smuzhiyun inw(ioaddr + 12);
637*4882a593Smuzhiyun EL3WINDOW(4);
638*4882a593Smuzhiyun inb(ioaddr + 12);
639*4882a593Smuzhiyun inb(ioaddr + 13);
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun /* .. enable any extra statistics bits.. */
642*4882a593Smuzhiyun outw(0x0040, ioaddr + Wn4_NetDiag);
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun EL3WINDOW(1);
645*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->window_lock, flags);
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun /* .. re-sync MII and re-fill what NWay is advertising. */
648*4882a593Smuzhiyun mdio_sync(ioaddr, 32);
649*4882a593Smuzhiyun mdio_write(ioaddr, lp->phys, 4, lp->advertising);
650*4882a593Smuzhiyun if (!auto_polarity) {
651*4882a593Smuzhiyun /* works for TDK 78Q2120 series MII's */
652*4882a593Smuzhiyun i = mdio_read(ioaddr, lp->phys, 16) | 0x20;
653*4882a593Smuzhiyun mdio_write(ioaddr, lp->phys, 16, i);
654*4882a593Smuzhiyun }
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun spin_lock_irqsave(&lp->window_lock, flags);
657*4882a593Smuzhiyun /* Switch to register set 1 for normal use, just for TxFree. */
658*4882a593Smuzhiyun set_rx_mode(dev);
659*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->window_lock, flags);
660*4882a593Smuzhiyun outw(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
661*4882a593Smuzhiyun outw(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
662*4882a593Smuzhiyun outw(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
663*4882a593Smuzhiyun /* Allow status bits to be seen. */
664*4882a593Smuzhiyun outw(SetStatusEnb | 0xff, ioaddr + EL3_CMD);
665*4882a593Smuzhiyun /* Ack all pending events, and set active indicator mask. */
666*4882a593Smuzhiyun outw(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
667*4882a593Smuzhiyun ioaddr + EL3_CMD);
668*4882a593Smuzhiyun outw(SetIntrEnb | IntLatch | TxAvailable | RxComplete | StatsFull
669*4882a593Smuzhiyun | AdapterFailure | RxEarly, ioaddr + EL3_CMD);
670*4882a593Smuzhiyun }
671*4882a593Smuzhiyun
el3_open(struct net_device * dev)672*4882a593Smuzhiyun static int el3_open(struct net_device *dev)
673*4882a593Smuzhiyun {
674*4882a593Smuzhiyun struct el3_private *lp = netdev_priv(dev);
675*4882a593Smuzhiyun struct pcmcia_device *link = lp->p_dev;
676*4882a593Smuzhiyun
677*4882a593Smuzhiyun if (!pcmcia_dev_present(link))
678*4882a593Smuzhiyun return -ENODEV;
679*4882a593Smuzhiyun
680*4882a593Smuzhiyun link->open++;
681*4882a593Smuzhiyun netif_start_queue(dev);
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun tc574_reset(dev);
684*4882a593Smuzhiyun lp->media.expires = jiffies + HZ;
685*4882a593Smuzhiyun add_timer(&lp->media);
686*4882a593Smuzhiyun
687*4882a593Smuzhiyun dev_dbg(&link->dev, "%s: opened, status %4.4x.\n",
688*4882a593Smuzhiyun dev->name, inw(dev->base_addr + EL3_STATUS));
689*4882a593Smuzhiyun
690*4882a593Smuzhiyun return 0;
691*4882a593Smuzhiyun }
692*4882a593Smuzhiyun
el3_tx_timeout(struct net_device * dev,unsigned int txqueue)693*4882a593Smuzhiyun static void el3_tx_timeout(struct net_device *dev, unsigned int txqueue)
694*4882a593Smuzhiyun {
695*4882a593Smuzhiyun unsigned int ioaddr = dev->base_addr;
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun netdev_notice(dev, "Transmit timed out!\n");
698*4882a593Smuzhiyun dump_status(dev);
699*4882a593Smuzhiyun dev->stats.tx_errors++;
700*4882a593Smuzhiyun netif_trans_update(dev); /* prevent tx timeout */
701*4882a593Smuzhiyun /* Issue TX_RESET and TX_START commands. */
702*4882a593Smuzhiyun tc574_wait_for_completion(dev, TxReset);
703*4882a593Smuzhiyun outw(TxEnable, ioaddr + EL3_CMD);
704*4882a593Smuzhiyun netif_wake_queue(dev);
705*4882a593Smuzhiyun }
706*4882a593Smuzhiyun
pop_tx_status(struct net_device * dev)707*4882a593Smuzhiyun static void pop_tx_status(struct net_device *dev)
708*4882a593Smuzhiyun {
709*4882a593Smuzhiyun unsigned int ioaddr = dev->base_addr;
710*4882a593Smuzhiyun int i;
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun /* Clear the Tx status stack. */
713*4882a593Smuzhiyun for (i = 32; i > 0; i--) {
714*4882a593Smuzhiyun u_char tx_status = inb(ioaddr + TxStatus);
715*4882a593Smuzhiyun if (!(tx_status & 0x84))
716*4882a593Smuzhiyun break;
717*4882a593Smuzhiyun /* reset transmitter on jabber error or underrun */
718*4882a593Smuzhiyun if (tx_status & 0x30)
719*4882a593Smuzhiyun tc574_wait_for_completion(dev, TxReset);
720*4882a593Smuzhiyun if (tx_status & 0x38) {
721*4882a593Smuzhiyun pr_debug("%s: transmit error: status 0x%02x\n",
722*4882a593Smuzhiyun dev->name, tx_status);
723*4882a593Smuzhiyun outw(TxEnable, ioaddr + EL3_CMD);
724*4882a593Smuzhiyun dev->stats.tx_aborted_errors++;
725*4882a593Smuzhiyun }
726*4882a593Smuzhiyun outb(0x00, ioaddr + TxStatus); /* Pop the status stack. */
727*4882a593Smuzhiyun }
728*4882a593Smuzhiyun }
729*4882a593Smuzhiyun
el3_start_xmit(struct sk_buff * skb,struct net_device * dev)730*4882a593Smuzhiyun static netdev_tx_t el3_start_xmit(struct sk_buff *skb,
731*4882a593Smuzhiyun struct net_device *dev)
732*4882a593Smuzhiyun {
733*4882a593Smuzhiyun unsigned int ioaddr = dev->base_addr;
734*4882a593Smuzhiyun struct el3_private *lp = netdev_priv(dev);
735*4882a593Smuzhiyun unsigned long flags;
736*4882a593Smuzhiyun
737*4882a593Smuzhiyun pr_debug("%s: el3_start_xmit(length = %ld) called, "
738*4882a593Smuzhiyun "status %4.4x.\n", dev->name, (long)skb->len,
739*4882a593Smuzhiyun inw(ioaddr + EL3_STATUS));
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun spin_lock_irqsave(&lp->window_lock, flags);
742*4882a593Smuzhiyun
743*4882a593Smuzhiyun dev->stats.tx_bytes += skb->len;
744*4882a593Smuzhiyun
745*4882a593Smuzhiyun /* Put out the doubleword header... */
746*4882a593Smuzhiyun outw(skb->len, ioaddr + TX_FIFO);
747*4882a593Smuzhiyun outw(0, ioaddr + TX_FIFO);
748*4882a593Smuzhiyun /* ... and the packet rounded to a doubleword. */
749*4882a593Smuzhiyun outsl(ioaddr + TX_FIFO, skb->data, (skb->len+3)>>2);
750*4882a593Smuzhiyun
751*4882a593Smuzhiyun /* TxFree appears only in Window 1, not offset 0x1c. */
752*4882a593Smuzhiyun if (inw(ioaddr + TxFree) <= 1536) {
753*4882a593Smuzhiyun netif_stop_queue(dev);
754*4882a593Smuzhiyun /* Interrupt us when the FIFO has room for max-sized packet.
755*4882a593Smuzhiyun The threshold is in units of dwords. */
756*4882a593Smuzhiyun outw(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
757*4882a593Smuzhiyun }
758*4882a593Smuzhiyun
759*4882a593Smuzhiyun pop_tx_status(dev);
760*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->window_lock, flags);
761*4882a593Smuzhiyun dev_kfree_skb(skb);
762*4882a593Smuzhiyun return NETDEV_TX_OK;
763*4882a593Smuzhiyun }
764*4882a593Smuzhiyun
765*4882a593Smuzhiyun /* The EL3 interrupt handler. */
el3_interrupt(int irq,void * dev_id)766*4882a593Smuzhiyun static irqreturn_t el3_interrupt(int irq, void *dev_id)
767*4882a593Smuzhiyun {
768*4882a593Smuzhiyun struct net_device *dev = (struct net_device *) dev_id;
769*4882a593Smuzhiyun struct el3_private *lp = netdev_priv(dev);
770*4882a593Smuzhiyun unsigned int ioaddr;
771*4882a593Smuzhiyun unsigned status;
772*4882a593Smuzhiyun int work_budget = max_interrupt_work;
773*4882a593Smuzhiyun int handled = 0;
774*4882a593Smuzhiyun
775*4882a593Smuzhiyun if (!netif_device_present(dev))
776*4882a593Smuzhiyun return IRQ_NONE;
777*4882a593Smuzhiyun ioaddr = dev->base_addr;
778*4882a593Smuzhiyun
779*4882a593Smuzhiyun pr_debug("%s: interrupt, status %4.4x.\n",
780*4882a593Smuzhiyun dev->name, inw(ioaddr + EL3_STATUS));
781*4882a593Smuzhiyun
782*4882a593Smuzhiyun spin_lock(&lp->window_lock);
783*4882a593Smuzhiyun
784*4882a593Smuzhiyun while ((status = inw(ioaddr + EL3_STATUS)) &
785*4882a593Smuzhiyun (IntLatch | RxComplete | RxEarly | StatsFull)) {
786*4882a593Smuzhiyun if (!netif_device_present(dev) ||
787*4882a593Smuzhiyun ((status & 0xe000) != 0x2000)) {
788*4882a593Smuzhiyun pr_debug("%s: Interrupt from dead card\n", dev->name);
789*4882a593Smuzhiyun break;
790*4882a593Smuzhiyun }
791*4882a593Smuzhiyun
792*4882a593Smuzhiyun handled = 1;
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun if (status & RxComplete)
795*4882a593Smuzhiyun work_budget = el3_rx(dev, work_budget);
796*4882a593Smuzhiyun
797*4882a593Smuzhiyun if (status & TxAvailable) {
798*4882a593Smuzhiyun pr_debug(" TX room bit was handled.\n");
799*4882a593Smuzhiyun /* There's room in the FIFO for a full-sized packet. */
800*4882a593Smuzhiyun outw(AckIntr | TxAvailable, ioaddr + EL3_CMD);
801*4882a593Smuzhiyun netif_wake_queue(dev);
802*4882a593Smuzhiyun }
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun if (status & TxComplete)
805*4882a593Smuzhiyun pop_tx_status(dev);
806*4882a593Smuzhiyun
807*4882a593Smuzhiyun if (status & (AdapterFailure | RxEarly | StatsFull)) {
808*4882a593Smuzhiyun /* Handle all uncommon interrupts. */
809*4882a593Smuzhiyun if (status & StatsFull)
810*4882a593Smuzhiyun update_stats(dev);
811*4882a593Smuzhiyun if (status & RxEarly) {
812*4882a593Smuzhiyun work_budget = el3_rx(dev, work_budget);
813*4882a593Smuzhiyun outw(AckIntr | RxEarly, ioaddr + EL3_CMD);
814*4882a593Smuzhiyun }
815*4882a593Smuzhiyun if (status & AdapterFailure) {
816*4882a593Smuzhiyun u16 fifo_diag;
817*4882a593Smuzhiyun EL3WINDOW(4);
818*4882a593Smuzhiyun fifo_diag = inw(ioaddr + Wn4_FIFODiag);
819*4882a593Smuzhiyun EL3WINDOW(1);
820*4882a593Smuzhiyun netdev_notice(dev, "adapter failure, FIFO diagnostic register %04x\n",
821*4882a593Smuzhiyun fifo_diag);
822*4882a593Smuzhiyun if (fifo_diag & 0x0400) {
823*4882a593Smuzhiyun /* Tx overrun */
824*4882a593Smuzhiyun tc574_wait_for_completion(dev, TxReset);
825*4882a593Smuzhiyun outw(TxEnable, ioaddr + EL3_CMD);
826*4882a593Smuzhiyun }
827*4882a593Smuzhiyun if (fifo_diag & 0x2000) {
828*4882a593Smuzhiyun /* Rx underrun */
829*4882a593Smuzhiyun tc574_wait_for_completion(dev, RxReset);
830*4882a593Smuzhiyun set_rx_mode(dev);
831*4882a593Smuzhiyun outw(RxEnable, ioaddr + EL3_CMD);
832*4882a593Smuzhiyun }
833*4882a593Smuzhiyun outw(AckIntr | AdapterFailure, ioaddr + EL3_CMD);
834*4882a593Smuzhiyun }
835*4882a593Smuzhiyun }
836*4882a593Smuzhiyun
837*4882a593Smuzhiyun if (--work_budget < 0) {
838*4882a593Smuzhiyun pr_debug("%s: Too much work in interrupt, "
839*4882a593Smuzhiyun "status %4.4x.\n", dev->name, status);
840*4882a593Smuzhiyun /* Clear all interrupts */
841*4882a593Smuzhiyun outw(AckIntr | 0xFF, ioaddr + EL3_CMD);
842*4882a593Smuzhiyun break;
843*4882a593Smuzhiyun }
844*4882a593Smuzhiyun /* Acknowledge the IRQ. */
845*4882a593Smuzhiyun outw(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
846*4882a593Smuzhiyun }
847*4882a593Smuzhiyun
848*4882a593Smuzhiyun pr_debug("%s: exiting interrupt, status %4.4x.\n",
849*4882a593Smuzhiyun dev->name, inw(ioaddr + EL3_STATUS));
850*4882a593Smuzhiyun
851*4882a593Smuzhiyun spin_unlock(&lp->window_lock);
852*4882a593Smuzhiyun return IRQ_RETVAL(handled);
853*4882a593Smuzhiyun }
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun /*
856*4882a593Smuzhiyun This timer serves two purposes: to check for missed interrupts
857*4882a593Smuzhiyun (and as a last resort, poll the NIC for events), and to monitor
858*4882a593Smuzhiyun the MII, reporting changes in cable status.
859*4882a593Smuzhiyun */
media_check(struct timer_list * t)860*4882a593Smuzhiyun static void media_check(struct timer_list *t)
861*4882a593Smuzhiyun {
862*4882a593Smuzhiyun struct el3_private *lp = from_timer(lp, t, media);
863*4882a593Smuzhiyun struct net_device *dev = lp->p_dev->priv;
864*4882a593Smuzhiyun unsigned int ioaddr = dev->base_addr;
865*4882a593Smuzhiyun unsigned long flags;
866*4882a593Smuzhiyun unsigned short /* cable, */ media, partner;
867*4882a593Smuzhiyun
868*4882a593Smuzhiyun if (!netif_device_present(dev))
869*4882a593Smuzhiyun goto reschedule;
870*4882a593Smuzhiyun
871*4882a593Smuzhiyun /* Check for pending interrupt with expired latency timer: with
872*4882a593Smuzhiyun this, we can limp along even if the interrupt is blocked */
873*4882a593Smuzhiyun if ((inw(ioaddr + EL3_STATUS) & IntLatch) && (inb(ioaddr + Timer) == 0xff)) {
874*4882a593Smuzhiyun if (!lp->fast_poll)
875*4882a593Smuzhiyun netdev_info(dev, "interrupt(s) dropped!\n");
876*4882a593Smuzhiyun
877*4882a593Smuzhiyun local_irq_save(flags);
878*4882a593Smuzhiyun el3_interrupt(dev->irq, dev);
879*4882a593Smuzhiyun local_irq_restore(flags);
880*4882a593Smuzhiyun
881*4882a593Smuzhiyun lp->fast_poll = HZ;
882*4882a593Smuzhiyun }
883*4882a593Smuzhiyun if (lp->fast_poll) {
884*4882a593Smuzhiyun lp->fast_poll--;
885*4882a593Smuzhiyun lp->media.expires = jiffies + 2*HZ/100;
886*4882a593Smuzhiyun add_timer(&lp->media);
887*4882a593Smuzhiyun return;
888*4882a593Smuzhiyun }
889*4882a593Smuzhiyun
890*4882a593Smuzhiyun spin_lock_irqsave(&lp->window_lock, flags);
891*4882a593Smuzhiyun EL3WINDOW(4);
892*4882a593Smuzhiyun media = mdio_read(ioaddr, lp->phys, 1);
893*4882a593Smuzhiyun partner = mdio_read(ioaddr, lp->phys, 5);
894*4882a593Smuzhiyun EL3WINDOW(1);
895*4882a593Smuzhiyun
896*4882a593Smuzhiyun if (media != lp->media_status) {
897*4882a593Smuzhiyun if ((media ^ lp->media_status) & 0x0004)
898*4882a593Smuzhiyun netdev_info(dev, "%s link beat\n",
899*4882a593Smuzhiyun (lp->media_status & 0x0004) ? "lost" : "found");
900*4882a593Smuzhiyun if ((media ^ lp->media_status) & 0x0020) {
901*4882a593Smuzhiyun lp->partner = 0;
902*4882a593Smuzhiyun if (lp->media_status & 0x0020) {
903*4882a593Smuzhiyun netdev_info(dev, "autonegotiation restarted\n");
904*4882a593Smuzhiyun } else if (partner) {
905*4882a593Smuzhiyun partner &= lp->advertising;
906*4882a593Smuzhiyun lp->partner = partner;
907*4882a593Smuzhiyun netdev_info(dev, "autonegotiation complete: "
908*4882a593Smuzhiyun "%dbaseT-%cD selected\n",
909*4882a593Smuzhiyun (partner & 0x0180) ? 100 : 10,
910*4882a593Smuzhiyun (partner & 0x0140) ? 'F' : 'H');
911*4882a593Smuzhiyun } else {
912*4882a593Smuzhiyun netdev_info(dev, "link partner did not autonegotiate\n");
913*4882a593Smuzhiyun }
914*4882a593Smuzhiyun
915*4882a593Smuzhiyun EL3WINDOW(3);
916*4882a593Smuzhiyun outb((partner & 0x0140 ? 0x20 : 0) |
917*4882a593Smuzhiyun (dev->mtu > 1500 ? 0x40 : 0), ioaddr + Wn3_MAC_Ctrl);
918*4882a593Smuzhiyun EL3WINDOW(1);
919*4882a593Smuzhiyun
920*4882a593Smuzhiyun }
921*4882a593Smuzhiyun if (media & 0x0010)
922*4882a593Smuzhiyun netdev_info(dev, "remote fault detected\n");
923*4882a593Smuzhiyun if (media & 0x0002)
924*4882a593Smuzhiyun netdev_info(dev, "jabber detected\n");
925*4882a593Smuzhiyun lp->media_status = media;
926*4882a593Smuzhiyun }
927*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->window_lock, flags);
928*4882a593Smuzhiyun
929*4882a593Smuzhiyun reschedule:
930*4882a593Smuzhiyun lp->media.expires = jiffies + HZ;
931*4882a593Smuzhiyun add_timer(&lp->media);
932*4882a593Smuzhiyun }
933*4882a593Smuzhiyun
el3_get_stats(struct net_device * dev)934*4882a593Smuzhiyun static struct net_device_stats *el3_get_stats(struct net_device *dev)
935*4882a593Smuzhiyun {
936*4882a593Smuzhiyun struct el3_private *lp = netdev_priv(dev);
937*4882a593Smuzhiyun
938*4882a593Smuzhiyun if (netif_device_present(dev)) {
939*4882a593Smuzhiyun unsigned long flags;
940*4882a593Smuzhiyun spin_lock_irqsave(&lp->window_lock, flags);
941*4882a593Smuzhiyun update_stats(dev);
942*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->window_lock, flags);
943*4882a593Smuzhiyun }
944*4882a593Smuzhiyun return &dev->stats;
945*4882a593Smuzhiyun }
946*4882a593Smuzhiyun
947*4882a593Smuzhiyun /* Update statistics.
948*4882a593Smuzhiyun Surprisingly this need not be run single-threaded, but it effectively is.
949*4882a593Smuzhiyun The counters clear when read, so the adds must merely be atomic.
950*4882a593Smuzhiyun */
update_stats(struct net_device * dev)951*4882a593Smuzhiyun static void update_stats(struct net_device *dev)
952*4882a593Smuzhiyun {
953*4882a593Smuzhiyun unsigned int ioaddr = dev->base_addr;
954*4882a593Smuzhiyun u8 up;
955*4882a593Smuzhiyun
956*4882a593Smuzhiyun pr_debug("%s: updating the statistics.\n", dev->name);
957*4882a593Smuzhiyun
958*4882a593Smuzhiyun if (inw(ioaddr+EL3_STATUS) == 0xffff) /* No card. */
959*4882a593Smuzhiyun return;
960*4882a593Smuzhiyun
961*4882a593Smuzhiyun /* Unlike the 3c509 we need not turn off stats updates while reading. */
962*4882a593Smuzhiyun /* Switch to the stats window, and read everything. */
963*4882a593Smuzhiyun EL3WINDOW(6);
964*4882a593Smuzhiyun dev->stats.tx_carrier_errors += inb(ioaddr + 0);
965*4882a593Smuzhiyun dev->stats.tx_heartbeat_errors += inb(ioaddr + 1);
966*4882a593Smuzhiyun /* Multiple collisions. */ inb(ioaddr + 2);
967*4882a593Smuzhiyun dev->stats.collisions += inb(ioaddr + 3);
968*4882a593Smuzhiyun dev->stats.tx_window_errors += inb(ioaddr + 4);
969*4882a593Smuzhiyun dev->stats.rx_fifo_errors += inb(ioaddr + 5);
970*4882a593Smuzhiyun dev->stats.tx_packets += inb(ioaddr + 6);
971*4882a593Smuzhiyun up = inb(ioaddr + 9);
972*4882a593Smuzhiyun dev->stats.tx_packets += (up&0x30) << 4;
973*4882a593Smuzhiyun /* Rx packets */ inb(ioaddr + 7);
974*4882a593Smuzhiyun /* Tx deferrals */ inb(ioaddr + 8);
975*4882a593Smuzhiyun /* rx */ inw(ioaddr + 10);
976*4882a593Smuzhiyun /* tx */ inw(ioaddr + 12);
977*4882a593Smuzhiyun
978*4882a593Smuzhiyun EL3WINDOW(4);
979*4882a593Smuzhiyun /* BadSSD */ inb(ioaddr + 12);
980*4882a593Smuzhiyun up = inb(ioaddr + 13);
981*4882a593Smuzhiyun
982*4882a593Smuzhiyun EL3WINDOW(1);
983*4882a593Smuzhiyun }
984*4882a593Smuzhiyun
el3_rx(struct net_device * dev,int worklimit)985*4882a593Smuzhiyun static int el3_rx(struct net_device *dev, int worklimit)
986*4882a593Smuzhiyun {
987*4882a593Smuzhiyun unsigned int ioaddr = dev->base_addr;
988*4882a593Smuzhiyun short rx_status;
989*4882a593Smuzhiyun
990*4882a593Smuzhiyun pr_debug("%s: in rx_packet(), status %4.4x, rx_status %4.4x.\n",
991*4882a593Smuzhiyun dev->name, inw(ioaddr+EL3_STATUS), inw(ioaddr+RxStatus));
992*4882a593Smuzhiyun while (!((rx_status = inw(ioaddr + RxStatus)) & 0x8000) &&
993*4882a593Smuzhiyun worklimit > 0) {
994*4882a593Smuzhiyun worklimit--;
995*4882a593Smuzhiyun if (rx_status & 0x4000) { /* Error, update stats. */
996*4882a593Smuzhiyun short error = rx_status & 0x3800;
997*4882a593Smuzhiyun dev->stats.rx_errors++;
998*4882a593Smuzhiyun switch (error) {
999*4882a593Smuzhiyun case 0x0000: dev->stats.rx_over_errors++; break;
1000*4882a593Smuzhiyun case 0x0800: dev->stats.rx_length_errors++; break;
1001*4882a593Smuzhiyun case 0x1000: dev->stats.rx_frame_errors++; break;
1002*4882a593Smuzhiyun case 0x1800: dev->stats.rx_length_errors++; break;
1003*4882a593Smuzhiyun case 0x2000: dev->stats.rx_frame_errors++; break;
1004*4882a593Smuzhiyun case 0x2800: dev->stats.rx_crc_errors++; break;
1005*4882a593Smuzhiyun }
1006*4882a593Smuzhiyun } else {
1007*4882a593Smuzhiyun short pkt_len = rx_status & 0x7ff;
1008*4882a593Smuzhiyun struct sk_buff *skb;
1009*4882a593Smuzhiyun
1010*4882a593Smuzhiyun skb = netdev_alloc_skb(dev, pkt_len + 5);
1011*4882a593Smuzhiyun
1012*4882a593Smuzhiyun pr_debug(" Receiving packet size %d status %4.4x.\n",
1013*4882a593Smuzhiyun pkt_len, rx_status);
1014*4882a593Smuzhiyun if (skb != NULL) {
1015*4882a593Smuzhiyun skb_reserve(skb, 2);
1016*4882a593Smuzhiyun insl(ioaddr+RX_FIFO, skb_put(skb, pkt_len),
1017*4882a593Smuzhiyun ((pkt_len+3)>>2));
1018*4882a593Smuzhiyun skb->protocol = eth_type_trans(skb, dev);
1019*4882a593Smuzhiyun netif_rx(skb);
1020*4882a593Smuzhiyun dev->stats.rx_packets++;
1021*4882a593Smuzhiyun dev->stats.rx_bytes += pkt_len;
1022*4882a593Smuzhiyun } else {
1023*4882a593Smuzhiyun pr_debug("%s: couldn't allocate a sk_buff of"
1024*4882a593Smuzhiyun " size %d.\n", dev->name, pkt_len);
1025*4882a593Smuzhiyun dev->stats.rx_dropped++;
1026*4882a593Smuzhiyun }
1027*4882a593Smuzhiyun }
1028*4882a593Smuzhiyun tc574_wait_for_completion(dev, RxDiscard);
1029*4882a593Smuzhiyun }
1030*4882a593Smuzhiyun
1031*4882a593Smuzhiyun return worklimit;
1032*4882a593Smuzhiyun }
1033*4882a593Smuzhiyun
1034*4882a593Smuzhiyun /* Provide ioctl() calls to examine the MII xcvr state. */
el3_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)1035*4882a593Smuzhiyun static int el3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1036*4882a593Smuzhiyun {
1037*4882a593Smuzhiyun struct el3_private *lp = netdev_priv(dev);
1038*4882a593Smuzhiyun unsigned int ioaddr = dev->base_addr;
1039*4882a593Smuzhiyun struct mii_ioctl_data *data = if_mii(rq);
1040*4882a593Smuzhiyun int phy = lp->phys & 0x1f;
1041*4882a593Smuzhiyun
1042*4882a593Smuzhiyun pr_debug("%s: In ioct(%-.6s, %#4.4x) %4.4x %4.4x %4.4x %4.4x.\n",
1043*4882a593Smuzhiyun dev->name, rq->ifr_ifrn.ifrn_name, cmd,
1044*4882a593Smuzhiyun data->phy_id, data->reg_num, data->val_in, data->val_out);
1045*4882a593Smuzhiyun
1046*4882a593Smuzhiyun switch(cmd) {
1047*4882a593Smuzhiyun case SIOCGMIIPHY: /* Get the address of the PHY in use. */
1048*4882a593Smuzhiyun data->phy_id = phy;
1049*4882a593Smuzhiyun fallthrough;
1050*4882a593Smuzhiyun case SIOCGMIIREG: /* Read the specified MII register. */
1051*4882a593Smuzhiyun {
1052*4882a593Smuzhiyun int saved_window;
1053*4882a593Smuzhiyun unsigned long flags;
1054*4882a593Smuzhiyun
1055*4882a593Smuzhiyun spin_lock_irqsave(&lp->window_lock, flags);
1056*4882a593Smuzhiyun saved_window = inw(ioaddr + EL3_CMD) >> 13;
1057*4882a593Smuzhiyun EL3WINDOW(4);
1058*4882a593Smuzhiyun data->val_out = mdio_read(ioaddr, data->phy_id & 0x1f,
1059*4882a593Smuzhiyun data->reg_num & 0x1f);
1060*4882a593Smuzhiyun EL3WINDOW(saved_window);
1061*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->window_lock, flags);
1062*4882a593Smuzhiyun return 0;
1063*4882a593Smuzhiyun }
1064*4882a593Smuzhiyun case SIOCSMIIREG: /* Write the specified MII register */
1065*4882a593Smuzhiyun {
1066*4882a593Smuzhiyun int saved_window;
1067*4882a593Smuzhiyun unsigned long flags;
1068*4882a593Smuzhiyun
1069*4882a593Smuzhiyun spin_lock_irqsave(&lp->window_lock, flags);
1070*4882a593Smuzhiyun saved_window = inw(ioaddr + EL3_CMD) >> 13;
1071*4882a593Smuzhiyun EL3WINDOW(4);
1072*4882a593Smuzhiyun mdio_write(ioaddr, data->phy_id & 0x1f,
1073*4882a593Smuzhiyun data->reg_num & 0x1f, data->val_in);
1074*4882a593Smuzhiyun EL3WINDOW(saved_window);
1075*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->window_lock, flags);
1076*4882a593Smuzhiyun return 0;
1077*4882a593Smuzhiyun }
1078*4882a593Smuzhiyun default:
1079*4882a593Smuzhiyun return -EOPNOTSUPP;
1080*4882a593Smuzhiyun }
1081*4882a593Smuzhiyun }
1082*4882a593Smuzhiyun
1083*4882a593Smuzhiyun /* The Odie chip has a 64 bin multicast filter, but the bit layout is not
1084*4882a593Smuzhiyun documented. Until it is we revert to receiving all multicast frames when
1085*4882a593Smuzhiyun any multicast reception is desired.
1086*4882a593Smuzhiyun Note: My other drivers emit a log message whenever promiscuous mode is
1087*4882a593Smuzhiyun entered to help detect password sniffers. This is less desirable on
1088*4882a593Smuzhiyun typical PC card machines, so we omit the message.
1089*4882a593Smuzhiyun */
1090*4882a593Smuzhiyun
set_rx_mode(struct net_device * dev)1091*4882a593Smuzhiyun static void set_rx_mode(struct net_device *dev)
1092*4882a593Smuzhiyun {
1093*4882a593Smuzhiyun unsigned int ioaddr = dev->base_addr;
1094*4882a593Smuzhiyun
1095*4882a593Smuzhiyun if (dev->flags & IFF_PROMISC)
1096*4882a593Smuzhiyun outw(SetRxFilter | RxStation | RxMulticast | RxBroadcast | RxProm,
1097*4882a593Smuzhiyun ioaddr + EL3_CMD);
1098*4882a593Smuzhiyun else if (!netdev_mc_empty(dev) || (dev->flags & IFF_ALLMULTI))
1099*4882a593Smuzhiyun outw(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
1100*4882a593Smuzhiyun else
1101*4882a593Smuzhiyun outw(SetRxFilter | RxStation | RxBroadcast, ioaddr + EL3_CMD);
1102*4882a593Smuzhiyun }
1103*4882a593Smuzhiyun
set_multicast_list(struct net_device * dev)1104*4882a593Smuzhiyun static void set_multicast_list(struct net_device *dev)
1105*4882a593Smuzhiyun {
1106*4882a593Smuzhiyun struct el3_private *lp = netdev_priv(dev);
1107*4882a593Smuzhiyun unsigned long flags;
1108*4882a593Smuzhiyun
1109*4882a593Smuzhiyun spin_lock_irqsave(&lp->window_lock, flags);
1110*4882a593Smuzhiyun set_rx_mode(dev);
1111*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->window_lock, flags);
1112*4882a593Smuzhiyun }
1113*4882a593Smuzhiyun
el3_close(struct net_device * dev)1114*4882a593Smuzhiyun static int el3_close(struct net_device *dev)
1115*4882a593Smuzhiyun {
1116*4882a593Smuzhiyun unsigned int ioaddr = dev->base_addr;
1117*4882a593Smuzhiyun struct el3_private *lp = netdev_priv(dev);
1118*4882a593Smuzhiyun struct pcmcia_device *link = lp->p_dev;
1119*4882a593Smuzhiyun
1120*4882a593Smuzhiyun dev_dbg(&link->dev, "%s: shutting down ethercard.\n", dev->name);
1121*4882a593Smuzhiyun
1122*4882a593Smuzhiyun if (pcmcia_dev_present(link)) {
1123*4882a593Smuzhiyun unsigned long flags;
1124*4882a593Smuzhiyun
1125*4882a593Smuzhiyun /* Turn off statistics ASAP. We update lp->stats below. */
1126*4882a593Smuzhiyun outw(StatsDisable, ioaddr + EL3_CMD);
1127*4882a593Smuzhiyun
1128*4882a593Smuzhiyun /* Disable the receiver and transmitter. */
1129*4882a593Smuzhiyun outw(RxDisable, ioaddr + EL3_CMD);
1130*4882a593Smuzhiyun outw(TxDisable, ioaddr + EL3_CMD);
1131*4882a593Smuzhiyun
1132*4882a593Smuzhiyun /* Note: Switching to window 0 may disable the IRQ. */
1133*4882a593Smuzhiyun EL3WINDOW(0);
1134*4882a593Smuzhiyun spin_lock_irqsave(&lp->window_lock, flags);
1135*4882a593Smuzhiyun update_stats(dev);
1136*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->window_lock, flags);
1137*4882a593Smuzhiyun
1138*4882a593Smuzhiyun /* force interrupts off */
1139*4882a593Smuzhiyun outw(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
1140*4882a593Smuzhiyun }
1141*4882a593Smuzhiyun
1142*4882a593Smuzhiyun link->open--;
1143*4882a593Smuzhiyun netif_stop_queue(dev);
1144*4882a593Smuzhiyun del_timer_sync(&lp->media);
1145*4882a593Smuzhiyun
1146*4882a593Smuzhiyun return 0;
1147*4882a593Smuzhiyun }
1148*4882a593Smuzhiyun
1149*4882a593Smuzhiyun static const struct pcmcia_device_id tc574_ids[] = {
1150*4882a593Smuzhiyun PCMCIA_DEVICE_MANF_CARD(0x0101, 0x0574),
1151*4882a593Smuzhiyun PCMCIA_MFC_DEVICE_CIS_MANF_CARD(0, 0x0101, 0x0556, "cis/3CCFEM556.cis"),
1152*4882a593Smuzhiyun PCMCIA_DEVICE_NULL,
1153*4882a593Smuzhiyun };
1154*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pcmcia, tc574_ids);
1155*4882a593Smuzhiyun
1156*4882a593Smuzhiyun static struct pcmcia_driver tc574_driver = {
1157*4882a593Smuzhiyun .owner = THIS_MODULE,
1158*4882a593Smuzhiyun .name = "3c574_cs",
1159*4882a593Smuzhiyun .probe = tc574_probe,
1160*4882a593Smuzhiyun .remove = tc574_detach,
1161*4882a593Smuzhiyun .id_table = tc574_ids,
1162*4882a593Smuzhiyun .suspend = tc574_suspend,
1163*4882a593Smuzhiyun .resume = tc574_resume,
1164*4882a593Smuzhiyun };
1165*4882a593Smuzhiyun module_pcmcia_driver(tc574_driver);
1166