1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun Written 1997-1998 by Donald Becker.
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun This software may be used and distributed according to the terms
5*4882a593Smuzhiyun of the GNU General Public License, incorporated herein by reference.
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun This driver is for the 3Com ISA EtherLink XL "Corkscrew" 3c515 ethercard.
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun The author may be reached as becker@scyld.com, or C/O
10*4882a593Smuzhiyun Scyld Computing Corporation
11*4882a593Smuzhiyun 410 Severn Ave., Suite 210
12*4882a593Smuzhiyun Annapolis MD 21403
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun 2000/2/2- Added support for kernel-level ISAPnP
16*4882a593Smuzhiyun by Stephen Frost <sfrost@snowman.net> and Alessandro Zummo
17*4882a593Smuzhiyun Cleaned up for 2.3.x/softnet by Jeff Garzik and Alan Cox.
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun 2001/11/17 - Added ethtool support (jgarzik)
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun 2002/10/28 - Locking updates for 2.5 (alan@lxorguk.ukuu.org.uk)
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun */
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define DRV_NAME "3c515"
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define CORKSCREW 1
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* "Knobs" that adjust features and parameters. */
30*4882a593Smuzhiyun /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
31*4882a593Smuzhiyun Setting to > 1512 effectively disables this feature. */
32*4882a593Smuzhiyun static int rx_copybreak = 200;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
35*4882a593Smuzhiyun static const int mtu = 1500;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
38*4882a593Smuzhiyun static int max_interrupt_work = 20;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* Enable the automatic media selection code -- usually set. */
41*4882a593Smuzhiyun #define AUTOMEDIA 1
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /* Allow the use of fragment bus master transfers instead of only
44*4882a593Smuzhiyun programmed-I/O for Vortex cards. Full-bus-master transfers are always
45*4882a593Smuzhiyun enabled by default on Boomerang cards. If VORTEX_BUS_MASTER is defined,
46*4882a593Smuzhiyun the feature may be turned on using 'options'. */
47*4882a593Smuzhiyun #define VORTEX_BUS_MASTER
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* A few values that may be tweaked. */
50*4882a593Smuzhiyun /* Keep the ring sizes a power of two for efficiency. */
51*4882a593Smuzhiyun #define TX_RING_SIZE 16
52*4882a593Smuzhiyun #define RX_RING_SIZE 16
53*4882a593Smuzhiyun #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #include <linux/module.h>
56*4882a593Smuzhiyun #include <linux/isapnp.h>
57*4882a593Smuzhiyun #include <linux/kernel.h>
58*4882a593Smuzhiyun #include <linux/netdevice.h>
59*4882a593Smuzhiyun #include <linux/string.h>
60*4882a593Smuzhiyun #include <linux/errno.h>
61*4882a593Smuzhiyun #include <linux/in.h>
62*4882a593Smuzhiyun #include <linux/ioport.h>
63*4882a593Smuzhiyun #include <linux/skbuff.h>
64*4882a593Smuzhiyun #include <linux/etherdevice.h>
65*4882a593Smuzhiyun #include <linux/interrupt.h>
66*4882a593Smuzhiyun #include <linux/timer.h>
67*4882a593Smuzhiyun #include <linux/ethtool.h>
68*4882a593Smuzhiyun #include <linux/bitops.h>
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun #include <linux/uaccess.h>
71*4882a593Smuzhiyun #include <asm/io.h>
72*4882a593Smuzhiyun #include <asm/dma.h>
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun #define NEW_MULTICAST
75*4882a593Smuzhiyun #include <linux/delay.h>
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun #define MAX_UNITS 8
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
80*4882a593Smuzhiyun MODULE_DESCRIPTION("3Com 3c515 Corkscrew driver");
81*4882a593Smuzhiyun MODULE_LICENSE("GPL");
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /* "Knobs" for adjusting internal parameters. */
84*4882a593Smuzhiyun /* Put out somewhat more debugging messages. (0 - no msg, 1 minimal msgs). */
85*4882a593Smuzhiyun #define DRIVER_DEBUG 1
86*4882a593Smuzhiyun /* Some values here only for performance evaluation and path-coverage
87*4882a593Smuzhiyun debugging. */
88*4882a593Smuzhiyun static int rx_nocopy, rx_copy, queued_packet;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /* Number of times to check to see if the Tx FIFO has space, used in some
91*4882a593Smuzhiyun limited cases. */
92*4882a593Smuzhiyun #define WAIT_TX_AVAIL 200
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* Operational parameter that usually are not changed. */
95*4882a593Smuzhiyun #define TX_TIMEOUT ((4*HZ)/10) /* Time in jiffies before concluding Tx hung */
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun /* The size here is somewhat misleading: the Corkscrew also uses the ISA
98*4882a593Smuzhiyun aliased registers at <base>+0x400.
99*4882a593Smuzhiyun */
100*4882a593Smuzhiyun #define CORKSCREW_TOTAL_SIZE 0x20
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun #ifdef DRIVER_DEBUG
103*4882a593Smuzhiyun static int corkscrew_debug = DRIVER_DEBUG;
104*4882a593Smuzhiyun #else
105*4882a593Smuzhiyun static int corkscrew_debug = 1;
106*4882a593Smuzhiyun #endif
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun #define CORKSCREW_ID 10
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /*
111*4882a593Smuzhiyun Theory of Operation
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun I. Board Compatibility
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun This device driver is designed for the 3Com 3c515 ISA Fast EtherLink XL,
116*4882a593Smuzhiyun 3Com's ISA bus adapter for Fast Ethernet. Due to the unique I/O port layout,
117*4882a593Smuzhiyun it's not practical to integrate this driver with the other EtherLink drivers.
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun II. Board-specific settings
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun The Corkscrew has an EEPROM for configuration, but no special settings are
122*4882a593Smuzhiyun needed for Linux.
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun III. Driver operation
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun The 3c515 series use an interface that's very similar to the 3c900 "Boomerang"
127*4882a593Smuzhiyun PCI cards, with the bus master interface extensively modified to work with
128*4882a593Smuzhiyun the ISA bus.
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun The card is capable of full-bus-master transfers with separate
131*4882a593Smuzhiyun lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
132*4882a593Smuzhiyun DEC Tulip and Intel Speedo3.
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun This driver uses a "RX_COPYBREAK" scheme rather than a fixed intermediate
135*4882a593Smuzhiyun receive buffer. This scheme allocates full-sized skbuffs as receive
136*4882a593Smuzhiyun buffers. The value RX_COPYBREAK is used as the copying breakpoint: it is
137*4882a593Smuzhiyun chosen to trade-off the memory wasted by passing the full-sized skbuff to
138*4882a593Smuzhiyun the queue layer for all frames vs. the copying cost of copying a frame to a
139*4882a593Smuzhiyun correctly-sized skbuff.
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun IIIC. Synchronization
143*4882a593Smuzhiyun The driver runs as two independent, single-threaded flows of control. One
144*4882a593Smuzhiyun is the send-packet routine, which enforces single-threaded use by the netif
145*4882a593Smuzhiyun layer. The other thread is the interrupt handler, which is single
146*4882a593Smuzhiyun threaded by the hardware and other software.
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun IV. Notes
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun Thanks to Terry Murphy of 3Com for providing documentation and a development
151*4882a593Smuzhiyun board.
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun The names "Vortex", "Boomerang" and "Corkscrew" are the internal 3Com
154*4882a593Smuzhiyun project names. I use these names to eliminate confusion -- 3Com product
155*4882a593Smuzhiyun numbers and names are very similar and often confused.
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun The new chips support both ethernet (1.5K) and FDDI (4.5K) frame sizes!
158*4882a593Smuzhiyun This driver only supports ethernet frames because of the recent MTU limit
159*4882a593Smuzhiyun of 1.5K, but the changes to support 4.5K are minimal.
160*4882a593Smuzhiyun */
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun /* Operational definitions.
163*4882a593Smuzhiyun These are not used by other compilation units and thus are not
164*4882a593Smuzhiyun exported in a ".h" file.
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun First the windows. There are eight register windows, with the command
167*4882a593Smuzhiyun and status registers available in each.
168*4882a593Smuzhiyun */
169*4882a593Smuzhiyun #define EL3WINDOW(win_num) outw(SelectWindow + (win_num), ioaddr + EL3_CMD)
170*4882a593Smuzhiyun #define EL3_CMD 0x0e
171*4882a593Smuzhiyun #define EL3_STATUS 0x0e
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun /* The top five bits written to EL3_CMD are a command, the lower
174*4882a593Smuzhiyun 11 bits are the parameter, if applicable.
175*4882a593Smuzhiyun Note that 11 parameters bits was fine for ethernet, but the new chips
176*4882a593Smuzhiyun can handle FDDI length frames (~4500 octets) and now parameters count
177*4882a593Smuzhiyun 32-bit 'Dwords' rather than octets. */
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun enum corkscrew_cmd {
180*4882a593Smuzhiyun TotalReset = 0 << 11, SelectWindow = 1 << 11, StartCoax = 2 << 11,
181*4882a593Smuzhiyun RxDisable = 3 << 11, RxEnable = 4 << 11, RxReset = 5 << 11,
182*4882a593Smuzhiyun UpStall = 6 << 11, UpUnstall = (6 << 11) + 1, DownStall = (6 << 11) + 2,
183*4882a593Smuzhiyun DownUnstall = (6 << 11) + 3, RxDiscard = 8 << 11, TxEnable = 9 << 11,
184*4882a593Smuzhiyun TxDisable = 10 << 11, TxReset = 11 << 11, FakeIntr = 12 << 11,
185*4882a593Smuzhiyun AckIntr = 13 << 11, SetIntrEnb = 14 << 11, SetStatusEnb = 15 << 11,
186*4882a593Smuzhiyun SetRxFilter = 16 << 11, SetRxThreshold = 17 << 11,
187*4882a593Smuzhiyun SetTxThreshold = 18 << 11, SetTxStart = 19 << 11, StartDMAUp = 20 << 11,
188*4882a593Smuzhiyun StartDMADown = (20 << 11) + 1, StatsEnable = 21 << 11,
189*4882a593Smuzhiyun StatsDisable = 22 << 11, StopCoax = 23 << 11,
190*4882a593Smuzhiyun };
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun /* The SetRxFilter command accepts the following classes: */
193*4882a593Smuzhiyun enum RxFilter {
194*4882a593Smuzhiyun RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8
195*4882a593Smuzhiyun };
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun /* Bits in the general status register. */
198*4882a593Smuzhiyun enum corkscrew_status {
199*4882a593Smuzhiyun IntLatch = 0x0001, AdapterFailure = 0x0002, TxComplete = 0x0004,
200*4882a593Smuzhiyun TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
201*4882a593Smuzhiyun IntReq = 0x0040, StatsFull = 0x0080,
202*4882a593Smuzhiyun DMADone = 1 << 8, DownComplete = 1 << 9, UpComplete = 1 << 10,
203*4882a593Smuzhiyun DMAInProgress = 1 << 11, /* DMA controller is still busy. */
204*4882a593Smuzhiyun CmdInProgress = 1 << 12, /* EL3_CMD is still busy. */
205*4882a593Smuzhiyun };
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun /* Register window 1 offsets, the window used in normal operation.
208*4882a593Smuzhiyun On the Corkscrew this window is always mapped at offsets 0x10-0x1f. */
209*4882a593Smuzhiyun enum Window1 {
210*4882a593Smuzhiyun TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
211*4882a593Smuzhiyun RxStatus = 0x18, Timer = 0x1A, TxStatus = 0x1B,
212*4882a593Smuzhiyun TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
213*4882a593Smuzhiyun };
214*4882a593Smuzhiyun enum Window0 {
215*4882a593Smuzhiyun Wn0IRQ = 0x08,
216*4882a593Smuzhiyun #if defined(CORKSCREW)
217*4882a593Smuzhiyun Wn0EepromCmd = 0x200A, /* Corkscrew EEPROM command register. */
218*4882a593Smuzhiyun Wn0EepromData = 0x200C, /* Corkscrew EEPROM results register. */
219*4882a593Smuzhiyun #else
220*4882a593Smuzhiyun Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
221*4882a593Smuzhiyun Wn0EepromData = 12, /* Window 0: EEPROM results register. */
222*4882a593Smuzhiyun #endif
223*4882a593Smuzhiyun };
224*4882a593Smuzhiyun enum Win0_EEPROM_bits {
225*4882a593Smuzhiyun EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
226*4882a593Smuzhiyun EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
227*4882a593Smuzhiyun EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
228*4882a593Smuzhiyun };
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun /* EEPROM locations. */
231*4882a593Smuzhiyun enum eeprom_offset {
232*4882a593Smuzhiyun PhysAddr01 = 0, PhysAddr23 = 1, PhysAddr45 = 2, ModelID = 3,
233*4882a593Smuzhiyun EtherLink3ID = 7,
234*4882a593Smuzhiyun };
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun enum Window3 { /* Window 3: MAC/config bits. */
237*4882a593Smuzhiyun Wn3_Config = 0, Wn3_MAC_Ctrl = 6, Wn3_Options = 8,
238*4882a593Smuzhiyun };
239*4882a593Smuzhiyun enum wn3_config {
240*4882a593Smuzhiyun Ram_size = 7,
241*4882a593Smuzhiyun Ram_width = 8,
242*4882a593Smuzhiyun Ram_speed = 0x30,
243*4882a593Smuzhiyun Rom_size = 0xc0,
244*4882a593Smuzhiyun Ram_split_shift = 16,
245*4882a593Smuzhiyun Ram_split = 3 << Ram_split_shift,
246*4882a593Smuzhiyun Xcvr_shift = 20,
247*4882a593Smuzhiyun Xcvr = 7 << Xcvr_shift,
248*4882a593Smuzhiyun Autoselect = 0x1000000,
249*4882a593Smuzhiyun };
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun enum Window4 {
252*4882a593Smuzhiyun Wn4_NetDiag = 6, Wn4_Media = 10, /* Window 4: Xcvr/media bits. */
253*4882a593Smuzhiyun };
254*4882a593Smuzhiyun enum Win4_Media_bits {
255*4882a593Smuzhiyun Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
256*4882a593Smuzhiyun Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
257*4882a593Smuzhiyun Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
258*4882a593Smuzhiyun Media_LnkBeat = 0x0800,
259*4882a593Smuzhiyun };
260*4882a593Smuzhiyun enum Window7 { /* Window 7: Bus Master control. */
261*4882a593Smuzhiyun Wn7_MasterAddr = 0, Wn7_MasterLen = 6, Wn7_MasterStatus = 12,
262*4882a593Smuzhiyun };
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun /* Boomerang-style bus master control registers. Note ISA aliases! */
265*4882a593Smuzhiyun enum MasterCtrl {
266*4882a593Smuzhiyun PktStatus = 0x400, DownListPtr = 0x404, FragAddr = 0x408, FragLen =
267*4882a593Smuzhiyun 0x40c,
268*4882a593Smuzhiyun TxFreeThreshold = 0x40f, UpPktStatus = 0x410, UpListPtr = 0x418,
269*4882a593Smuzhiyun };
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun /* The Rx and Tx descriptor lists.
272*4882a593Smuzhiyun Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
273*4882a593Smuzhiyun alignment contraint on tx_ring[] and rx_ring[]. */
274*4882a593Smuzhiyun struct boom_rx_desc {
275*4882a593Smuzhiyun u32 next;
276*4882a593Smuzhiyun s32 status;
277*4882a593Smuzhiyun u32 addr;
278*4882a593Smuzhiyun s32 length;
279*4882a593Smuzhiyun };
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun /* Values for the Rx status entry. */
282*4882a593Smuzhiyun enum rx_desc_status {
283*4882a593Smuzhiyun RxDComplete = 0x00008000, RxDError = 0x4000,
284*4882a593Smuzhiyun /* See boomerang_rx() for actual error bits */
285*4882a593Smuzhiyun };
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun struct boom_tx_desc {
288*4882a593Smuzhiyun u32 next;
289*4882a593Smuzhiyun s32 status;
290*4882a593Smuzhiyun u32 addr;
291*4882a593Smuzhiyun s32 length;
292*4882a593Smuzhiyun };
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun struct corkscrew_private {
295*4882a593Smuzhiyun const char *product_name;
296*4882a593Smuzhiyun struct list_head list;
297*4882a593Smuzhiyun struct net_device *our_dev;
298*4882a593Smuzhiyun /* The Rx and Tx rings are here to keep them quad-word-aligned. */
299*4882a593Smuzhiyun struct boom_rx_desc rx_ring[RX_RING_SIZE];
300*4882a593Smuzhiyun struct boom_tx_desc tx_ring[TX_RING_SIZE];
301*4882a593Smuzhiyun /* The addresses of transmit- and receive-in-place skbuffs. */
302*4882a593Smuzhiyun struct sk_buff *rx_skbuff[RX_RING_SIZE];
303*4882a593Smuzhiyun struct sk_buff *tx_skbuff[TX_RING_SIZE];
304*4882a593Smuzhiyun unsigned int cur_rx, cur_tx; /* The next free ring entry */
305*4882a593Smuzhiyun unsigned int dirty_rx, dirty_tx;/* The ring entries to be free()ed. */
306*4882a593Smuzhiyun struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
307*4882a593Smuzhiyun struct timer_list timer; /* Media selection timer. */
308*4882a593Smuzhiyun int capabilities ; /* Adapter capabilities word. */
309*4882a593Smuzhiyun int options; /* User-settable misc. driver options. */
310*4882a593Smuzhiyun int last_rx_packets; /* For media autoselection. */
311*4882a593Smuzhiyun unsigned int available_media:8, /* From Wn3_Options */
312*4882a593Smuzhiyun media_override:3, /* Passed-in media type. */
313*4882a593Smuzhiyun default_media:3, /* Read from the EEPROM. */
314*4882a593Smuzhiyun full_duplex:1, autoselect:1, bus_master:1, /* Vortex can only do a fragment bus-m. */
315*4882a593Smuzhiyun full_bus_master_tx:1, full_bus_master_rx:1, /* Boomerang */
316*4882a593Smuzhiyun tx_full:1;
317*4882a593Smuzhiyun spinlock_t lock;
318*4882a593Smuzhiyun struct device *dev;
319*4882a593Smuzhiyun };
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun /* The action to take with a media selection timer tick.
322*4882a593Smuzhiyun Note that we deviate from the 3Com order by checking 10base2 before AUI.
323*4882a593Smuzhiyun */
324*4882a593Smuzhiyun enum xcvr_types {
325*4882a593Smuzhiyun XCVR_10baseT = 0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
326*4882a593Smuzhiyun XCVR_100baseFx, XCVR_MII = 6, XCVR_Default = 8,
327*4882a593Smuzhiyun };
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun static struct media_table {
330*4882a593Smuzhiyun char *name;
331*4882a593Smuzhiyun unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
332*4882a593Smuzhiyun mask:8, /* The transceiver-present bit in Wn3_Config. */
333*4882a593Smuzhiyun next:8; /* The media type to try next. */
334*4882a593Smuzhiyun short wait; /* Time before we check media status. */
335*4882a593Smuzhiyun } media_tbl[] = {
336*4882a593Smuzhiyun { "10baseT", Media_10TP, 0x08, XCVR_10base2, (14 * HZ) / 10 },
337*4882a593Smuzhiyun { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1 * HZ) / 10},
338*4882a593Smuzhiyun { "undefined", 0, 0x80, XCVR_10baseT, 10000},
339*4882a593Smuzhiyun { "10base2", 0, 0x10, XCVR_AUI, (1 * HZ) / 10},
340*4882a593Smuzhiyun { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14 * HZ) / 10},
341*4882a593Smuzhiyun { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14 * HZ) / 10},
342*4882a593Smuzhiyun { "MII", 0, 0x40, XCVR_10baseT, 3 * HZ},
343*4882a593Smuzhiyun { "undefined", 0, 0x01, XCVR_10baseT, 10000},
344*4882a593Smuzhiyun { "Default", 0, 0xFF, XCVR_10baseT, 10000},
345*4882a593Smuzhiyun };
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun #ifdef __ISAPNP__
348*4882a593Smuzhiyun static struct isapnp_device_id corkscrew_isapnp_adapters[] = {
349*4882a593Smuzhiyun { ISAPNP_ANY_ID, ISAPNP_ANY_ID,
350*4882a593Smuzhiyun ISAPNP_VENDOR('T', 'C', 'M'), ISAPNP_FUNCTION(0x5051),
351*4882a593Smuzhiyun (long) "3Com Fast EtherLink ISA" },
352*4882a593Smuzhiyun { } /* terminate list */
353*4882a593Smuzhiyun };
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun MODULE_DEVICE_TABLE(isapnp, corkscrew_isapnp_adapters);
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun static int nopnp;
358*4882a593Smuzhiyun #endif /* __ISAPNP__ */
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun static struct net_device *corkscrew_scan(int unit);
361*4882a593Smuzhiyun static int corkscrew_setup(struct net_device *dev, int ioaddr,
362*4882a593Smuzhiyun struct pnp_dev *idev, int card_number);
363*4882a593Smuzhiyun static int corkscrew_open(struct net_device *dev);
364*4882a593Smuzhiyun static void corkscrew_timer(struct timer_list *t);
365*4882a593Smuzhiyun static netdev_tx_t corkscrew_start_xmit(struct sk_buff *skb,
366*4882a593Smuzhiyun struct net_device *dev);
367*4882a593Smuzhiyun static int corkscrew_rx(struct net_device *dev);
368*4882a593Smuzhiyun static void corkscrew_timeout(struct net_device *dev, unsigned int txqueue);
369*4882a593Smuzhiyun static int boomerang_rx(struct net_device *dev);
370*4882a593Smuzhiyun static irqreturn_t corkscrew_interrupt(int irq, void *dev_id);
371*4882a593Smuzhiyun static int corkscrew_close(struct net_device *dev);
372*4882a593Smuzhiyun static void update_stats(int addr, struct net_device *dev);
373*4882a593Smuzhiyun static struct net_device_stats *corkscrew_get_stats(struct net_device *dev);
374*4882a593Smuzhiyun static void set_rx_mode(struct net_device *dev);
375*4882a593Smuzhiyun static const struct ethtool_ops netdev_ethtool_ops;
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun /*
379*4882a593Smuzhiyun Unfortunately maximizing the shared code between the integrated and
380*4882a593Smuzhiyun module version of the driver results in a complicated set of initialization
381*4882a593Smuzhiyun procedures.
382*4882a593Smuzhiyun init_module() -- modules / tc59x_init() -- built-in
383*4882a593Smuzhiyun The wrappers for corkscrew_scan()
384*4882a593Smuzhiyun corkscrew_scan() The common routine that scans for PCI and EISA cards
385*4882a593Smuzhiyun corkscrew_found_device() Allocate a device structure when we find a card.
386*4882a593Smuzhiyun Different versions exist for modules and built-in.
387*4882a593Smuzhiyun corkscrew_probe1() Fill in the device structure -- this is separated
388*4882a593Smuzhiyun so that the modules code can put it in dev->init.
389*4882a593Smuzhiyun */
390*4882a593Smuzhiyun /* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
391*4882a593Smuzhiyun /* Note: this is the only limit on the number of cards supported!! */
392*4882a593Smuzhiyun static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1, };
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun #ifdef MODULE
395*4882a593Smuzhiyun static int debug = -1;
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun module_param(debug, int, 0);
398*4882a593Smuzhiyun module_param_array(options, int, NULL, 0);
399*4882a593Smuzhiyun module_param(rx_copybreak, int, 0);
400*4882a593Smuzhiyun module_param(max_interrupt_work, int, 0);
401*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "3c515 debug level (0-6)");
402*4882a593Smuzhiyun MODULE_PARM_DESC(options, "3c515: Bits 0-2: media type, bit 3: full duplex, bit 4: bus mastering");
403*4882a593Smuzhiyun MODULE_PARM_DESC(rx_copybreak, "3c515 copy breakpoint for copy-only-tiny-frames");
404*4882a593Smuzhiyun MODULE_PARM_DESC(max_interrupt_work, "3c515 maximum events handled per interrupt");
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun /* A list of all installed Vortex devices, for removing the driver module. */
407*4882a593Smuzhiyun /* we will need locking (and refcounting) if we ever use it for more */
408*4882a593Smuzhiyun static LIST_HEAD(root_corkscrew_dev);
409*4882a593Smuzhiyun
init_module(void)410*4882a593Smuzhiyun int init_module(void)
411*4882a593Smuzhiyun {
412*4882a593Smuzhiyun int found = 0;
413*4882a593Smuzhiyun if (debug >= 0)
414*4882a593Smuzhiyun corkscrew_debug = debug;
415*4882a593Smuzhiyun while (corkscrew_scan(-1))
416*4882a593Smuzhiyun found++;
417*4882a593Smuzhiyun return found ? 0 : -ENODEV;
418*4882a593Smuzhiyun }
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun #else
tc515_probe(int unit)421*4882a593Smuzhiyun struct net_device *tc515_probe(int unit)
422*4882a593Smuzhiyun {
423*4882a593Smuzhiyun struct net_device *dev = corkscrew_scan(unit);
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun if (!dev)
426*4882a593Smuzhiyun return ERR_PTR(-ENODEV);
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun return dev;
429*4882a593Smuzhiyun }
430*4882a593Smuzhiyun #endif /* not MODULE */
431*4882a593Smuzhiyun
check_device(unsigned ioaddr)432*4882a593Smuzhiyun static int check_device(unsigned ioaddr)
433*4882a593Smuzhiyun {
434*4882a593Smuzhiyun int timer;
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun if (!request_region(ioaddr, CORKSCREW_TOTAL_SIZE, "3c515"))
437*4882a593Smuzhiyun return 0;
438*4882a593Smuzhiyun /* Check the resource configuration for a matching ioaddr. */
439*4882a593Smuzhiyun if ((inw(ioaddr + 0x2002) & 0x1f0) != (ioaddr & 0x1f0)) {
440*4882a593Smuzhiyun release_region(ioaddr, CORKSCREW_TOTAL_SIZE);
441*4882a593Smuzhiyun return 0;
442*4882a593Smuzhiyun }
443*4882a593Smuzhiyun /* Verify by reading the device ID from the EEPROM. */
444*4882a593Smuzhiyun outw(EEPROM_Read + 7, ioaddr + Wn0EepromCmd);
445*4882a593Smuzhiyun /* Pause for at least 162 us. for the read to take place. */
446*4882a593Smuzhiyun for (timer = 4; timer >= 0; timer--) {
447*4882a593Smuzhiyun udelay(162);
448*4882a593Smuzhiyun if ((inw(ioaddr + Wn0EepromCmd) & 0x0200) == 0)
449*4882a593Smuzhiyun break;
450*4882a593Smuzhiyun }
451*4882a593Smuzhiyun if (inw(ioaddr + Wn0EepromData) != 0x6d50) {
452*4882a593Smuzhiyun release_region(ioaddr, CORKSCREW_TOTAL_SIZE);
453*4882a593Smuzhiyun return 0;
454*4882a593Smuzhiyun }
455*4882a593Smuzhiyun return 1;
456*4882a593Smuzhiyun }
457*4882a593Smuzhiyun
cleanup_card(struct net_device * dev)458*4882a593Smuzhiyun static void cleanup_card(struct net_device *dev)
459*4882a593Smuzhiyun {
460*4882a593Smuzhiyun struct corkscrew_private *vp = netdev_priv(dev);
461*4882a593Smuzhiyun list_del_init(&vp->list);
462*4882a593Smuzhiyun if (dev->dma)
463*4882a593Smuzhiyun free_dma(dev->dma);
464*4882a593Smuzhiyun outw(TotalReset, dev->base_addr + EL3_CMD);
465*4882a593Smuzhiyun release_region(dev->base_addr, CORKSCREW_TOTAL_SIZE);
466*4882a593Smuzhiyun if (vp->dev)
467*4882a593Smuzhiyun pnp_device_detach(to_pnp_dev(vp->dev));
468*4882a593Smuzhiyun }
469*4882a593Smuzhiyun
corkscrew_scan(int unit)470*4882a593Smuzhiyun static struct net_device *corkscrew_scan(int unit)
471*4882a593Smuzhiyun {
472*4882a593Smuzhiyun struct net_device *dev;
473*4882a593Smuzhiyun static int cards_found = 0;
474*4882a593Smuzhiyun static int ioaddr;
475*4882a593Smuzhiyun int err;
476*4882a593Smuzhiyun #ifdef __ISAPNP__
477*4882a593Smuzhiyun short i;
478*4882a593Smuzhiyun static int pnp_cards;
479*4882a593Smuzhiyun #endif
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun dev = alloc_etherdev(sizeof(struct corkscrew_private));
482*4882a593Smuzhiyun if (!dev)
483*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun if (unit >= 0) {
486*4882a593Smuzhiyun sprintf(dev->name, "eth%d", unit);
487*4882a593Smuzhiyun netdev_boot_setup_check(dev);
488*4882a593Smuzhiyun }
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun #ifdef __ISAPNP__
491*4882a593Smuzhiyun if(nopnp == 1)
492*4882a593Smuzhiyun goto no_pnp;
493*4882a593Smuzhiyun for(i=0; corkscrew_isapnp_adapters[i].vendor != 0; i++) {
494*4882a593Smuzhiyun struct pnp_dev *idev = NULL;
495*4882a593Smuzhiyun int irq;
496*4882a593Smuzhiyun while((idev = pnp_find_dev(NULL,
497*4882a593Smuzhiyun corkscrew_isapnp_adapters[i].vendor,
498*4882a593Smuzhiyun corkscrew_isapnp_adapters[i].function,
499*4882a593Smuzhiyun idev))) {
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun if (pnp_device_attach(idev) < 0)
502*4882a593Smuzhiyun continue;
503*4882a593Smuzhiyun if (pnp_activate_dev(idev) < 0) {
504*4882a593Smuzhiyun pr_warn("pnp activate failed (out of resources?)\n");
505*4882a593Smuzhiyun pnp_device_detach(idev);
506*4882a593Smuzhiyun continue;
507*4882a593Smuzhiyun }
508*4882a593Smuzhiyun if (!pnp_port_valid(idev, 0) || !pnp_irq_valid(idev, 0)) {
509*4882a593Smuzhiyun pnp_device_detach(idev);
510*4882a593Smuzhiyun continue;
511*4882a593Smuzhiyun }
512*4882a593Smuzhiyun ioaddr = pnp_port_start(idev, 0);
513*4882a593Smuzhiyun irq = pnp_irq(idev, 0);
514*4882a593Smuzhiyun if (!check_device(ioaddr)) {
515*4882a593Smuzhiyun pnp_device_detach(idev);
516*4882a593Smuzhiyun continue;
517*4882a593Smuzhiyun }
518*4882a593Smuzhiyun if(corkscrew_debug)
519*4882a593Smuzhiyun pr_debug("ISAPNP reports %s at i/o 0x%x, irq %d\n",
520*4882a593Smuzhiyun (char*) corkscrew_isapnp_adapters[i].driver_data, ioaddr, irq);
521*4882a593Smuzhiyun pr_info("3c515 Resource configuration register %#4.4x, DCR %4.4x.\n",
522*4882a593Smuzhiyun inl(ioaddr + 0x2002), inw(ioaddr + 0x2000));
523*4882a593Smuzhiyun /* irq = inw(ioaddr + 0x2002) & 15; */ /* Use the irq from isapnp */
524*4882a593Smuzhiyun SET_NETDEV_DEV(dev, &idev->dev);
525*4882a593Smuzhiyun pnp_cards++;
526*4882a593Smuzhiyun err = corkscrew_setup(dev, ioaddr, idev, cards_found++);
527*4882a593Smuzhiyun if (!err)
528*4882a593Smuzhiyun return dev;
529*4882a593Smuzhiyun cleanup_card(dev);
530*4882a593Smuzhiyun }
531*4882a593Smuzhiyun }
532*4882a593Smuzhiyun no_pnp:
533*4882a593Smuzhiyun #endif /* __ISAPNP__ */
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun /* Check all locations on the ISA bus -- evil! */
536*4882a593Smuzhiyun for (ioaddr = 0x100; ioaddr < 0x400; ioaddr += 0x20) {
537*4882a593Smuzhiyun if (!check_device(ioaddr))
538*4882a593Smuzhiyun continue;
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun pr_info("3c515 Resource configuration register %#4.4x, DCR %4.4x.\n",
541*4882a593Smuzhiyun inl(ioaddr + 0x2002), inw(ioaddr + 0x2000));
542*4882a593Smuzhiyun err = corkscrew_setup(dev, ioaddr, NULL, cards_found++);
543*4882a593Smuzhiyun if (!err)
544*4882a593Smuzhiyun return dev;
545*4882a593Smuzhiyun cleanup_card(dev);
546*4882a593Smuzhiyun }
547*4882a593Smuzhiyun free_netdev(dev);
548*4882a593Smuzhiyun return NULL;
549*4882a593Smuzhiyun }
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun static const struct net_device_ops netdev_ops = {
553*4882a593Smuzhiyun .ndo_open = corkscrew_open,
554*4882a593Smuzhiyun .ndo_stop = corkscrew_close,
555*4882a593Smuzhiyun .ndo_start_xmit = corkscrew_start_xmit,
556*4882a593Smuzhiyun .ndo_tx_timeout = corkscrew_timeout,
557*4882a593Smuzhiyun .ndo_get_stats = corkscrew_get_stats,
558*4882a593Smuzhiyun .ndo_set_rx_mode = set_rx_mode,
559*4882a593Smuzhiyun .ndo_set_mac_address = eth_mac_addr,
560*4882a593Smuzhiyun .ndo_validate_addr = eth_validate_addr,
561*4882a593Smuzhiyun };
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun
corkscrew_setup(struct net_device * dev,int ioaddr,struct pnp_dev * idev,int card_number)564*4882a593Smuzhiyun static int corkscrew_setup(struct net_device *dev, int ioaddr,
565*4882a593Smuzhiyun struct pnp_dev *idev, int card_number)
566*4882a593Smuzhiyun {
567*4882a593Smuzhiyun struct corkscrew_private *vp = netdev_priv(dev);
568*4882a593Smuzhiyun unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
569*4882a593Smuzhiyun int i;
570*4882a593Smuzhiyun int irq;
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun #ifdef __ISAPNP__
573*4882a593Smuzhiyun if (idev) {
574*4882a593Smuzhiyun irq = pnp_irq(idev, 0);
575*4882a593Smuzhiyun vp->dev = &idev->dev;
576*4882a593Smuzhiyun } else {
577*4882a593Smuzhiyun irq = inw(ioaddr + 0x2002) & 15;
578*4882a593Smuzhiyun }
579*4882a593Smuzhiyun #else
580*4882a593Smuzhiyun irq = inw(ioaddr + 0x2002) & 15;
581*4882a593Smuzhiyun #endif
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun dev->base_addr = ioaddr;
584*4882a593Smuzhiyun dev->irq = irq;
585*4882a593Smuzhiyun dev->dma = inw(ioaddr + 0x2000) & 7;
586*4882a593Smuzhiyun vp->product_name = "3c515";
587*4882a593Smuzhiyun vp->options = dev->mem_start;
588*4882a593Smuzhiyun vp->our_dev = dev;
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun if (!vp->options) {
591*4882a593Smuzhiyun if (card_number >= MAX_UNITS)
592*4882a593Smuzhiyun vp->options = -1;
593*4882a593Smuzhiyun else
594*4882a593Smuzhiyun vp->options = options[card_number];
595*4882a593Smuzhiyun }
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun if (vp->options >= 0) {
598*4882a593Smuzhiyun vp->media_override = vp->options & 7;
599*4882a593Smuzhiyun if (vp->media_override == 2)
600*4882a593Smuzhiyun vp->media_override = 0;
601*4882a593Smuzhiyun vp->full_duplex = (vp->options & 8) ? 1 : 0;
602*4882a593Smuzhiyun vp->bus_master = (vp->options & 16) ? 1 : 0;
603*4882a593Smuzhiyun } else {
604*4882a593Smuzhiyun vp->media_override = 7;
605*4882a593Smuzhiyun vp->full_duplex = 0;
606*4882a593Smuzhiyun vp->bus_master = 0;
607*4882a593Smuzhiyun }
608*4882a593Smuzhiyun #ifdef MODULE
609*4882a593Smuzhiyun list_add(&vp->list, &root_corkscrew_dev);
610*4882a593Smuzhiyun #endif
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun pr_info("%s: 3Com %s at %#3x,", dev->name, vp->product_name, ioaddr);
613*4882a593Smuzhiyun
614*4882a593Smuzhiyun spin_lock_init(&vp->lock);
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun timer_setup(&vp->timer, corkscrew_timer, 0);
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun /* Read the station address from the EEPROM. */
619*4882a593Smuzhiyun EL3WINDOW(0);
620*4882a593Smuzhiyun for (i = 0; i < 0x18; i++) {
621*4882a593Smuzhiyun __be16 *phys_addr = (__be16 *) dev->dev_addr;
622*4882a593Smuzhiyun int timer;
623*4882a593Smuzhiyun outw(EEPROM_Read + i, ioaddr + Wn0EepromCmd);
624*4882a593Smuzhiyun /* Pause for at least 162 us. for the read to take place. */
625*4882a593Smuzhiyun for (timer = 4; timer >= 0; timer--) {
626*4882a593Smuzhiyun udelay(162);
627*4882a593Smuzhiyun if ((inw(ioaddr + Wn0EepromCmd) & 0x0200) == 0)
628*4882a593Smuzhiyun break;
629*4882a593Smuzhiyun }
630*4882a593Smuzhiyun eeprom[i] = inw(ioaddr + Wn0EepromData);
631*4882a593Smuzhiyun checksum ^= eeprom[i];
632*4882a593Smuzhiyun if (i < 3)
633*4882a593Smuzhiyun phys_addr[i] = htons(eeprom[i]);
634*4882a593Smuzhiyun }
635*4882a593Smuzhiyun checksum = (checksum ^ (checksum >> 8)) & 0xff;
636*4882a593Smuzhiyun if (checksum != 0x00)
637*4882a593Smuzhiyun pr_cont(" ***INVALID CHECKSUM %4.4x*** ", checksum);
638*4882a593Smuzhiyun pr_cont(" %pM", dev->dev_addr);
639*4882a593Smuzhiyun if (eeprom[16] == 0x11c7) { /* Corkscrew */
640*4882a593Smuzhiyun if (request_dma(dev->dma, "3c515")) {
641*4882a593Smuzhiyun pr_cont(", DMA %d allocation failed", dev->dma);
642*4882a593Smuzhiyun dev->dma = 0;
643*4882a593Smuzhiyun } else
644*4882a593Smuzhiyun pr_cont(", DMA %d", dev->dma);
645*4882a593Smuzhiyun }
646*4882a593Smuzhiyun pr_cont(", IRQ %d\n", dev->irq);
647*4882a593Smuzhiyun /* Tell them about an invalid IRQ. */
648*4882a593Smuzhiyun if (corkscrew_debug && (dev->irq <= 0 || dev->irq > 15))
649*4882a593Smuzhiyun pr_warn(" *** Warning: this IRQ is unlikely to work! ***\n");
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun {
652*4882a593Smuzhiyun static const char * const ram_split[] = {
653*4882a593Smuzhiyun "5:3", "3:1", "1:1", "3:5"
654*4882a593Smuzhiyun };
655*4882a593Smuzhiyun __u32 config;
656*4882a593Smuzhiyun EL3WINDOW(3);
657*4882a593Smuzhiyun vp->available_media = inw(ioaddr + Wn3_Options);
658*4882a593Smuzhiyun config = inl(ioaddr + Wn3_Config);
659*4882a593Smuzhiyun if (corkscrew_debug > 1)
660*4882a593Smuzhiyun pr_info(" Internal config register is %4.4x, transceivers %#x.\n",
661*4882a593Smuzhiyun config, inw(ioaddr + Wn3_Options));
662*4882a593Smuzhiyun pr_info(" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
663*4882a593Smuzhiyun 8 << config & Ram_size,
664*4882a593Smuzhiyun config & Ram_width ? "word" : "byte",
665*4882a593Smuzhiyun ram_split[(config & Ram_split) >> Ram_split_shift],
666*4882a593Smuzhiyun config & Autoselect ? "autoselect/" : "",
667*4882a593Smuzhiyun media_tbl[(config & Xcvr) >> Xcvr_shift].name);
668*4882a593Smuzhiyun vp->default_media = (config & Xcvr) >> Xcvr_shift;
669*4882a593Smuzhiyun vp->autoselect = config & Autoselect ? 1 : 0;
670*4882a593Smuzhiyun dev->if_port = vp->default_media;
671*4882a593Smuzhiyun }
672*4882a593Smuzhiyun if (vp->media_override != 7) {
673*4882a593Smuzhiyun pr_info(" Media override to transceiver type %d (%s).\n",
674*4882a593Smuzhiyun vp->media_override,
675*4882a593Smuzhiyun media_tbl[vp->media_override].name);
676*4882a593Smuzhiyun dev->if_port = vp->media_override;
677*4882a593Smuzhiyun }
678*4882a593Smuzhiyun
679*4882a593Smuzhiyun vp->capabilities = eeprom[16];
680*4882a593Smuzhiyun vp->full_bus_master_tx = (vp->capabilities & 0x20) ? 1 : 0;
681*4882a593Smuzhiyun /* Rx is broken at 10mbps, so we always disable it. */
682*4882a593Smuzhiyun /* vp->full_bus_master_rx = 0; */
683*4882a593Smuzhiyun vp->full_bus_master_rx = (vp->capabilities & 0x20) ? 1 : 0;
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun /* The 3c51x-specific entries in the device structure. */
686*4882a593Smuzhiyun dev->netdev_ops = &netdev_ops;
687*4882a593Smuzhiyun dev->watchdog_timeo = (400 * HZ) / 1000;
688*4882a593Smuzhiyun dev->ethtool_ops = &netdev_ethtool_ops;
689*4882a593Smuzhiyun
690*4882a593Smuzhiyun return register_netdev(dev);
691*4882a593Smuzhiyun }
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun
corkscrew_open(struct net_device * dev)694*4882a593Smuzhiyun static int corkscrew_open(struct net_device *dev)
695*4882a593Smuzhiyun {
696*4882a593Smuzhiyun int ioaddr = dev->base_addr;
697*4882a593Smuzhiyun struct corkscrew_private *vp = netdev_priv(dev);
698*4882a593Smuzhiyun bool armtimer = false;
699*4882a593Smuzhiyun __u32 config;
700*4882a593Smuzhiyun int i;
701*4882a593Smuzhiyun
702*4882a593Smuzhiyun /* Before initializing select the active media port. */
703*4882a593Smuzhiyun EL3WINDOW(3);
704*4882a593Smuzhiyun if (vp->full_duplex)
705*4882a593Smuzhiyun outb(0x20, ioaddr + Wn3_MAC_Ctrl); /* Set the full-duplex bit. */
706*4882a593Smuzhiyun config = inl(ioaddr + Wn3_Config);
707*4882a593Smuzhiyun
708*4882a593Smuzhiyun if (vp->media_override != 7) {
709*4882a593Smuzhiyun if (corkscrew_debug > 1)
710*4882a593Smuzhiyun pr_info("%s: Media override to transceiver %d (%s).\n",
711*4882a593Smuzhiyun dev->name, vp->media_override,
712*4882a593Smuzhiyun media_tbl[vp->media_override].name);
713*4882a593Smuzhiyun dev->if_port = vp->media_override;
714*4882a593Smuzhiyun } else if (vp->autoselect) {
715*4882a593Smuzhiyun /* Find first available media type, starting with 100baseTx. */
716*4882a593Smuzhiyun dev->if_port = 4;
717*4882a593Smuzhiyun while (!(vp->available_media & media_tbl[dev->if_port].mask))
718*4882a593Smuzhiyun dev->if_port = media_tbl[dev->if_port].next;
719*4882a593Smuzhiyun
720*4882a593Smuzhiyun if (corkscrew_debug > 1)
721*4882a593Smuzhiyun pr_debug("%s: Initial media type %s.\n",
722*4882a593Smuzhiyun dev->name, media_tbl[dev->if_port].name);
723*4882a593Smuzhiyun armtimer = true;
724*4882a593Smuzhiyun } else
725*4882a593Smuzhiyun dev->if_port = vp->default_media;
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun config = (config & ~Xcvr) | (dev->if_port << Xcvr_shift);
728*4882a593Smuzhiyun outl(config, ioaddr + Wn3_Config);
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun if (corkscrew_debug > 1) {
731*4882a593Smuzhiyun pr_debug("%s: corkscrew_open() InternalConfig %8.8x.\n",
732*4882a593Smuzhiyun dev->name, config);
733*4882a593Smuzhiyun }
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun outw(TxReset, ioaddr + EL3_CMD);
736*4882a593Smuzhiyun for (i = 20; i >= 0; i--)
737*4882a593Smuzhiyun if (!(inw(ioaddr + EL3_STATUS) & CmdInProgress))
738*4882a593Smuzhiyun break;
739*4882a593Smuzhiyun
740*4882a593Smuzhiyun outw(RxReset, ioaddr + EL3_CMD);
741*4882a593Smuzhiyun /* Wait a few ticks for the RxReset command to complete. */
742*4882a593Smuzhiyun for (i = 20; i >= 0; i--)
743*4882a593Smuzhiyun if (!(inw(ioaddr + EL3_STATUS) & CmdInProgress))
744*4882a593Smuzhiyun break;
745*4882a593Smuzhiyun
746*4882a593Smuzhiyun outw(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun /* Use the now-standard shared IRQ implementation. */
749*4882a593Smuzhiyun if (vp->capabilities == 0x11c7) {
750*4882a593Smuzhiyun /* Corkscrew: Cannot share ISA resources. */
751*4882a593Smuzhiyun if (dev->irq == 0 ||
752*4882a593Smuzhiyun dev->dma == 0 ||
753*4882a593Smuzhiyun request_irq(dev->irq, corkscrew_interrupt, 0,
754*4882a593Smuzhiyun vp->product_name, dev))
755*4882a593Smuzhiyun return -EAGAIN;
756*4882a593Smuzhiyun enable_dma(dev->dma);
757*4882a593Smuzhiyun set_dma_mode(dev->dma, DMA_MODE_CASCADE);
758*4882a593Smuzhiyun } else if (request_irq(dev->irq, corkscrew_interrupt, IRQF_SHARED,
759*4882a593Smuzhiyun vp->product_name, dev)) {
760*4882a593Smuzhiyun return -EAGAIN;
761*4882a593Smuzhiyun }
762*4882a593Smuzhiyun
763*4882a593Smuzhiyun if (armtimer)
764*4882a593Smuzhiyun mod_timer(&vp->timer, jiffies + media_tbl[dev->if_port].wait);
765*4882a593Smuzhiyun
766*4882a593Smuzhiyun if (corkscrew_debug > 1) {
767*4882a593Smuzhiyun EL3WINDOW(4);
768*4882a593Smuzhiyun pr_debug("%s: corkscrew_open() irq %d media status %4.4x.\n",
769*4882a593Smuzhiyun dev->name, dev->irq, inw(ioaddr + Wn4_Media));
770*4882a593Smuzhiyun }
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun /* Set the station address and mask in window 2 each time opened. */
773*4882a593Smuzhiyun EL3WINDOW(2);
774*4882a593Smuzhiyun for (i = 0; i < 6; i++)
775*4882a593Smuzhiyun outb(dev->dev_addr[i], ioaddr + i);
776*4882a593Smuzhiyun for (; i < 12; i += 2)
777*4882a593Smuzhiyun outw(0, ioaddr + i);
778*4882a593Smuzhiyun
779*4882a593Smuzhiyun if (dev->if_port == 3)
780*4882a593Smuzhiyun /* Start the thinnet transceiver. We should really wait 50ms... */
781*4882a593Smuzhiyun outw(StartCoax, ioaddr + EL3_CMD);
782*4882a593Smuzhiyun EL3WINDOW(4);
783*4882a593Smuzhiyun outw((inw(ioaddr + Wn4_Media) & ~(Media_10TP | Media_SQE)) |
784*4882a593Smuzhiyun media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun /* Switch to the stats window, and clear all stats by reading. */
787*4882a593Smuzhiyun outw(StatsDisable, ioaddr + EL3_CMD);
788*4882a593Smuzhiyun EL3WINDOW(6);
789*4882a593Smuzhiyun for (i = 0; i < 10; i++)
790*4882a593Smuzhiyun inb(ioaddr + i);
791*4882a593Smuzhiyun inw(ioaddr + 10);
792*4882a593Smuzhiyun inw(ioaddr + 12);
793*4882a593Smuzhiyun /* New: On the Vortex we must also clear the BadSSD counter. */
794*4882a593Smuzhiyun EL3WINDOW(4);
795*4882a593Smuzhiyun inb(ioaddr + 12);
796*4882a593Smuzhiyun /* ..and on the Boomerang we enable the extra statistics bits. */
797*4882a593Smuzhiyun outw(0x0040, ioaddr + Wn4_NetDiag);
798*4882a593Smuzhiyun
799*4882a593Smuzhiyun /* Switch to register set 7 for normal use. */
800*4882a593Smuzhiyun EL3WINDOW(7);
801*4882a593Smuzhiyun
802*4882a593Smuzhiyun if (vp->full_bus_master_rx) { /* Boomerang bus master. */
803*4882a593Smuzhiyun vp->cur_rx = vp->dirty_rx = 0;
804*4882a593Smuzhiyun if (corkscrew_debug > 2)
805*4882a593Smuzhiyun pr_debug("%s: Filling in the Rx ring.\n", dev->name);
806*4882a593Smuzhiyun for (i = 0; i < RX_RING_SIZE; i++) {
807*4882a593Smuzhiyun struct sk_buff *skb;
808*4882a593Smuzhiyun if (i < (RX_RING_SIZE - 1))
809*4882a593Smuzhiyun vp->rx_ring[i].next =
810*4882a593Smuzhiyun isa_virt_to_bus(&vp->rx_ring[i + 1]);
811*4882a593Smuzhiyun else
812*4882a593Smuzhiyun vp->rx_ring[i].next = 0;
813*4882a593Smuzhiyun vp->rx_ring[i].status = 0; /* Clear complete bit. */
814*4882a593Smuzhiyun vp->rx_ring[i].length = PKT_BUF_SZ | 0x80000000;
815*4882a593Smuzhiyun skb = netdev_alloc_skb(dev, PKT_BUF_SZ);
816*4882a593Smuzhiyun vp->rx_skbuff[i] = skb;
817*4882a593Smuzhiyun if (skb == NULL)
818*4882a593Smuzhiyun break; /* Bad news! */
819*4882a593Smuzhiyun skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
820*4882a593Smuzhiyun vp->rx_ring[i].addr = isa_virt_to_bus(skb->data);
821*4882a593Smuzhiyun }
822*4882a593Smuzhiyun if (i != 0)
823*4882a593Smuzhiyun vp->rx_ring[i - 1].next =
824*4882a593Smuzhiyun isa_virt_to_bus(&vp->rx_ring[0]); /* Wrap the ring. */
825*4882a593Smuzhiyun outl(isa_virt_to_bus(&vp->rx_ring[0]), ioaddr + UpListPtr);
826*4882a593Smuzhiyun }
827*4882a593Smuzhiyun if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
828*4882a593Smuzhiyun vp->cur_tx = vp->dirty_tx = 0;
829*4882a593Smuzhiyun outb(PKT_BUF_SZ >> 8, ioaddr + TxFreeThreshold); /* Room for a packet. */
830*4882a593Smuzhiyun /* Clear the Tx ring. */
831*4882a593Smuzhiyun for (i = 0; i < TX_RING_SIZE; i++)
832*4882a593Smuzhiyun vp->tx_skbuff[i] = NULL;
833*4882a593Smuzhiyun outl(0, ioaddr + DownListPtr);
834*4882a593Smuzhiyun }
835*4882a593Smuzhiyun /* Set receiver mode: presumably accept b-case and phys addr only. */
836*4882a593Smuzhiyun set_rx_mode(dev);
837*4882a593Smuzhiyun outw(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
838*4882a593Smuzhiyun
839*4882a593Smuzhiyun netif_start_queue(dev);
840*4882a593Smuzhiyun
841*4882a593Smuzhiyun outw(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
842*4882a593Smuzhiyun outw(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
843*4882a593Smuzhiyun /* Allow status bits to be seen. */
844*4882a593Smuzhiyun outw(SetStatusEnb | AdapterFailure | IntReq | StatsFull |
845*4882a593Smuzhiyun (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
846*4882a593Smuzhiyun (vp->full_bus_master_rx ? UpComplete : RxComplete) |
847*4882a593Smuzhiyun (vp->bus_master ? DMADone : 0), ioaddr + EL3_CMD);
848*4882a593Smuzhiyun /* Ack all pending events, and set active indicator mask. */
849*4882a593Smuzhiyun outw(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
850*4882a593Smuzhiyun ioaddr + EL3_CMD);
851*4882a593Smuzhiyun outw(SetIntrEnb | IntLatch | TxAvailable | RxComplete | StatsFull
852*4882a593Smuzhiyun | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete,
853*4882a593Smuzhiyun ioaddr + EL3_CMD);
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun return 0;
856*4882a593Smuzhiyun }
857*4882a593Smuzhiyun
corkscrew_timer(struct timer_list * t)858*4882a593Smuzhiyun static void corkscrew_timer(struct timer_list *t)
859*4882a593Smuzhiyun {
860*4882a593Smuzhiyun #ifdef AUTOMEDIA
861*4882a593Smuzhiyun struct corkscrew_private *vp = from_timer(vp, t, timer);
862*4882a593Smuzhiyun struct net_device *dev = vp->our_dev;
863*4882a593Smuzhiyun int ioaddr = dev->base_addr;
864*4882a593Smuzhiyun unsigned long flags;
865*4882a593Smuzhiyun int ok = 0;
866*4882a593Smuzhiyun
867*4882a593Smuzhiyun if (corkscrew_debug > 1)
868*4882a593Smuzhiyun pr_debug("%s: Media selection timer tick happened, %s.\n",
869*4882a593Smuzhiyun dev->name, media_tbl[dev->if_port].name);
870*4882a593Smuzhiyun
871*4882a593Smuzhiyun spin_lock_irqsave(&vp->lock, flags);
872*4882a593Smuzhiyun
873*4882a593Smuzhiyun {
874*4882a593Smuzhiyun int old_window = inw(ioaddr + EL3_CMD) >> 13;
875*4882a593Smuzhiyun int media_status;
876*4882a593Smuzhiyun EL3WINDOW(4);
877*4882a593Smuzhiyun media_status = inw(ioaddr + Wn4_Media);
878*4882a593Smuzhiyun switch (dev->if_port) {
879*4882a593Smuzhiyun case 0:
880*4882a593Smuzhiyun case 4:
881*4882a593Smuzhiyun case 5: /* 10baseT, 100baseTX, 100baseFX */
882*4882a593Smuzhiyun if (media_status & Media_LnkBeat) {
883*4882a593Smuzhiyun ok = 1;
884*4882a593Smuzhiyun if (corkscrew_debug > 1)
885*4882a593Smuzhiyun pr_debug("%s: Media %s has link beat, %x.\n",
886*4882a593Smuzhiyun dev->name,
887*4882a593Smuzhiyun media_tbl[dev->if_port].name,
888*4882a593Smuzhiyun media_status);
889*4882a593Smuzhiyun } else if (corkscrew_debug > 1)
890*4882a593Smuzhiyun pr_debug("%s: Media %s is has no link beat, %x.\n",
891*4882a593Smuzhiyun dev->name,
892*4882a593Smuzhiyun media_tbl[dev->if_port].name,
893*4882a593Smuzhiyun media_status);
894*4882a593Smuzhiyun
895*4882a593Smuzhiyun break;
896*4882a593Smuzhiyun default: /* Other media types handled by Tx timeouts. */
897*4882a593Smuzhiyun if (corkscrew_debug > 1)
898*4882a593Smuzhiyun pr_debug("%s: Media %s is has no indication, %x.\n",
899*4882a593Smuzhiyun dev->name,
900*4882a593Smuzhiyun media_tbl[dev->if_port].name,
901*4882a593Smuzhiyun media_status);
902*4882a593Smuzhiyun ok = 1;
903*4882a593Smuzhiyun }
904*4882a593Smuzhiyun if (!ok) {
905*4882a593Smuzhiyun __u32 config;
906*4882a593Smuzhiyun
907*4882a593Smuzhiyun do {
908*4882a593Smuzhiyun dev->if_port =
909*4882a593Smuzhiyun media_tbl[dev->if_port].next;
910*4882a593Smuzhiyun }
911*4882a593Smuzhiyun while (!(vp->available_media & media_tbl[dev->if_port].mask));
912*4882a593Smuzhiyun
913*4882a593Smuzhiyun if (dev->if_port == 8) { /* Go back to default. */
914*4882a593Smuzhiyun dev->if_port = vp->default_media;
915*4882a593Smuzhiyun if (corkscrew_debug > 1)
916*4882a593Smuzhiyun pr_debug("%s: Media selection failing, using default %s port.\n",
917*4882a593Smuzhiyun dev->name,
918*4882a593Smuzhiyun media_tbl[dev->if_port].name);
919*4882a593Smuzhiyun } else {
920*4882a593Smuzhiyun if (corkscrew_debug > 1)
921*4882a593Smuzhiyun pr_debug("%s: Media selection failed, now trying %s port.\n",
922*4882a593Smuzhiyun dev->name,
923*4882a593Smuzhiyun media_tbl[dev->if_port].name);
924*4882a593Smuzhiyun vp->timer.expires = jiffies + media_tbl[dev->if_port].wait;
925*4882a593Smuzhiyun add_timer(&vp->timer);
926*4882a593Smuzhiyun }
927*4882a593Smuzhiyun outw((media_status & ~(Media_10TP | Media_SQE)) |
928*4882a593Smuzhiyun media_tbl[dev->if_port].media_bits,
929*4882a593Smuzhiyun ioaddr + Wn4_Media);
930*4882a593Smuzhiyun
931*4882a593Smuzhiyun EL3WINDOW(3);
932*4882a593Smuzhiyun config = inl(ioaddr + Wn3_Config);
933*4882a593Smuzhiyun config = (config & ~Xcvr) | (dev->if_port << Xcvr_shift);
934*4882a593Smuzhiyun outl(config, ioaddr + Wn3_Config);
935*4882a593Smuzhiyun
936*4882a593Smuzhiyun outw(dev->if_port == 3 ? StartCoax : StopCoax,
937*4882a593Smuzhiyun ioaddr + EL3_CMD);
938*4882a593Smuzhiyun }
939*4882a593Smuzhiyun EL3WINDOW(old_window);
940*4882a593Smuzhiyun }
941*4882a593Smuzhiyun
942*4882a593Smuzhiyun spin_unlock_irqrestore(&vp->lock, flags);
943*4882a593Smuzhiyun if (corkscrew_debug > 1)
944*4882a593Smuzhiyun pr_debug("%s: Media selection timer finished, %s.\n",
945*4882a593Smuzhiyun dev->name, media_tbl[dev->if_port].name);
946*4882a593Smuzhiyun
947*4882a593Smuzhiyun #endif /* AUTOMEDIA */
948*4882a593Smuzhiyun }
949*4882a593Smuzhiyun
corkscrew_timeout(struct net_device * dev,unsigned int txqueue)950*4882a593Smuzhiyun static void corkscrew_timeout(struct net_device *dev, unsigned int txqueue)
951*4882a593Smuzhiyun {
952*4882a593Smuzhiyun int i;
953*4882a593Smuzhiyun struct corkscrew_private *vp = netdev_priv(dev);
954*4882a593Smuzhiyun int ioaddr = dev->base_addr;
955*4882a593Smuzhiyun
956*4882a593Smuzhiyun pr_warn("%s: transmit timed out, tx_status %2.2x status %4.4x\n",
957*4882a593Smuzhiyun dev->name, inb(ioaddr + TxStatus),
958*4882a593Smuzhiyun inw(ioaddr + EL3_STATUS));
959*4882a593Smuzhiyun /* Slight code bloat to be user friendly. */
960*4882a593Smuzhiyun if ((inb(ioaddr + TxStatus) & 0x88) == 0x88)
961*4882a593Smuzhiyun pr_warn("%s: Transmitter encountered 16 collisions -- network cable problem?\n",
962*4882a593Smuzhiyun dev->name);
963*4882a593Smuzhiyun #ifndef final_version
964*4882a593Smuzhiyun pr_debug(" Flags; bus-master %d, full %d; dirty %d current %d.\n",
965*4882a593Smuzhiyun vp->full_bus_master_tx, vp->tx_full, vp->dirty_tx,
966*4882a593Smuzhiyun vp->cur_tx);
967*4882a593Smuzhiyun pr_debug(" Down list %8.8x vs. %p.\n", inl(ioaddr + DownListPtr),
968*4882a593Smuzhiyun &vp->tx_ring[0]);
969*4882a593Smuzhiyun for (i = 0; i < TX_RING_SIZE; i++) {
970*4882a593Smuzhiyun pr_debug(" %d: %p length %8.8x status %8.8x\n", i,
971*4882a593Smuzhiyun &vp->tx_ring[i],
972*4882a593Smuzhiyun vp->tx_ring[i].length, vp->tx_ring[i].status);
973*4882a593Smuzhiyun }
974*4882a593Smuzhiyun #endif
975*4882a593Smuzhiyun /* Issue TX_RESET and TX_START commands. */
976*4882a593Smuzhiyun outw(TxReset, ioaddr + EL3_CMD);
977*4882a593Smuzhiyun for (i = 20; i >= 0; i--)
978*4882a593Smuzhiyun if (!(inw(ioaddr + EL3_STATUS) & CmdInProgress))
979*4882a593Smuzhiyun break;
980*4882a593Smuzhiyun outw(TxEnable, ioaddr + EL3_CMD);
981*4882a593Smuzhiyun netif_trans_update(dev); /* prevent tx timeout */
982*4882a593Smuzhiyun dev->stats.tx_errors++;
983*4882a593Smuzhiyun dev->stats.tx_dropped++;
984*4882a593Smuzhiyun netif_wake_queue(dev);
985*4882a593Smuzhiyun }
986*4882a593Smuzhiyun
corkscrew_start_xmit(struct sk_buff * skb,struct net_device * dev)987*4882a593Smuzhiyun static netdev_tx_t corkscrew_start_xmit(struct sk_buff *skb,
988*4882a593Smuzhiyun struct net_device *dev)
989*4882a593Smuzhiyun {
990*4882a593Smuzhiyun struct corkscrew_private *vp = netdev_priv(dev);
991*4882a593Smuzhiyun int ioaddr = dev->base_addr;
992*4882a593Smuzhiyun
993*4882a593Smuzhiyun /* Block a timer-based transmit from overlapping. */
994*4882a593Smuzhiyun
995*4882a593Smuzhiyun netif_stop_queue(dev);
996*4882a593Smuzhiyun
997*4882a593Smuzhiyun if (vp->full_bus_master_tx) { /* BOOMERANG bus-master */
998*4882a593Smuzhiyun /* Calculate the next Tx descriptor entry. */
999*4882a593Smuzhiyun int entry = vp->cur_tx % TX_RING_SIZE;
1000*4882a593Smuzhiyun struct boom_tx_desc *prev_entry;
1001*4882a593Smuzhiyun unsigned long flags;
1002*4882a593Smuzhiyun int i;
1003*4882a593Smuzhiyun
1004*4882a593Smuzhiyun if (vp->tx_full) /* No room to transmit with */
1005*4882a593Smuzhiyun return NETDEV_TX_BUSY;
1006*4882a593Smuzhiyun if (vp->cur_tx != 0)
1007*4882a593Smuzhiyun prev_entry = &vp->tx_ring[(vp->cur_tx - 1) % TX_RING_SIZE];
1008*4882a593Smuzhiyun else
1009*4882a593Smuzhiyun prev_entry = NULL;
1010*4882a593Smuzhiyun if (corkscrew_debug > 3)
1011*4882a593Smuzhiyun pr_debug("%s: Trying to send a packet, Tx index %d.\n",
1012*4882a593Smuzhiyun dev->name, vp->cur_tx);
1013*4882a593Smuzhiyun /* vp->tx_full = 1; */
1014*4882a593Smuzhiyun vp->tx_skbuff[entry] = skb;
1015*4882a593Smuzhiyun vp->tx_ring[entry].next = 0;
1016*4882a593Smuzhiyun vp->tx_ring[entry].addr = isa_virt_to_bus(skb->data);
1017*4882a593Smuzhiyun vp->tx_ring[entry].length = skb->len | 0x80000000;
1018*4882a593Smuzhiyun vp->tx_ring[entry].status = skb->len | 0x80000000;
1019*4882a593Smuzhiyun
1020*4882a593Smuzhiyun spin_lock_irqsave(&vp->lock, flags);
1021*4882a593Smuzhiyun outw(DownStall, ioaddr + EL3_CMD);
1022*4882a593Smuzhiyun /* Wait for the stall to complete. */
1023*4882a593Smuzhiyun for (i = 20; i >= 0; i--)
1024*4882a593Smuzhiyun if ((inw(ioaddr + EL3_STATUS) & CmdInProgress) == 0)
1025*4882a593Smuzhiyun break;
1026*4882a593Smuzhiyun if (prev_entry)
1027*4882a593Smuzhiyun prev_entry->next = isa_virt_to_bus(&vp->tx_ring[entry]);
1028*4882a593Smuzhiyun if (inl(ioaddr + DownListPtr) == 0) {
1029*4882a593Smuzhiyun outl(isa_virt_to_bus(&vp->tx_ring[entry]),
1030*4882a593Smuzhiyun ioaddr + DownListPtr);
1031*4882a593Smuzhiyun queued_packet++;
1032*4882a593Smuzhiyun }
1033*4882a593Smuzhiyun outw(DownUnstall, ioaddr + EL3_CMD);
1034*4882a593Smuzhiyun spin_unlock_irqrestore(&vp->lock, flags);
1035*4882a593Smuzhiyun
1036*4882a593Smuzhiyun vp->cur_tx++;
1037*4882a593Smuzhiyun if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1)
1038*4882a593Smuzhiyun vp->tx_full = 1;
1039*4882a593Smuzhiyun else { /* Clear previous interrupt enable. */
1040*4882a593Smuzhiyun if (prev_entry)
1041*4882a593Smuzhiyun prev_entry->status &= ~0x80000000;
1042*4882a593Smuzhiyun netif_wake_queue(dev);
1043*4882a593Smuzhiyun }
1044*4882a593Smuzhiyun return NETDEV_TX_OK;
1045*4882a593Smuzhiyun }
1046*4882a593Smuzhiyun /* Put out the doubleword header... */
1047*4882a593Smuzhiyun outl(skb->len, ioaddr + TX_FIFO);
1048*4882a593Smuzhiyun dev->stats.tx_bytes += skb->len;
1049*4882a593Smuzhiyun #ifdef VORTEX_BUS_MASTER
1050*4882a593Smuzhiyun if (vp->bus_master) {
1051*4882a593Smuzhiyun /* Set the bus-master controller to transfer the packet. */
1052*4882a593Smuzhiyun outl((int) (skb->data), ioaddr + Wn7_MasterAddr);
1053*4882a593Smuzhiyun outw((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
1054*4882a593Smuzhiyun vp->tx_skb = skb;
1055*4882a593Smuzhiyun outw(StartDMADown, ioaddr + EL3_CMD);
1056*4882a593Smuzhiyun /* queue will be woken at the DMADone interrupt. */
1057*4882a593Smuzhiyun } else {
1058*4882a593Smuzhiyun /* ... and the packet rounded to a doubleword. */
1059*4882a593Smuzhiyun outsl(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
1060*4882a593Smuzhiyun dev_kfree_skb(skb);
1061*4882a593Smuzhiyun if (inw(ioaddr + TxFree) > 1536) {
1062*4882a593Smuzhiyun netif_wake_queue(dev);
1063*4882a593Smuzhiyun } else
1064*4882a593Smuzhiyun /* Interrupt us when the FIFO has room for max-sized packet. */
1065*4882a593Smuzhiyun outw(SetTxThreshold + (1536 >> 2),
1066*4882a593Smuzhiyun ioaddr + EL3_CMD);
1067*4882a593Smuzhiyun }
1068*4882a593Smuzhiyun #else
1069*4882a593Smuzhiyun /* ... and the packet rounded to a doubleword. */
1070*4882a593Smuzhiyun outsl(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
1071*4882a593Smuzhiyun dev_kfree_skb(skb);
1072*4882a593Smuzhiyun if (inw(ioaddr + TxFree) > 1536) {
1073*4882a593Smuzhiyun netif_wake_queue(dev);
1074*4882a593Smuzhiyun } else
1075*4882a593Smuzhiyun /* Interrupt us when the FIFO has room for max-sized packet. */
1076*4882a593Smuzhiyun outw(SetTxThreshold + (1536 >> 2), ioaddr + EL3_CMD);
1077*4882a593Smuzhiyun #endif /* bus master */
1078*4882a593Smuzhiyun
1079*4882a593Smuzhiyun
1080*4882a593Smuzhiyun /* Clear the Tx status stack. */
1081*4882a593Smuzhiyun {
1082*4882a593Smuzhiyun short tx_status;
1083*4882a593Smuzhiyun int i = 4;
1084*4882a593Smuzhiyun
1085*4882a593Smuzhiyun while (--i > 0 && (tx_status = inb(ioaddr + TxStatus)) > 0) {
1086*4882a593Smuzhiyun if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
1087*4882a593Smuzhiyun if (corkscrew_debug > 2)
1088*4882a593Smuzhiyun pr_debug("%s: Tx error, status %2.2x.\n",
1089*4882a593Smuzhiyun dev->name, tx_status);
1090*4882a593Smuzhiyun if (tx_status & 0x04)
1091*4882a593Smuzhiyun dev->stats.tx_fifo_errors++;
1092*4882a593Smuzhiyun if (tx_status & 0x38)
1093*4882a593Smuzhiyun dev->stats.tx_aborted_errors++;
1094*4882a593Smuzhiyun if (tx_status & 0x30) {
1095*4882a593Smuzhiyun int j;
1096*4882a593Smuzhiyun outw(TxReset, ioaddr + EL3_CMD);
1097*4882a593Smuzhiyun for (j = 20; j >= 0; j--)
1098*4882a593Smuzhiyun if (!(inw(ioaddr + EL3_STATUS) & CmdInProgress))
1099*4882a593Smuzhiyun break;
1100*4882a593Smuzhiyun }
1101*4882a593Smuzhiyun outw(TxEnable, ioaddr + EL3_CMD);
1102*4882a593Smuzhiyun }
1103*4882a593Smuzhiyun outb(0x00, ioaddr + TxStatus); /* Pop the status stack. */
1104*4882a593Smuzhiyun }
1105*4882a593Smuzhiyun }
1106*4882a593Smuzhiyun return NETDEV_TX_OK;
1107*4882a593Smuzhiyun }
1108*4882a593Smuzhiyun
1109*4882a593Smuzhiyun /* The interrupt handler does all of the Rx thread work and cleans up
1110*4882a593Smuzhiyun after the Tx thread. */
1111*4882a593Smuzhiyun
corkscrew_interrupt(int irq,void * dev_id)1112*4882a593Smuzhiyun static irqreturn_t corkscrew_interrupt(int irq, void *dev_id)
1113*4882a593Smuzhiyun {
1114*4882a593Smuzhiyun /* Use the now-standard shared IRQ implementation. */
1115*4882a593Smuzhiyun struct net_device *dev = dev_id;
1116*4882a593Smuzhiyun struct corkscrew_private *lp = netdev_priv(dev);
1117*4882a593Smuzhiyun int ioaddr, status;
1118*4882a593Smuzhiyun int latency;
1119*4882a593Smuzhiyun int i = max_interrupt_work;
1120*4882a593Smuzhiyun
1121*4882a593Smuzhiyun ioaddr = dev->base_addr;
1122*4882a593Smuzhiyun latency = inb(ioaddr + Timer);
1123*4882a593Smuzhiyun
1124*4882a593Smuzhiyun spin_lock(&lp->lock);
1125*4882a593Smuzhiyun
1126*4882a593Smuzhiyun status = inw(ioaddr + EL3_STATUS);
1127*4882a593Smuzhiyun
1128*4882a593Smuzhiyun if (corkscrew_debug > 4)
1129*4882a593Smuzhiyun pr_debug("%s: interrupt, status %4.4x, timer %d.\n",
1130*4882a593Smuzhiyun dev->name, status, latency);
1131*4882a593Smuzhiyun if ((status & 0xE000) != 0xE000) {
1132*4882a593Smuzhiyun static int donedidthis;
1133*4882a593Smuzhiyun /* Some interrupt controllers store a bogus interrupt from boot-time.
1134*4882a593Smuzhiyun Ignore a single early interrupt, but don't hang the machine for
1135*4882a593Smuzhiyun other interrupt problems. */
1136*4882a593Smuzhiyun if (donedidthis++ > 100) {
1137*4882a593Smuzhiyun pr_err("%s: Bogus interrupt, bailing. Status %4.4x, start=%d.\n",
1138*4882a593Smuzhiyun dev->name, status, netif_running(dev));
1139*4882a593Smuzhiyun free_irq(dev->irq, dev);
1140*4882a593Smuzhiyun dev->irq = -1;
1141*4882a593Smuzhiyun }
1142*4882a593Smuzhiyun }
1143*4882a593Smuzhiyun
1144*4882a593Smuzhiyun do {
1145*4882a593Smuzhiyun if (corkscrew_debug > 5)
1146*4882a593Smuzhiyun pr_debug("%s: In interrupt loop, status %4.4x.\n",
1147*4882a593Smuzhiyun dev->name, status);
1148*4882a593Smuzhiyun if (status & RxComplete)
1149*4882a593Smuzhiyun corkscrew_rx(dev);
1150*4882a593Smuzhiyun
1151*4882a593Smuzhiyun if (status & TxAvailable) {
1152*4882a593Smuzhiyun if (corkscrew_debug > 5)
1153*4882a593Smuzhiyun pr_debug(" TX room bit was handled.\n");
1154*4882a593Smuzhiyun /* There's room in the FIFO for a full-sized packet. */
1155*4882a593Smuzhiyun outw(AckIntr | TxAvailable, ioaddr + EL3_CMD);
1156*4882a593Smuzhiyun netif_wake_queue(dev);
1157*4882a593Smuzhiyun }
1158*4882a593Smuzhiyun if (status & DownComplete) {
1159*4882a593Smuzhiyun unsigned int dirty_tx = lp->dirty_tx;
1160*4882a593Smuzhiyun
1161*4882a593Smuzhiyun while (lp->cur_tx - dirty_tx > 0) {
1162*4882a593Smuzhiyun int entry = dirty_tx % TX_RING_SIZE;
1163*4882a593Smuzhiyun if (inl(ioaddr + DownListPtr) == isa_virt_to_bus(&lp->tx_ring[entry]))
1164*4882a593Smuzhiyun break; /* It still hasn't been processed. */
1165*4882a593Smuzhiyun if (lp->tx_skbuff[entry]) {
1166*4882a593Smuzhiyun dev_consume_skb_irq(lp->tx_skbuff[entry]);
1167*4882a593Smuzhiyun lp->tx_skbuff[entry] = NULL;
1168*4882a593Smuzhiyun }
1169*4882a593Smuzhiyun dirty_tx++;
1170*4882a593Smuzhiyun }
1171*4882a593Smuzhiyun lp->dirty_tx = dirty_tx;
1172*4882a593Smuzhiyun outw(AckIntr | DownComplete, ioaddr + EL3_CMD);
1173*4882a593Smuzhiyun if (lp->tx_full && (lp->cur_tx - dirty_tx <= TX_RING_SIZE - 1)) {
1174*4882a593Smuzhiyun lp->tx_full = 0;
1175*4882a593Smuzhiyun netif_wake_queue(dev);
1176*4882a593Smuzhiyun }
1177*4882a593Smuzhiyun }
1178*4882a593Smuzhiyun #ifdef VORTEX_BUS_MASTER
1179*4882a593Smuzhiyun if (status & DMADone) {
1180*4882a593Smuzhiyun outw(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
1181*4882a593Smuzhiyun dev_consume_skb_irq(lp->tx_skb); /* Release the transferred buffer */
1182*4882a593Smuzhiyun netif_wake_queue(dev);
1183*4882a593Smuzhiyun }
1184*4882a593Smuzhiyun #endif
1185*4882a593Smuzhiyun if (status & UpComplete) {
1186*4882a593Smuzhiyun boomerang_rx(dev);
1187*4882a593Smuzhiyun outw(AckIntr | UpComplete, ioaddr + EL3_CMD);
1188*4882a593Smuzhiyun }
1189*4882a593Smuzhiyun if (status & (AdapterFailure | RxEarly | StatsFull)) {
1190*4882a593Smuzhiyun /* Handle all uncommon interrupts at once. */
1191*4882a593Smuzhiyun if (status & RxEarly) { /* Rx early is unused. */
1192*4882a593Smuzhiyun corkscrew_rx(dev);
1193*4882a593Smuzhiyun outw(AckIntr | RxEarly, ioaddr + EL3_CMD);
1194*4882a593Smuzhiyun }
1195*4882a593Smuzhiyun if (status & StatsFull) { /* Empty statistics. */
1196*4882a593Smuzhiyun static int DoneDidThat;
1197*4882a593Smuzhiyun if (corkscrew_debug > 4)
1198*4882a593Smuzhiyun pr_debug("%s: Updating stats.\n", dev->name);
1199*4882a593Smuzhiyun update_stats(ioaddr, dev);
1200*4882a593Smuzhiyun /* DEBUG HACK: Disable statistics as an interrupt source. */
1201*4882a593Smuzhiyun /* This occurs when we have the wrong media type! */
1202*4882a593Smuzhiyun if (DoneDidThat == 0 && inw(ioaddr + EL3_STATUS) & StatsFull) {
1203*4882a593Smuzhiyun int win, reg;
1204*4882a593Smuzhiyun pr_notice("%s: Updating stats failed, disabling stats as an interrupt source.\n",
1205*4882a593Smuzhiyun dev->name);
1206*4882a593Smuzhiyun for (win = 0; win < 8; win++) {
1207*4882a593Smuzhiyun EL3WINDOW(win);
1208*4882a593Smuzhiyun pr_notice("Vortex window %d:", win);
1209*4882a593Smuzhiyun for (reg = 0; reg < 16; reg++)
1210*4882a593Smuzhiyun pr_cont(" %2.2x", inb(ioaddr + reg));
1211*4882a593Smuzhiyun pr_cont("\n");
1212*4882a593Smuzhiyun }
1213*4882a593Smuzhiyun EL3WINDOW(7);
1214*4882a593Smuzhiyun outw(SetIntrEnb | TxAvailable |
1215*4882a593Smuzhiyun RxComplete | AdapterFailure |
1216*4882a593Smuzhiyun UpComplete | DownComplete |
1217*4882a593Smuzhiyun TxComplete, ioaddr + EL3_CMD);
1218*4882a593Smuzhiyun DoneDidThat++;
1219*4882a593Smuzhiyun }
1220*4882a593Smuzhiyun }
1221*4882a593Smuzhiyun if (status & AdapterFailure) {
1222*4882a593Smuzhiyun /* Adapter failure requires Rx reset and reinit. */
1223*4882a593Smuzhiyun outw(RxReset, ioaddr + EL3_CMD);
1224*4882a593Smuzhiyun /* Set the Rx filter to the current state. */
1225*4882a593Smuzhiyun set_rx_mode(dev);
1226*4882a593Smuzhiyun outw(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
1227*4882a593Smuzhiyun outw(AckIntr | AdapterFailure,
1228*4882a593Smuzhiyun ioaddr + EL3_CMD);
1229*4882a593Smuzhiyun }
1230*4882a593Smuzhiyun }
1231*4882a593Smuzhiyun
1232*4882a593Smuzhiyun if (--i < 0) {
1233*4882a593Smuzhiyun pr_err("%s: Too much work in interrupt, status %4.4x. Disabling functions (%4.4x).\n",
1234*4882a593Smuzhiyun dev->name, status, SetStatusEnb | ((~status) & 0x7FE));
1235*4882a593Smuzhiyun /* Disable all pending interrupts. */
1236*4882a593Smuzhiyun outw(SetStatusEnb | ((~status) & 0x7FE), ioaddr + EL3_CMD);
1237*4882a593Smuzhiyun outw(AckIntr | 0x7FF, ioaddr + EL3_CMD);
1238*4882a593Smuzhiyun break;
1239*4882a593Smuzhiyun }
1240*4882a593Smuzhiyun /* Acknowledge the IRQ. */
1241*4882a593Smuzhiyun outw(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
1242*4882a593Smuzhiyun
1243*4882a593Smuzhiyun } while ((status = inw(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
1244*4882a593Smuzhiyun
1245*4882a593Smuzhiyun spin_unlock(&lp->lock);
1246*4882a593Smuzhiyun
1247*4882a593Smuzhiyun if (corkscrew_debug > 4)
1248*4882a593Smuzhiyun pr_debug("%s: exiting interrupt, status %4.4x.\n", dev->name, status);
1249*4882a593Smuzhiyun return IRQ_HANDLED;
1250*4882a593Smuzhiyun }
1251*4882a593Smuzhiyun
corkscrew_rx(struct net_device * dev)1252*4882a593Smuzhiyun static int corkscrew_rx(struct net_device *dev)
1253*4882a593Smuzhiyun {
1254*4882a593Smuzhiyun int ioaddr = dev->base_addr;
1255*4882a593Smuzhiyun int i;
1256*4882a593Smuzhiyun short rx_status;
1257*4882a593Smuzhiyun
1258*4882a593Smuzhiyun if (corkscrew_debug > 5)
1259*4882a593Smuzhiyun pr_debug(" In rx_packet(), status %4.4x, rx_status %4.4x.\n",
1260*4882a593Smuzhiyun inw(ioaddr + EL3_STATUS), inw(ioaddr + RxStatus));
1261*4882a593Smuzhiyun while ((rx_status = inw(ioaddr + RxStatus)) > 0) {
1262*4882a593Smuzhiyun if (rx_status & 0x4000) { /* Error, update stats. */
1263*4882a593Smuzhiyun unsigned char rx_error = inb(ioaddr + RxErrors);
1264*4882a593Smuzhiyun if (corkscrew_debug > 2)
1265*4882a593Smuzhiyun pr_debug(" Rx error: status %2.2x.\n",
1266*4882a593Smuzhiyun rx_error);
1267*4882a593Smuzhiyun dev->stats.rx_errors++;
1268*4882a593Smuzhiyun if (rx_error & 0x01)
1269*4882a593Smuzhiyun dev->stats.rx_over_errors++;
1270*4882a593Smuzhiyun if (rx_error & 0x02)
1271*4882a593Smuzhiyun dev->stats.rx_length_errors++;
1272*4882a593Smuzhiyun if (rx_error & 0x04)
1273*4882a593Smuzhiyun dev->stats.rx_frame_errors++;
1274*4882a593Smuzhiyun if (rx_error & 0x08)
1275*4882a593Smuzhiyun dev->stats.rx_crc_errors++;
1276*4882a593Smuzhiyun if (rx_error & 0x10)
1277*4882a593Smuzhiyun dev->stats.rx_length_errors++;
1278*4882a593Smuzhiyun } else {
1279*4882a593Smuzhiyun /* The packet length: up to 4.5K!. */
1280*4882a593Smuzhiyun short pkt_len = rx_status & 0x1fff;
1281*4882a593Smuzhiyun struct sk_buff *skb;
1282*4882a593Smuzhiyun
1283*4882a593Smuzhiyun skb = netdev_alloc_skb(dev, pkt_len + 5 + 2);
1284*4882a593Smuzhiyun if (corkscrew_debug > 4)
1285*4882a593Smuzhiyun pr_debug("Receiving packet size %d status %4.4x.\n",
1286*4882a593Smuzhiyun pkt_len, rx_status);
1287*4882a593Smuzhiyun if (skb != NULL) {
1288*4882a593Smuzhiyun skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1289*4882a593Smuzhiyun /* 'skb_put()' points to the start of sk_buff data area. */
1290*4882a593Smuzhiyun insl(ioaddr + RX_FIFO,
1291*4882a593Smuzhiyun skb_put(skb, pkt_len),
1292*4882a593Smuzhiyun (pkt_len + 3) >> 2);
1293*4882a593Smuzhiyun outw(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
1294*4882a593Smuzhiyun skb->protocol = eth_type_trans(skb, dev);
1295*4882a593Smuzhiyun netif_rx(skb);
1296*4882a593Smuzhiyun dev->stats.rx_packets++;
1297*4882a593Smuzhiyun dev->stats.rx_bytes += pkt_len;
1298*4882a593Smuzhiyun /* Wait a limited time to go to next packet. */
1299*4882a593Smuzhiyun for (i = 200; i >= 0; i--)
1300*4882a593Smuzhiyun if (! (inw(ioaddr + EL3_STATUS) & CmdInProgress))
1301*4882a593Smuzhiyun break;
1302*4882a593Smuzhiyun continue;
1303*4882a593Smuzhiyun } else if (corkscrew_debug)
1304*4882a593Smuzhiyun pr_debug("%s: Couldn't allocate a sk_buff of size %d.\n", dev->name, pkt_len);
1305*4882a593Smuzhiyun }
1306*4882a593Smuzhiyun outw(RxDiscard, ioaddr + EL3_CMD);
1307*4882a593Smuzhiyun dev->stats.rx_dropped++;
1308*4882a593Smuzhiyun /* Wait a limited time to skip this packet. */
1309*4882a593Smuzhiyun for (i = 200; i >= 0; i--)
1310*4882a593Smuzhiyun if (!(inw(ioaddr + EL3_STATUS) & CmdInProgress))
1311*4882a593Smuzhiyun break;
1312*4882a593Smuzhiyun }
1313*4882a593Smuzhiyun return 0;
1314*4882a593Smuzhiyun }
1315*4882a593Smuzhiyun
boomerang_rx(struct net_device * dev)1316*4882a593Smuzhiyun static int boomerang_rx(struct net_device *dev)
1317*4882a593Smuzhiyun {
1318*4882a593Smuzhiyun struct corkscrew_private *vp = netdev_priv(dev);
1319*4882a593Smuzhiyun int entry = vp->cur_rx % RX_RING_SIZE;
1320*4882a593Smuzhiyun int ioaddr = dev->base_addr;
1321*4882a593Smuzhiyun int rx_status;
1322*4882a593Smuzhiyun
1323*4882a593Smuzhiyun if (corkscrew_debug > 5)
1324*4882a593Smuzhiyun pr_debug(" In boomerang_rx(), status %4.4x, rx_status %4.4x.\n",
1325*4882a593Smuzhiyun inw(ioaddr + EL3_STATUS), inw(ioaddr + RxStatus));
1326*4882a593Smuzhiyun while ((rx_status = vp->rx_ring[entry].status) & RxDComplete) {
1327*4882a593Smuzhiyun if (rx_status & RxDError) { /* Error, update stats. */
1328*4882a593Smuzhiyun unsigned char rx_error = rx_status >> 16;
1329*4882a593Smuzhiyun if (corkscrew_debug > 2)
1330*4882a593Smuzhiyun pr_debug(" Rx error: status %2.2x.\n",
1331*4882a593Smuzhiyun rx_error);
1332*4882a593Smuzhiyun dev->stats.rx_errors++;
1333*4882a593Smuzhiyun if (rx_error & 0x01)
1334*4882a593Smuzhiyun dev->stats.rx_over_errors++;
1335*4882a593Smuzhiyun if (rx_error & 0x02)
1336*4882a593Smuzhiyun dev->stats.rx_length_errors++;
1337*4882a593Smuzhiyun if (rx_error & 0x04)
1338*4882a593Smuzhiyun dev->stats.rx_frame_errors++;
1339*4882a593Smuzhiyun if (rx_error & 0x08)
1340*4882a593Smuzhiyun dev->stats.rx_crc_errors++;
1341*4882a593Smuzhiyun if (rx_error & 0x10)
1342*4882a593Smuzhiyun dev->stats.rx_length_errors++;
1343*4882a593Smuzhiyun } else {
1344*4882a593Smuzhiyun /* The packet length: up to 4.5K!. */
1345*4882a593Smuzhiyun short pkt_len = rx_status & 0x1fff;
1346*4882a593Smuzhiyun struct sk_buff *skb;
1347*4882a593Smuzhiyun
1348*4882a593Smuzhiyun dev->stats.rx_bytes += pkt_len;
1349*4882a593Smuzhiyun if (corkscrew_debug > 4)
1350*4882a593Smuzhiyun pr_debug("Receiving packet size %d status %4.4x.\n",
1351*4882a593Smuzhiyun pkt_len, rx_status);
1352*4882a593Smuzhiyun
1353*4882a593Smuzhiyun /* Check if the packet is long enough to just accept without
1354*4882a593Smuzhiyun copying to a properly sized skbuff. */
1355*4882a593Smuzhiyun if (pkt_len < rx_copybreak &&
1356*4882a593Smuzhiyun (skb = netdev_alloc_skb(dev, pkt_len + 4)) != NULL) {
1357*4882a593Smuzhiyun skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1358*4882a593Smuzhiyun /* 'skb_put()' points to the start of sk_buff data area. */
1359*4882a593Smuzhiyun skb_put_data(skb,
1360*4882a593Smuzhiyun isa_bus_to_virt(vp->rx_ring[entry].addr),
1361*4882a593Smuzhiyun pkt_len);
1362*4882a593Smuzhiyun rx_copy++;
1363*4882a593Smuzhiyun } else {
1364*4882a593Smuzhiyun void *temp;
1365*4882a593Smuzhiyun /* Pass up the skbuff already on the Rx ring. */
1366*4882a593Smuzhiyun skb = vp->rx_skbuff[entry];
1367*4882a593Smuzhiyun vp->rx_skbuff[entry] = NULL;
1368*4882a593Smuzhiyun temp = skb_put(skb, pkt_len);
1369*4882a593Smuzhiyun /* Remove this checking code for final release. */
1370*4882a593Smuzhiyun if (isa_bus_to_virt(vp->rx_ring[entry].addr) != temp)
1371*4882a593Smuzhiyun pr_warn("%s: Warning -- the skbuff addresses do not match in boomerang_rx: %p vs. %p / %p\n",
1372*4882a593Smuzhiyun dev->name,
1373*4882a593Smuzhiyun isa_bus_to_virt(vp->rx_ring[entry].addr),
1374*4882a593Smuzhiyun skb->head, temp);
1375*4882a593Smuzhiyun rx_nocopy++;
1376*4882a593Smuzhiyun }
1377*4882a593Smuzhiyun skb->protocol = eth_type_trans(skb, dev);
1378*4882a593Smuzhiyun netif_rx(skb);
1379*4882a593Smuzhiyun dev->stats.rx_packets++;
1380*4882a593Smuzhiyun }
1381*4882a593Smuzhiyun entry = (++vp->cur_rx) % RX_RING_SIZE;
1382*4882a593Smuzhiyun }
1383*4882a593Smuzhiyun /* Refill the Rx ring buffers. */
1384*4882a593Smuzhiyun for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
1385*4882a593Smuzhiyun struct sk_buff *skb;
1386*4882a593Smuzhiyun entry = vp->dirty_rx % RX_RING_SIZE;
1387*4882a593Smuzhiyun if (vp->rx_skbuff[entry] == NULL) {
1388*4882a593Smuzhiyun skb = netdev_alloc_skb(dev, PKT_BUF_SZ);
1389*4882a593Smuzhiyun if (skb == NULL)
1390*4882a593Smuzhiyun break; /* Bad news! */
1391*4882a593Smuzhiyun skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1392*4882a593Smuzhiyun vp->rx_ring[entry].addr = isa_virt_to_bus(skb->data);
1393*4882a593Smuzhiyun vp->rx_skbuff[entry] = skb;
1394*4882a593Smuzhiyun }
1395*4882a593Smuzhiyun vp->rx_ring[entry].status = 0; /* Clear complete bit. */
1396*4882a593Smuzhiyun }
1397*4882a593Smuzhiyun return 0;
1398*4882a593Smuzhiyun }
1399*4882a593Smuzhiyun
corkscrew_close(struct net_device * dev)1400*4882a593Smuzhiyun static int corkscrew_close(struct net_device *dev)
1401*4882a593Smuzhiyun {
1402*4882a593Smuzhiyun struct corkscrew_private *vp = netdev_priv(dev);
1403*4882a593Smuzhiyun int ioaddr = dev->base_addr;
1404*4882a593Smuzhiyun int i;
1405*4882a593Smuzhiyun
1406*4882a593Smuzhiyun netif_stop_queue(dev);
1407*4882a593Smuzhiyun
1408*4882a593Smuzhiyun if (corkscrew_debug > 1) {
1409*4882a593Smuzhiyun pr_debug("%s: corkscrew_close() status %4.4x, Tx status %2.2x.\n",
1410*4882a593Smuzhiyun dev->name, inw(ioaddr + EL3_STATUS),
1411*4882a593Smuzhiyun inb(ioaddr + TxStatus));
1412*4882a593Smuzhiyun pr_debug("%s: corkscrew close stats: rx_nocopy %d rx_copy %d tx_queued %d.\n",
1413*4882a593Smuzhiyun dev->name, rx_nocopy, rx_copy, queued_packet);
1414*4882a593Smuzhiyun }
1415*4882a593Smuzhiyun
1416*4882a593Smuzhiyun del_timer_sync(&vp->timer);
1417*4882a593Smuzhiyun
1418*4882a593Smuzhiyun /* Turn off statistics ASAP. We update lp->stats below. */
1419*4882a593Smuzhiyun outw(StatsDisable, ioaddr + EL3_CMD);
1420*4882a593Smuzhiyun
1421*4882a593Smuzhiyun /* Disable the receiver and transmitter. */
1422*4882a593Smuzhiyun outw(RxDisable, ioaddr + EL3_CMD);
1423*4882a593Smuzhiyun outw(TxDisable, ioaddr + EL3_CMD);
1424*4882a593Smuzhiyun
1425*4882a593Smuzhiyun if (dev->if_port == XCVR_10base2)
1426*4882a593Smuzhiyun /* Turn off thinnet power. Green! */
1427*4882a593Smuzhiyun outw(StopCoax, ioaddr + EL3_CMD);
1428*4882a593Smuzhiyun
1429*4882a593Smuzhiyun free_irq(dev->irq, dev);
1430*4882a593Smuzhiyun
1431*4882a593Smuzhiyun outw(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
1432*4882a593Smuzhiyun
1433*4882a593Smuzhiyun update_stats(ioaddr, dev);
1434*4882a593Smuzhiyun if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
1435*4882a593Smuzhiyun outl(0, ioaddr + UpListPtr);
1436*4882a593Smuzhiyun for (i = 0; i < RX_RING_SIZE; i++)
1437*4882a593Smuzhiyun if (vp->rx_skbuff[i]) {
1438*4882a593Smuzhiyun dev_kfree_skb(vp->rx_skbuff[i]);
1439*4882a593Smuzhiyun vp->rx_skbuff[i] = NULL;
1440*4882a593Smuzhiyun }
1441*4882a593Smuzhiyun }
1442*4882a593Smuzhiyun if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
1443*4882a593Smuzhiyun outl(0, ioaddr + DownListPtr);
1444*4882a593Smuzhiyun for (i = 0; i < TX_RING_SIZE; i++)
1445*4882a593Smuzhiyun if (vp->tx_skbuff[i]) {
1446*4882a593Smuzhiyun dev_kfree_skb(vp->tx_skbuff[i]);
1447*4882a593Smuzhiyun vp->tx_skbuff[i] = NULL;
1448*4882a593Smuzhiyun }
1449*4882a593Smuzhiyun }
1450*4882a593Smuzhiyun
1451*4882a593Smuzhiyun return 0;
1452*4882a593Smuzhiyun }
1453*4882a593Smuzhiyun
corkscrew_get_stats(struct net_device * dev)1454*4882a593Smuzhiyun static struct net_device_stats *corkscrew_get_stats(struct net_device *dev)
1455*4882a593Smuzhiyun {
1456*4882a593Smuzhiyun struct corkscrew_private *vp = netdev_priv(dev);
1457*4882a593Smuzhiyun unsigned long flags;
1458*4882a593Smuzhiyun
1459*4882a593Smuzhiyun if (netif_running(dev)) {
1460*4882a593Smuzhiyun spin_lock_irqsave(&vp->lock, flags);
1461*4882a593Smuzhiyun update_stats(dev->base_addr, dev);
1462*4882a593Smuzhiyun spin_unlock_irqrestore(&vp->lock, flags);
1463*4882a593Smuzhiyun }
1464*4882a593Smuzhiyun return &dev->stats;
1465*4882a593Smuzhiyun }
1466*4882a593Smuzhiyun
1467*4882a593Smuzhiyun /* Update statistics.
1468*4882a593Smuzhiyun Unlike with the EL3 we need not worry about interrupts changing
1469*4882a593Smuzhiyun the window setting from underneath us, but we must still guard
1470*4882a593Smuzhiyun against a race condition with a StatsUpdate interrupt updating the
1471*4882a593Smuzhiyun table. This is done by checking that the ASM (!) code generated uses
1472*4882a593Smuzhiyun atomic updates with '+='.
1473*4882a593Smuzhiyun */
update_stats(int ioaddr,struct net_device * dev)1474*4882a593Smuzhiyun static void update_stats(int ioaddr, struct net_device *dev)
1475*4882a593Smuzhiyun {
1476*4882a593Smuzhiyun /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
1477*4882a593Smuzhiyun /* Switch to the stats window, and read everything. */
1478*4882a593Smuzhiyun EL3WINDOW(6);
1479*4882a593Smuzhiyun dev->stats.tx_carrier_errors += inb(ioaddr + 0);
1480*4882a593Smuzhiyun dev->stats.tx_heartbeat_errors += inb(ioaddr + 1);
1481*4882a593Smuzhiyun /* Multiple collisions. */ inb(ioaddr + 2);
1482*4882a593Smuzhiyun dev->stats.collisions += inb(ioaddr + 3);
1483*4882a593Smuzhiyun dev->stats.tx_window_errors += inb(ioaddr + 4);
1484*4882a593Smuzhiyun dev->stats.rx_fifo_errors += inb(ioaddr + 5);
1485*4882a593Smuzhiyun dev->stats.tx_packets += inb(ioaddr + 6);
1486*4882a593Smuzhiyun dev->stats.tx_packets += (inb(ioaddr + 9) & 0x30) << 4;
1487*4882a593Smuzhiyun /* Rx packets */ inb(ioaddr + 7);
1488*4882a593Smuzhiyun /* Must read to clear */
1489*4882a593Smuzhiyun /* Tx deferrals */ inb(ioaddr + 8);
1490*4882a593Smuzhiyun /* Don't bother with register 9, an extension of registers 6&7.
1491*4882a593Smuzhiyun If we do use the 6&7 values the atomic update assumption above
1492*4882a593Smuzhiyun is invalid. */
1493*4882a593Smuzhiyun inw(ioaddr + 10); /* Total Rx and Tx octets. */
1494*4882a593Smuzhiyun inw(ioaddr + 12);
1495*4882a593Smuzhiyun /* New: On the Vortex we must also clear the BadSSD counter. */
1496*4882a593Smuzhiyun EL3WINDOW(4);
1497*4882a593Smuzhiyun inb(ioaddr + 12);
1498*4882a593Smuzhiyun
1499*4882a593Smuzhiyun /* We change back to window 7 (not 1) with the Vortex. */
1500*4882a593Smuzhiyun EL3WINDOW(7);
1501*4882a593Smuzhiyun }
1502*4882a593Smuzhiyun
1503*4882a593Smuzhiyun /* This new version of set_rx_mode() supports v1.4 kernels.
1504*4882a593Smuzhiyun The Vortex chip has no documented multicast filter, so the only
1505*4882a593Smuzhiyun multicast setting is to receive all multicast frames. At least
1506*4882a593Smuzhiyun the chip has a very clean way to set the mode, unlike many others. */
set_rx_mode(struct net_device * dev)1507*4882a593Smuzhiyun static void set_rx_mode(struct net_device *dev)
1508*4882a593Smuzhiyun {
1509*4882a593Smuzhiyun int ioaddr = dev->base_addr;
1510*4882a593Smuzhiyun unsigned short new_mode;
1511*4882a593Smuzhiyun
1512*4882a593Smuzhiyun if (dev->flags & IFF_PROMISC) {
1513*4882a593Smuzhiyun if (corkscrew_debug > 3)
1514*4882a593Smuzhiyun pr_debug("%s: Setting promiscuous mode.\n",
1515*4882a593Smuzhiyun dev->name);
1516*4882a593Smuzhiyun new_mode = SetRxFilter | RxStation | RxMulticast | RxBroadcast | RxProm;
1517*4882a593Smuzhiyun } else if (!netdev_mc_empty(dev) || dev->flags & IFF_ALLMULTI) {
1518*4882a593Smuzhiyun new_mode = SetRxFilter | RxStation | RxMulticast | RxBroadcast;
1519*4882a593Smuzhiyun } else
1520*4882a593Smuzhiyun new_mode = SetRxFilter | RxStation | RxBroadcast;
1521*4882a593Smuzhiyun
1522*4882a593Smuzhiyun outw(new_mode, ioaddr + EL3_CMD);
1523*4882a593Smuzhiyun }
1524*4882a593Smuzhiyun
netdev_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)1525*4882a593Smuzhiyun static void netdev_get_drvinfo(struct net_device *dev,
1526*4882a593Smuzhiyun struct ethtool_drvinfo *info)
1527*4882a593Smuzhiyun {
1528*4882a593Smuzhiyun strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1529*4882a593Smuzhiyun snprintf(info->bus_info, sizeof(info->bus_info), "ISA 0x%lx",
1530*4882a593Smuzhiyun dev->base_addr);
1531*4882a593Smuzhiyun }
1532*4882a593Smuzhiyun
netdev_get_msglevel(struct net_device * dev)1533*4882a593Smuzhiyun static u32 netdev_get_msglevel(struct net_device *dev)
1534*4882a593Smuzhiyun {
1535*4882a593Smuzhiyun return corkscrew_debug;
1536*4882a593Smuzhiyun }
1537*4882a593Smuzhiyun
netdev_set_msglevel(struct net_device * dev,u32 level)1538*4882a593Smuzhiyun static void netdev_set_msglevel(struct net_device *dev, u32 level)
1539*4882a593Smuzhiyun {
1540*4882a593Smuzhiyun corkscrew_debug = level;
1541*4882a593Smuzhiyun }
1542*4882a593Smuzhiyun
1543*4882a593Smuzhiyun static const struct ethtool_ops netdev_ethtool_ops = {
1544*4882a593Smuzhiyun .get_drvinfo = netdev_get_drvinfo,
1545*4882a593Smuzhiyun .get_msglevel = netdev_get_msglevel,
1546*4882a593Smuzhiyun .set_msglevel = netdev_set_msglevel,
1547*4882a593Smuzhiyun };
1548*4882a593Smuzhiyun
1549*4882a593Smuzhiyun
1550*4882a593Smuzhiyun #ifdef MODULE
cleanup_module(void)1551*4882a593Smuzhiyun void cleanup_module(void)
1552*4882a593Smuzhiyun {
1553*4882a593Smuzhiyun while (!list_empty(&root_corkscrew_dev)) {
1554*4882a593Smuzhiyun struct net_device *dev;
1555*4882a593Smuzhiyun struct corkscrew_private *vp;
1556*4882a593Smuzhiyun
1557*4882a593Smuzhiyun vp = list_entry(root_corkscrew_dev.next,
1558*4882a593Smuzhiyun struct corkscrew_private, list);
1559*4882a593Smuzhiyun dev = vp->our_dev;
1560*4882a593Smuzhiyun unregister_netdev(dev);
1561*4882a593Smuzhiyun cleanup_card(dev);
1562*4882a593Smuzhiyun free_netdev(dev);
1563*4882a593Smuzhiyun }
1564*4882a593Smuzhiyun }
1565*4882a593Smuzhiyun #endif /* MODULE */
1566