xref: /OK3568_Linux_fs/kernel/drivers/net/dsa/vitesse-vsc73xx-spi.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /* DSA driver for:
3*4882a593Smuzhiyun  * Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
4*4882a593Smuzhiyun  * Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
5*4882a593Smuzhiyun  * Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
6*4882a593Smuzhiyun  * Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * This driver takes control of the switch chip over SPI and
9*4882a593Smuzhiyun  * configures it to route packages around when connected to a CPU port.
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * Copyright (C) 2018 Linus Wallej <linus.walleij@linaro.org>
12*4882a593Smuzhiyun  * Includes portions of code from the firmware uploader by:
13*4882a593Smuzhiyun  * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
14*4882a593Smuzhiyun  */
15*4882a593Smuzhiyun #include <linux/kernel.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/of.h>
18*4882a593Smuzhiyun #include <linux/spi/spi.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #include "vitesse-vsc73xx.h"
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #define VSC73XX_CMD_SPI_MODE_READ		0
23*4882a593Smuzhiyun #define VSC73XX_CMD_SPI_MODE_WRITE		1
24*4882a593Smuzhiyun #define VSC73XX_CMD_SPI_MODE_SHIFT		4
25*4882a593Smuzhiyun #define VSC73XX_CMD_SPI_BLOCK_SHIFT		5
26*4882a593Smuzhiyun #define VSC73XX_CMD_SPI_BLOCK_MASK		0x7
27*4882a593Smuzhiyun #define VSC73XX_CMD_SPI_SUBBLOCK_MASK		0xf
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun /*
30*4882a593Smuzhiyun  * struct vsc73xx_spi - VSC73xx SPI state container
31*4882a593Smuzhiyun  */
32*4882a593Smuzhiyun struct vsc73xx_spi {
33*4882a593Smuzhiyun 	struct spi_device	*spi;
34*4882a593Smuzhiyun 	struct mutex		lock; /* Protects SPI traffic */
35*4882a593Smuzhiyun 	struct vsc73xx		vsc;
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun static const struct vsc73xx_ops vsc73xx_spi_ops;
39*4882a593Smuzhiyun 
vsc73xx_make_addr(u8 mode,u8 block,u8 subblock)40*4882a593Smuzhiyun static u8 vsc73xx_make_addr(u8 mode, u8 block, u8 subblock)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun 	u8 ret;
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun 	ret =
45*4882a593Smuzhiyun 	    (block & VSC73XX_CMD_SPI_BLOCK_MASK) << VSC73XX_CMD_SPI_BLOCK_SHIFT;
46*4882a593Smuzhiyun 	ret |= (mode & 1) << VSC73XX_CMD_SPI_MODE_SHIFT;
47*4882a593Smuzhiyun 	ret |= subblock & VSC73XX_CMD_SPI_SUBBLOCK_MASK;
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 	return ret;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun 
vsc73xx_spi_read(struct vsc73xx * vsc,u8 block,u8 subblock,u8 reg,u32 * val)52*4882a593Smuzhiyun static int vsc73xx_spi_read(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg,
53*4882a593Smuzhiyun 			    u32 *val)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun 	struct vsc73xx_spi *vsc_spi = vsc->priv;
56*4882a593Smuzhiyun 	struct spi_transfer t[2];
57*4882a593Smuzhiyun 	struct spi_message m;
58*4882a593Smuzhiyun 	u8 cmd[4];
59*4882a593Smuzhiyun 	u8 buf[4];
60*4882a593Smuzhiyun 	int ret;
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	if (!vsc73xx_is_addr_valid(block, subblock))
63*4882a593Smuzhiyun 		return -EINVAL;
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 	spi_message_init(&m);
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	memset(&t, 0, sizeof(t));
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	t[0].tx_buf = cmd;
70*4882a593Smuzhiyun 	t[0].len = sizeof(cmd);
71*4882a593Smuzhiyun 	spi_message_add_tail(&t[0], &m);
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	t[1].rx_buf = buf;
74*4882a593Smuzhiyun 	t[1].len = sizeof(buf);
75*4882a593Smuzhiyun 	spi_message_add_tail(&t[1], &m);
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	cmd[0] = vsc73xx_make_addr(VSC73XX_CMD_SPI_MODE_READ, block, subblock);
78*4882a593Smuzhiyun 	cmd[1] = reg;
79*4882a593Smuzhiyun 	cmd[2] = 0;
80*4882a593Smuzhiyun 	cmd[3] = 0;
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 	mutex_lock(&vsc_spi->lock);
83*4882a593Smuzhiyun 	ret = spi_sync(vsc_spi->spi, &m);
84*4882a593Smuzhiyun 	mutex_unlock(&vsc_spi->lock);
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	if (ret)
87*4882a593Smuzhiyun 		return ret;
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	*val = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	return 0;
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun 
vsc73xx_spi_write(struct vsc73xx * vsc,u8 block,u8 subblock,u8 reg,u32 val)94*4882a593Smuzhiyun static int vsc73xx_spi_write(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg,
95*4882a593Smuzhiyun 			     u32 val)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun 	struct vsc73xx_spi *vsc_spi = vsc->priv;
98*4882a593Smuzhiyun 	struct spi_transfer t[2];
99*4882a593Smuzhiyun 	struct spi_message m;
100*4882a593Smuzhiyun 	u8 cmd[2];
101*4882a593Smuzhiyun 	u8 buf[4];
102*4882a593Smuzhiyun 	int ret;
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	if (!vsc73xx_is_addr_valid(block, subblock))
105*4882a593Smuzhiyun 		return -EINVAL;
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	spi_message_init(&m);
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	memset(&t, 0, sizeof(t));
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	t[0].tx_buf = cmd;
112*4882a593Smuzhiyun 	t[0].len = sizeof(cmd);
113*4882a593Smuzhiyun 	spi_message_add_tail(&t[0], &m);
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	t[1].tx_buf = buf;
116*4882a593Smuzhiyun 	t[1].len = sizeof(buf);
117*4882a593Smuzhiyun 	spi_message_add_tail(&t[1], &m);
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	cmd[0] = vsc73xx_make_addr(VSC73XX_CMD_SPI_MODE_WRITE, block, subblock);
120*4882a593Smuzhiyun 	cmd[1] = reg;
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	buf[0] = (val >> 24) & 0xff;
123*4882a593Smuzhiyun 	buf[1] = (val >> 16) & 0xff;
124*4882a593Smuzhiyun 	buf[2] = (val >> 8) & 0xff;
125*4882a593Smuzhiyun 	buf[3] = val & 0xff;
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun 	mutex_lock(&vsc_spi->lock);
128*4882a593Smuzhiyun 	ret = spi_sync(vsc_spi->spi, &m);
129*4882a593Smuzhiyun 	mutex_unlock(&vsc_spi->lock);
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	return ret;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun 
vsc73xx_spi_probe(struct spi_device * spi)134*4882a593Smuzhiyun static int vsc73xx_spi_probe(struct spi_device *spi)
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun 	struct device *dev = &spi->dev;
137*4882a593Smuzhiyun 	struct vsc73xx_spi *vsc_spi;
138*4882a593Smuzhiyun 	int ret;
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	vsc_spi = devm_kzalloc(dev, sizeof(*vsc_spi), GFP_KERNEL);
141*4882a593Smuzhiyun 	if (!vsc_spi)
142*4882a593Smuzhiyun 		return -ENOMEM;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	spi_set_drvdata(spi, vsc_spi);
145*4882a593Smuzhiyun 	vsc_spi->spi = spi_dev_get(spi);
146*4882a593Smuzhiyun 	vsc_spi->vsc.dev = dev;
147*4882a593Smuzhiyun 	vsc_spi->vsc.priv = vsc_spi;
148*4882a593Smuzhiyun 	vsc_spi->vsc.ops = &vsc73xx_spi_ops;
149*4882a593Smuzhiyun 	mutex_init(&vsc_spi->lock);
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	spi->mode = SPI_MODE_0;
152*4882a593Smuzhiyun 	spi->bits_per_word = 8;
153*4882a593Smuzhiyun 	ret = spi_setup(spi);
154*4882a593Smuzhiyun 	if (ret < 0) {
155*4882a593Smuzhiyun 		dev_err(dev, "spi setup failed.\n");
156*4882a593Smuzhiyun 		return ret;
157*4882a593Smuzhiyun 	}
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	return vsc73xx_probe(&vsc_spi->vsc);
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun 
vsc73xx_spi_remove(struct spi_device * spi)162*4882a593Smuzhiyun static int vsc73xx_spi_remove(struct spi_device *spi)
163*4882a593Smuzhiyun {
164*4882a593Smuzhiyun 	struct vsc73xx_spi *vsc_spi = spi_get_drvdata(spi);
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun 	return vsc73xx_remove(&vsc_spi->vsc);
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun static const struct vsc73xx_ops vsc73xx_spi_ops = {
170*4882a593Smuzhiyun 	.read = vsc73xx_spi_read,
171*4882a593Smuzhiyun 	.write = vsc73xx_spi_write,
172*4882a593Smuzhiyun };
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun static const struct of_device_id vsc73xx_of_match[] = {
175*4882a593Smuzhiyun 	{
176*4882a593Smuzhiyun 		.compatible = "vitesse,vsc7385",
177*4882a593Smuzhiyun 	},
178*4882a593Smuzhiyun 	{
179*4882a593Smuzhiyun 		.compatible = "vitesse,vsc7388",
180*4882a593Smuzhiyun 	},
181*4882a593Smuzhiyun 	{
182*4882a593Smuzhiyun 		.compatible = "vitesse,vsc7395",
183*4882a593Smuzhiyun 	},
184*4882a593Smuzhiyun 	{
185*4882a593Smuzhiyun 		.compatible = "vitesse,vsc7398",
186*4882a593Smuzhiyun 	},
187*4882a593Smuzhiyun 	{ },
188*4882a593Smuzhiyun };
189*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, vsc73xx_of_match);
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun static struct spi_driver vsc73xx_spi_driver = {
192*4882a593Smuzhiyun 	.probe = vsc73xx_spi_probe,
193*4882a593Smuzhiyun 	.remove = vsc73xx_spi_remove,
194*4882a593Smuzhiyun 	.driver = {
195*4882a593Smuzhiyun 		.name = "vsc73xx-spi",
196*4882a593Smuzhiyun 		.of_match_table = vsc73xx_of_match,
197*4882a593Smuzhiyun 	},
198*4882a593Smuzhiyun };
199*4882a593Smuzhiyun module_spi_driver(vsc73xx_spi_driver);
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
202*4882a593Smuzhiyun MODULE_DESCRIPTION("Vitesse VSC7385/7388/7395/7398 SPI driver");
203*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
204