xref: /OK3568_Linux_fs/kernel/drivers/net/dsa/vitesse-vsc73xx-platform.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /* DSA driver for:
3*4882a593Smuzhiyun  * Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
4*4882a593Smuzhiyun  * Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
5*4882a593Smuzhiyun  * Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
6*4882a593Smuzhiyun  * Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * This driver takes control of the switch chip connected over CPU-attached
9*4882a593Smuzhiyun  * address bus and configures it to route packages around when connected to
10*4882a593Smuzhiyun  * a CPU port.
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  * Copyright (C) 2019 Pawel Dembicki <paweldembicki@gmail.com>
13*4882a593Smuzhiyun  * Based on vitesse-vsc-spi.c by:
14*4882a593Smuzhiyun  * Copyright (C) 2018 Linus Wallej <linus.walleij@linaro.org>
15*4882a593Smuzhiyun  * Includes portions of code from the firmware uploader by:
16*4882a593Smuzhiyun  * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
17*4882a593Smuzhiyun  */
18*4882a593Smuzhiyun #include <linux/kernel.h>
19*4882a593Smuzhiyun #include <linux/module.h>
20*4882a593Smuzhiyun #include <linux/of.h>
21*4882a593Smuzhiyun #include <linux/platform_device.h>
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #include "vitesse-vsc73xx.h"
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #define VSC73XX_CMD_PLATFORM_BLOCK_SHIFT		14
26*4882a593Smuzhiyun #define VSC73XX_CMD_PLATFORM_BLOCK_MASK			0x7
27*4882a593Smuzhiyun #define VSC73XX_CMD_PLATFORM_SUBBLOCK_SHIFT		10
28*4882a593Smuzhiyun #define VSC73XX_CMD_PLATFORM_SUBBLOCK_MASK		0xf
29*4882a593Smuzhiyun #define VSC73XX_CMD_PLATFORM_REGISTER_SHIFT		2
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun /*
32*4882a593Smuzhiyun  * struct vsc73xx_platform - VSC73xx Platform state container
33*4882a593Smuzhiyun  */
34*4882a593Smuzhiyun struct vsc73xx_platform {
35*4882a593Smuzhiyun 	struct platform_device	*pdev;
36*4882a593Smuzhiyun 	void __iomem		*base_addr;
37*4882a593Smuzhiyun 	struct vsc73xx		vsc;
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun static const struct vsc73xx_ops vsc73xx_platform_ops;
41*4882a593Smuzhiyun 
vsc73xx_make_addr(u8 block,u8 subblock,u8 reg)42*4882a593Smuzhiyun static u32 vsc73xx_make_addr(u8 block, u8 subblock, u8 reg)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun 	u32 ret;
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 	ret = (block & VSC73XX_CMD_PLATFORM_BLOCK_MASK)
47*4882a593Smuzhiyun 	    << VSC73XX_CMD_PLATFORM_BLOCK_SHIFT;
48*4882a593Smuzhiyun 	ret |= (subblock & VSC73XX_CMD_PLATFORM_SUBBLOCK_MASK)
49*4882a593Smuzhiyun 	    << VSC73XX_CMD_PLATFORM_SUBBLOCK_SHIFT;
50*4882a593Smuzhiyun 	ret |= reg << VSC73XX_CMD_PLATFORM_REGISTER_SHIFT;
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	return ret;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun 
vsc73xx_platform_read(struct vsc73xx * vsc,u8 block,u8 subblock,u8 reg,u32 * val)55*4882a593Smuzhiyun static int vsc73xx_platform_read(struct vsc73xx *vsc, u8 block, u8 subblock,
56*4882a593Smuzhiyun 				 u8 reg, u32 *val)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun 	struct vsc73xx_platform *vsc_platform = vsc->priv;
59*4882a593Smuzhiyun 	u32 offset;
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	if (!vsc73xx_is_addr_valid(block, subblock))
62*4882a593Smuzhiyun 		return -EINVAL;
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 	offset = vsc73xx_make_addr(block, subblock, reg);
65*4882a593Smuzhiyun 	/* By default vsc73xx running in big-endian mode.
66*4882a593Smuzhiyun 	 * (See "Register Addressing" section 5.5.3 in the VSC7385 manual.)
67*4882a593Smuzhiyun 	 */
68*4882a593Smuzhiyun 	*val = ioread32be(vsc_platform->base_addr + offset);
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 	return 0;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun 
vsc73xx_platform_write(struct vsc73xx * vsc,u8 block,u8 subblock,u8 reg,u32 val)73*4882a593Smuzhiyun static int vsc73xx_platform_write(struct vsc73xx *vsc, u8 block, u8 subblock,
74*4882a593Smuzhiyun 				  u8 reg, u32 val)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun 	struct vsc73xx_platform *vsc_platform = vsc->priv;
77*4882a593Smuzhiyun 	u32 offset;
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	if (!vsc73xx_is_addr_valid(block, subblock))
80*4882a593Smuzhiyun 		return -EINVAL;
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 	offset = vsc73xx_make_addr(block, subblock, reg);
83*4882a593Smuzhiyun 	iowrite32be(val, vsc_platform->base_addr + offset);
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	return 0;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun 
vsc73xx_platform_probe(struct platform_device * pdev)88*4882a593Smuzhiyun static int vsc73xx_platform_probe(struct platform_device *pdev)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
91*4882a593Smuzhiyun 	struct vsc73xx_platform *vsc_platform;
92*4882a593Smuzhiyun 	int ret;
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	vsc_platform = devm_kzalloc(dev, sizeof(*vsc_platform), GFP_KERNEL);
95*4882a593Smuzhiyun 	if (!vsc_platform)
96*4882a593Smuzhiyun 		return -ENOMEM;
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	platform_set_drvdata(pdev, vsc_platform);
99*4882a593Smuzhiyun 	vsc_platform->pdev = pdev;
100*4882a593Smuzhiyun 	vsc_platform->vsc.dev = dev;
101*4882a593Smuzhiyun 	vsc_platform->vsc.priv = vsc_platform;
102*4882a593Smuzhiyun 	vsc_platform->vsc.ops = &vsc73xx_platform_ops;
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	/* obtain I/O memory space */
105*4882a593Smuzhiyun 	vsc_platform->base_addr = devm_platform_ioremap_resource(pdev, 0);
106*4882a593Smuzhiyun 	if (IS_ERR(vsc_platform->base_addr)) {
107*4882a593Smuzhiyun 		dev_err(&pdev->dev, "cannot request I/O memory space\n");
108*4882a593Smuzhiyun 		ret = -ENXIO;
109*4882a593Smuzhiyun 		return ret;
110*4882a593Smuzhiyun 	}
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	return vsc73xx_probe(&vsc_platform->vsc);
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun 
vsc73xx_platform_remove(struct platform_device * pdev)115*4882a593Smuzhiyun static int vsc73xx_platform_remove(struct platform_device *pdev)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun 	struct vsc73xx_platform *vsc_platform = platform_get_drvdata(pdev);
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	return vsc73xx_remove(&vsc_platform->vsc);
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun static const struct vsc73xx_ops vsc73xx_platform_ops = {
123*4882a593Smuzhiyun 	.read = vsc73xx_platform_read,
124*4882a593Smuzhiyun 	.write = vsc73xx_platform_write,
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun static const struct of_device_id vsc73xx_of_match[] = {
128*4882a593Smuzhiyun 	{
129*4882a593Smuzhiyun 		.compatible = "vitesse,vsc7385",
130*4882a593Smuzhiyun 	},
131*4882a593Smuzhiyun 	{
132*4882a593Smuzhiyun 		.compatible = "vitesse,vsc7388",
133*4882a593Smuzhiyun 	},
134*4882a593Smuzhiyun 	{
135*4882a593Smuzhiyun 		.compatible = "vitesse,vsc7395",
136*4882a593Smuzhiyun 	},
137*4882a593Smuzhiyun 	{
138*4882a593Smuzhiyun 		.compatible = "vitesse,vsc7398",
139*4882a593Smuzhiyun 	},
140*4882a593Smuzhiyun 	{ },
141*4882a593Smuzhiyun };
142*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, vsc73xx_of_match);
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun static struct platform_driver vsc73xx_platform_driver = {
145*4882a593Smuzhiyun 	.probe = vsc73xx_platform_probe,
146*4882a593Smuzhiyun 	.remove = vsc73xx_platform_remove,
147*4882a593Smuzhiyun 	.driver = {
148*4882a593Smuzhiyun 		.name = "vsc73xx-platform",
149*4882a593Smuzhiyun 		.of_match_table = vsc73xx_of_match,
150*4882a593Smuzhiyun 	},
151*4882a593Smuzhiyun };
152*4882a593Smuzhiyun module_platform_driver(vsc73xx_platform_driver);
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun MODULE_AUTHOR("Pawel Dembicki <paweldembicki@gmail.com>");
155*4882a593Smuzhiyun MODULE_DESCRIPTION("Vitesse VSC7385/7388/7395/7398 Platform driver");
156*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
157