1*4882a593Smuzhiyun /* SPDX-License-Identifier: BSD-3-Clause */ 2*4882a593Smuzhiyun /* Copyright 2020, NXP Semiconductors 3*4882a593Smuzhiyun */ 4*4882a593Smuzhiyun #ifndef _SJA1105_SGMII_H 5*4882a593Smuzhiyun #define _SJA1105_SGMII_H 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define SJA1105_SGMII_PORT 4 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* DIGITAL_CONTROL_1 (address 1f8000h) */ 10*4882a593Smuzhiyun #define SJA1105_DC1 0x8000 11*4882a593Smuzhiyun #define SJA1105_DC1_VS_RESET BIT(15) 12*4882a593Smuzhiyun #define SJA1105_DC1_REMOTE_LOOPBACK BIT(14) 13*4882a593Smuzhiyun #define SJA1105_DC1_EN_VSMMD1 BIT(13) 14*4882a593Smuzhiyun #define SJA1105_DC1_POWER_SAVE BIT(11) 15*4882a593Smuzhiyun #define SJA1105_DC1_CLOCK_STOP_EN BIT(10) 16*4882a593Smuzhiyun #define SJA1105_DC1_MAC_AUTO_SW BIT(9) 17*4882a593Smuzhiyun #define SJA1105_DC1_INIT BIT(8) 18*4882a593Smuzhiyun #define SJA1105_DC1_TX_DISABLE BIT(4) 19*4882a593Smuzhiyun #define SJA1105_DC1_AUTONEG_TIMER_OVRR BIT(3) 20*4882a593Smuzhiyun #define SJA1105_DC1_BYP_POWERUP BIT(1) 21*4882a593Smuzhiyun #define SJA1105_DC1_PHY_MODE_CONTROL BIT(0) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* DIGITAL_CONTROL_2 register (address 1f80E1h) */ 24*4882a593Smuzhiyun #define SJA1105_DC2 0x80e1 25*4882a593Smuzhiyun #define SJA1105_DC2_TX_POL_INV_DISABLE BIT(4) 26*4882a593Smuzhiyun #define SJA1105_DC2_RX_POL_INV BIT(0) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* DIGITAL_ERROR_CNT register (address 1f80E2h) */ 29*4882a593Smuzhiyun #define SJA1105_DEC 0x80e2 30*4882a593Smuzhiyun #define SJA1105_DEC_ICG_EC_ENA BIT(4) 31*4882a593Smuzhiyun #define SJA1105_DEC_CLEAR_ON_READ BIT(0) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* AUTONEG_CONTROL register (address 1f8001h) */ 34*4882a593Smuzhiyun #define SJA1105_AC 0x8001 35*4882a593Smuzhiyun #define SJA1105_AC_MII_CONTROL BIT(8) 36*4882a593Smuzhiyun #define SJA1105_AC_SGMII_LINK BIT(4) 37*4882a593Smuzhiyun #define SJA1105_AC_PHY_MODE BIT(3) 38*4882a593Smuzhiyun #define SJA1105_AC_AUTONEG_MODE(x) (((x) << 1) & GENMASK(2, 1)) 39*4882a593Smuzhiyun #define SJA1105_AC_AUTONEG_MODE_SGMII SJA1105_AC_AUTONEG_MODE(2) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* AUTONEG_INTR_STATUS register (address 1f8002h) */ 42*4882a593Smuzhiyun #define SJA1105_AIS 0x8002 43*4882a593Smuzhiyun #define SJA1105_AIS_LINK_STATUS(x) (!!((x) & BIT(4))) 44*4882a593Smuzhiyun #define SJA1105_AIS_SPEED(x) (((x) & GENMASK(3, 2)) >> 2) 45*4882a593Smuzhiyun #define SJA1105_AIS_DUPLEX_MODE(x) (!!((x) & BIT(1))) 46*4882a593Smuzhiyun #define SJA1105_AIS_COMPLETE(x) (!!((x) & BIT(0))) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* DEBUG_CONTROL register (address 1f8005h) */ 49*4882a593Smuzhiyun #define SJA1105_DC 0x8005 50*4882a593Smuzhiyun #define SJA1105_DC_SUPPRESS_LOS BIT(4) 51*4882a593Smuzhiyun #define SJA1105_DC_RESTART_SYNC BIT(0) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #endif 54