1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Marvell 88E6xxx System Management Interface (SMI) support
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2008 Marvell Semiconductor
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (c) 2019 Vivien Didelot <vivien.didelot@gmail.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #ifndef _MV88E6XXX_SMI_H
11*4882a593Smuzhiyun #define _MV88E6XXX_SMI_H
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include "chip.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun /* Offset 0x00: SMI Command Register */
16*4882a593Smuzhiyun #define MV88E6XXX_SMI_CMD 0x00
17*4882a593Smuzhiyun #define MV88E6XXX_SMI_CMD_BUSY 0x8000
18*4882a593Smuzhiyun #define MV88E6XXX_SMI_CMD_MODE_MASK 0x1000
19*4882a593Smuzhiyun #define MV88E6XXX_SMI_CMD_MODE_45 0x0000
20*4882a593Smuzhiyun #define MV88E6XXX_SMI_CMD_MODE_22 0x1000
21*4882a593Smuzhiyun #define MV88E6XXX_SMI_CMD_OP_MASK 0x0c00
22*4882a593Smuzhiyun #define MV88E6XXX_SMI_CMD_OP_22_WRITE 0x0400
23*4882a593Smuzhiyun #define MV88E6XXX_SMI_CMD_OP_22_READ 0x0800
24*4882a593Smuzhiyun #define MV88E6XXX_SMI_CMD_OP_45_WRITE_ADDR 0x0000
25*4882a593Smuzhiyun #define MV88E6XXX_SMI_CMD_OP_45_WRITE_DATA 0x0400
26*4882a593Smuzhiyun #define MV88E6XXX_SMI_CMD_OP_45_READ_DATA 0x0800
27*4882a593Smuzhiyun #define MV88E6XXX_SMI_CMD_OP_45_READ_DATA_INC 0x0c00
28*4882a593Smuzhiyun #define MV88E6XXX_SMI_CMD_DEV_ADDR_MASK 0x003e
29*4882a593Smuzhiyun #define MV88E6XXX_SMI_CMD_REG_ADDR_MASK 0x001f
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* Offset 0x01: SMI Data Register */
32*4882a593Smuzhiyun #define MV88E6XXX_SMI_DATA 0x01
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
35*4882a593Smuzhiyun struct mii_bus *bus, int sw_addr);
36*4882a593Smuzhiyun
mv88e6xxx_smi_read(struct mv88e6xxx_chip * chip,int dev,int reg,u16 * data)37*4882a593Smuzhiyun static inline int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
38*4882a593Smuzhiyun int dev, int reg, u16 *data)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun if (chip->smi_ops && chip->smi_ops->read)
41*4882a593Smuzhiyun return chip->smi_ops->read(chip, dev, reg, data);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun return -EOPNOTSUPP;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
mv88e6xxx_smi_write(struct mv88e6xxx_chip * chip,int dev,int reg,u16 data)46*4882a593Smuzhiyun static inline int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
47*4882a593Smuzhiyun int dev, int reg, u16 data)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun if (chip->smi_ops && chip->smi_ops->write)
50*4882a593Smuzhiyun return chip->smi_ops->write(chip, dev, reg, data);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun return -EOPNOTSUPP;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #endif /* _MV88E6XXX_SMI_H */
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