1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Marvell 88E6xxx Switch Global (1) Registers support 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2008 Marvell Semiconductor 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 8*4882a593Smuzhiyun * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _MV88E6XXX_GLOBAL1_H 12*4882a593Smuzhiyun #define _MV88E6XXX_GLOBAL1_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include "chip.h" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Offset 0x00: Switch Global Status Register */ 17*4882a593Smuzhiyun #define MV88E6XXX_G1_STS 0x00 18*4882a593Smuzhiyun #define MV88E6352_G1_STS_PPU_STATE 0x8000 19*4882a593Smuzhiyun #define MV88E6185_G1_STS_PPU_STATE_MASK 0xc000 20*4882a593Smuzhiyun #define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST 0x0000 21*4882a593Smuzhiyun #define MV88E6185_G1_STS_PPU_STATE_INITIALIZING 0x4000 22*4882a593Smuzhiyun #define MV88E6185_G1_STS_PPU_STATE_DISABLED 0x8000 23*4882a593Smuzhiyun #define MV88E6185_G1_STS_PPU_STATE_POLLING 0xc000 24*4882a593Smuzhiyun #define MV88E6XXX_G1_STS_INIT_READY 0x0800 25*4882a593Smuzhiyun #define MV88E6XXX_G1_STS_IRQ_AVB 8 26*4882a593Smuzhiyun #define MV88E6XXX_G1_STS_IRQ_DEVICE 7 27*4882a593Smuzhiyun #define MV88E6XXX_G1_STS_IRQ_STATS 6 28*4882a593Smuzhiyun #define MV88E6XXX_G1_STS_IRQ_VTU_PROB 5 29*4882a593Smuzhiyun #define MV88E6XXX_G1_STS_IRQ_VTU_DONE 4 30*4882a593Smuzhiyun #define MV88E6XXX_G1_STS_IRQ_ATU_PROB 3 31*4882a593Smuzhiyun #define MV88E6XXX_G1_STS_IRQ_ATU_DONE 2 32*4882a593Smuzhiyun #define MV88E6XXX_G1_STS_IRQ_TCAM_DONE 1 33*4882a593Smuzhiyun #define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE 0 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1 36*4882a593Smuzhiyun * Offset 0x02: Switch MAC Address Register Bytes 2 & 3 37*4882a593Smuzhiyun * Offset 0x03: Switch MAC Address Register Bytes 4 & 5 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun #define MV88E6XXX_G1_MAC_01 0x01 40*4882a593Smuzhiyun #define MV88E6XXX_G1_MAC_23 0x02 41*4882a593Smuzhiyun #define MV88E6XXX_G1_MAC_45 0x03 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* Offset 0x01: ATU FID Register */ 44*4882a593Smuzhiyun #define MV88E6352_G1_ATU_FID 0x01 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* Offset 0x02: VTU FID Register */ 47*4882a593Smuzhiyun #define MV88E6352_G1_VTU_FID 0x02 48*4882a593Smuzhiyun #define MV88E6352_G1_VTU_FID_MASK 0x0fff 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* Offset 0x03: VTU SID Register */ 51*4882a593Smuzhiyun #define MV88E6352_G1_VTU_SID 0x03 52*4882a593Smuzhiyun #define MV88E6352_G1_VTU_SID_MASK 0x3f 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Offset 0x04: Switch Global Control Register */ 55*4882a593Smuzhiyun #define MV88E6XXX_G1_CTL1 0x04 56*4882a593Smuzhiyun #define MV88E6XXX_G1_CTL1_SW_RESET 0x8000 57*4882a593Smuzhiyun #define MV88E6XXX_G1_CTL1_PPU_ENABLE 0x4000 58*4882a593Smuzhiyun #define MV88E6352_G1_CTL1_DISCARD_EXCESS 0x2000 59*4882a593Smuzhiyun #define MV88E6185_G1_CTL1_SCHED_PRIO 0x0800 60*4882a593Smuzhiyun #define MV88E6185_G1_CTL1_MAX_FRAME_1632 0x0400 61*4882a593Smuzhiyun #define MV88E6185_G1_CTL1_RELOAD_EEPROM 0x0200 62*4882a593Smuzhiyun #define MV88E6XXX_G1_CTL1_DEVICE_EN 0x0080 63*4882a593Smuzhiyun #define MV88E6XXX_G1_CTL1_STATS_DONE_EN 0x0040 64*4882a593Smuzhiyun #define MV88E6XXX_G1_CTL1_VTU_PROBLEM_EN 0x0020 65*4882a593Smuzhiyun #define MV88E6XXX_G1_CTL1_VTU_DONE_EN 0x0010 66*4882a593Smuzhiyun #define MV88E6XXX_G1_CTL1_ATU_PROBLEM_EN 0x0008 67*4882a593Smuzhiyun #define MV88E6XXX_G1_CTL1_ATU_DONE_EN 0x0004 68*4882a593Smuzhiyun #define MV88E6XXX_G1_CTL1_TCAM_EN 0x0002 69*4882a593Smuzhiyun #define MV88E6XXX_G1_CTL1_EEPROM_DONE_EN 0x0001 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* Offset 0x05: VTU Operation Register */ 72*4882a593Smuzhiyun #define MV88E6XXX_G1_VTU_OP 0x05 73*4882a593Smuzhiyun #define MV88E6XXX_G1_VTU_OP_BUSY 0x8000 74*4882a593Smuzhiyun #define MV88E6XXX_G1_VTU_OP_MASK 0x7000 75*4882a593Smuzhiyun #define MV88E6XXX_G1_VTU_OP_FLUSH_ALL 0x1000 76*4882a593Smuzhiyun #define MV88E6XXX_G1_VTU_OP_NOOP 0x2000 77*4882a593Smuzhiyun #define MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE 0x3000 78*4882a593Smuzhiyun #define MV88E6XXX_G1_VTU_OP_VTU_GET_NEXT 0x4000 79*4882a593Smuzhiyun #define MV88E6XXX_G1_VTU_OP_STU_LOAD_PURGE 0x5000 80*4882a593Smuzhiyun #define MV88E6XXX_G1_VTU_OP_STU_GET_NEXT 0x6000 81*4882a593Smuzhiyun #define MV88E6XXX_G1_VTU_OP_GET_CLR_VIOLATION 0x7000 82*4882a593Smuzhiyun #define MV88E6XXX_G1_VTU_OP_MEMBER_VIOLATION BIT(6) 83*4882a593Smuzhiyun #define MV88E6XXX_G1_VTU_OP_MISS_VIOLATION BIT(5) 84*4882a593Smuzhiyun #define MV88E6XXX_G1_VTU_OP_SPID_MASK 0xf 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* Offset 0x06: VTU VID Register */ 87*4882a593Smuzhiyun #define MV88E6XXX_G1_VTU_VID 0x06 88*4882a593Smuzhiyun #define MV88E6XXX_G1_VTU_VID_MASK 0x0fff 89*4882a593Smuzhiyun #define MV88E6390_G1_VTU_VID_PAGE 0x2000 90*4882a593Smuzhiyun #define MV88E6XXX_G1_VTU_VID_VALID 0x1000 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* Offset 0x07: VTU/STU Data Register 1 93*4882a593Smuzhiyun * Offset 0x08: VTU/STU Data Register 2 94*4882a593Smuzhiyun * Offset 0x09: VTU/STU Data Register 3 95*4882a593Smuzhiyun */ 96*4882a593Smuzhiyun #define MV88E6XXX_G1_VTU_DATA1 0x07 97*4882a593Smuzhiyun #define MV88E6XXX_G1_VTU_DATA2 0x08 98*4882a593Smuzhiyun #define MV88E6XXX_G1_VTU_DATA3 0x09 99*4882a593Smuzhiyun #define MV88E6XXX_G1_VTU_STU_DATA_MASK 0x0003 100*4882a593Smuzhiyun #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x0000 101*4882a593Smuzhiyun #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED 0x0001 102*4882a593Smuzhiyun #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED 0x0002 103*4882a593Smuzhiyun #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER 0x0003 104*4882a593Smuzhiyun #define MV88E6XXX_G1_STU_DATA_PORT_STATE_DISABLED 0x0000 105*4882a593Smuzhiyun #define MV88E6XXX_G1_STU_DATA_PORT_STATE_BLOCKING 0x0001 106*4882a593Smuzhiyun #define MV88E6XXX_G1_STU_DATA_PORT_STATE_LEARNING 0x0002 107*4882a593Smuzhiyun #define MV88E6XXX_G1_STU_DATA_PORT_STATE_FORWARDING 0x0003 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* Offset 0x0A: ATU Control Register */ 110*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_CTL 0x0a 111*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_CTL_LEARN2ALL 0x0008 112*4882a593Smuzhiyun #define MV88E6161_G1_ATU_CTL_HASH_MASK 0x0003 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* Offset 0x0B: ATU Operation Register */ 115*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_OP 0x0b 116*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_OP_BUSY 0x8000 117*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_OP_MASK 0x7000 118*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_OP_NOOP 0x0000 119*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL 0x1000 120*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC 0x2000 121*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_OP_LOAD_DB 0x3000 122*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_OP_GET_NEXT_DB 0x4000 123*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB 0x5000 124*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB 0x6000 125*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION 0x7000 126*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_OP_AGE_OUT_VIOLATION BIT(7) 127*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION BIT(6) 128*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_OP_MISS_VIOLATION BIT(5) 129*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_OP_FULL_VIOLATION BIT(4) 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* Offset 0x0C: ATU Data Register */ 132*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA 0x0c 133*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_TRUNK 0x8000 134*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_TRUNK_ID_MASK 0x00f0 135*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_PORT_VECTOR_MASK 0x3ff0 136*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_STATE_MASK 0x000f 137*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_STATE_UC_UNUSED 0x0000 138*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_1_OLDEST 0x0001 139*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_2 0x0002 140*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_3 0x0003 141*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_4 0x0004 142*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_5 0x0005 143*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_6 0x0006 144*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_7_NEWEST 0x0007 145*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY 0x0008 146*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY_PO 0x0009 147*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL 0x000a 148*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL_PO 0x000b 149*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT 0x000c 150*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT_PO 0x000d 151*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC 0x000e 152*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_PO 0x000f 153*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED 0x0000 154*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY 0x0004 155*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL 0x0005 156*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT 0x0006 157*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC 0x0007 158*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY_PO 0x000c 159*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL_PO 0x000d 160*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT_PO 0x000e 161*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_PO 0x000f 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1 164*4882a593Smuzhiyun * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3 165*4882a593Smuzhiyun * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5 166*4882a593Smuzhiyun */ 167*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_MAC01 0x0d 168*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_MAC23 0x0e 169*4882a593Smuzhiyun #define MV88E6XXX_G1_ATU_MAC45 0x0f 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun /* Offset 0x10: IP-PRI Mapping Register 0 172*4882a593Smuzhiyun * Offset 0x11: IP-PRI Mapping Register 1 173*4882a593Smuzhiyun * Offset 0x12: IP-PRI Mapping Register 2 174*4882a593Smuzhiyun * Offset 0x13: IP-PRI Mapping Register 3 175*4882a593Smuzhiyun * Offset 0x14: IP-PRI Mapping Register 4 176*4882a593Smuzhiyun * Offset 0x15: IP-PRI Mapping Register 5 177*4882a593Smuzhiyun * Offset 0x16: IP-PRI Mapping Register 6 178*4882a593Smuzhiyun * Offset 0x17: IP-PRI Mapping Register 7 179*4882a593Smuzhiyun */ 180*4882a593Smuzhiyun #define MV88E6XXX_G1_IP_PRI_0 0x10 181*4882a593Smuzhiyun #define MV88E6XXX_G1_IP_PRI_1 0x11 182*4882a593Smuzhiyun #define MV88E6XXX_G1_IP_PRI_2 0x12 183*4882a593Smuzhiyun #define MV88E6XXX_G1_IP_PRI_3 0x13 184*4882a593Smuzhiyun #define MV88E6XXX_G1_IP_PRI_4 0x14 185*4882a593Smuzhiyun #define MV88E6XXX_G1_IP_PRI_5 0x15 186*4882a593Smuzhiyun #define MV88E6XXX_G1_IP_PRI_6 0x16 187*4882a593Smuzhiyun #define MV88E6XXX_G1_IP_PRI_7 0x17 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun /* Offset 0x18: IEEE-PRI Register */ 190*4882a593Smuzhiyun #define MV88E6XXX_G1_IEEE_PRI 0x18 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun /* Offset 0x19: Core Tag Type */ 193*4882a593Smuzhiyun #define MV88E6185_G1_CORE_TAG_TYPE 0x19 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun /* Offset 0x1A: Monitor Control */ 196*4882a593Smuzhiyun #define MV88E6185_G1_MONITOR_CTL 0x1a 197*4882a593Smuzhiyun #define MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK 0xf000 198*4882a593Smuzhiyun #define MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK 0x0f00 199*4882a593Smuzhiyun #define MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK 0x00f0 200*4882a593Smuzhiyun #define MV88E6352_G1_MONITOR_CTL_CPU_DEST_MASK 0x00f0 201*4882a593Smuzhiyun #define MV88E6352_G1_MONITOR_CTL_MIRROR_DEST_MASK 0x000f 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun /* Offset 0x1A: Monitor & MGMT Control Register */ 204*4882a593Smuzhiyun #define MV88E6390_G1_MONITOR_MGMT_CTL 0x1a 205*4882a593Smuzhiyun #define MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE 0x8000 206*4882a593Smuzhiyun #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_MASK 0x3f00 207*4882a593Smuzhiyun #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO 0x0000 208*4882a593Smuzhiyun #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI 0x0100 209*4882a593Smuzhiyun #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO 0x0200 210*4882a593Smuzhiyun #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI 0x0300 211*4882a593Smuzhiyun #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST 0x2000 212*4882a593Smuzhiyun #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST 0x2100 213*4882a593Smuzhiyun #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST 0x3000 214*4882a593Smuzhiyun #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI 0x00e0 215*4882a593Smuzhiyun #define MV88E6390_G1_MONITOR_MGMT_CTL_DATA_MASK 0x00ff 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun /* Offset 0x1C: Global Control 2 */ 218*4882a593Smuzhiyun #define MV88E6XXX_G1_CTL2 0x1c 219*4882a593Smuzhiyun #define MV88E6185_G1_CTL2_CASCADE_PORT_MASK 0xf000 220*4882a593Smuzhiyun #define MV88E6185_G1_CTL2_CASCADE_PORT_NONE 0xe000 221*4882a593Smuzhiyun #define MV88E6185_G1_CTL2_CASCADE_PORT_MULTI 0xf000 222*4882a593Smuzhiyun #define MV88E6352_G1_CTL2_HEADER_TYPE_MASK 0xc000 223*4882a593Smuzhiyun #define MV88E6352_G1_CTL2_HEADER_TYPE_ORIG 0x0000 224*4882a593Smuzhiyun #define MV88E6352_G1_CTL2_HEADER_TYPE_MGMT 0x4000 225*4882a593Smuzhiyun #define MV88E6390_G1_CTL2_HEADER_TYPE_LAG 0x8000 226*4882a593Smuzhiyun #define MV88E6352_G1_CTL2_RMU_MODE_MASK 0x3000 227*4882a593Smuzhiyun #define MV88E6352_G1_CTL2_RMU_MODE_DISABLED 0x0000 228*4882a593Smuzhiyun #define MV88E6352_G1_CTL2_RMU_MODE_PORT_4 0x1000 229*4882a593Smuzhiyun #define MV88E6352_G1_CTL2_RMU_MODE_PORT_5 0x2000 230*4882a593Smuzhiyun #define MV88E6352_G1_CTL2_RMU_MODE_PORT_6 0x3000 231*4882a593Smuzhiyun #define MV88E6085_G1_CTL2_DA_CHECK 0x4000 232*4882a593Smuzhiyun #define MV88E6085_G1_CTL2_P10RM 0x2000 233*4882a593Smuzhiyun #define MV88E6085_G1_CTL2_RM_ENABLE 0x1000 234*4882a593Smuzhiyun #define MV88E6352_G1_CTL2_DA_CHECK 0x0800 235*4882a593Smuzhiyun #define MV88E6390_G1_CTL2_RMU_MODE_MASK 0x0700 236*4882a593Smuzhiyun #define MV88E6390_G1_CTL2_RMU_MODE_PORT_0 0x0000 237*4882a593Smuzhiyun #define MV88E6390_G1_CTL2_RMU_MODE_PORT_1 0x0100 238*4882a593Smuzhiyun #define MV88E6390_G1_CTL2_RMU_MODE_PORT_9 0x0200 239*4882a593Smuzhiyun #define MV88E6390_G1_CTL2_RMU_MODE_PORT_10 0x0300 240*4882a593Smuzhiyun #define MV88E6390_G1_CTL2_RMU_MODE_ALL_DSA 0x0600 241*4882a593Smuzhiyun #define MV88E6390_G1_CTL2_RMU_MODE_DISABLED 0x0700 242*4882a593Smuzhiyun #define MV88E6390_G1_CTL2_HIST_MODE_MASK 0x00c0 243*4882a593Smuzhiyun #define MV88E6390_G1_CTL2_HIST_MODE_RX 0x0040 244*4882a593Smuzhiyun #define MV88E6390_G1_CTL2_HIST_MODE_TX 0x0080 245*4882a593Smuzhiyun #define MV88E6352_G1_CTL2_CTR_MODE_MASK 0x0060 246*4882a593Smuzhiyun #define MV88E6390_G1_CTL2_CTR_MODE 0x0020 247*4882a593Smuzhiyun #define MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK 0x001f 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun /* Offset 0x1D: Stats Operation Register */ 250*4882a593Smuzhiyun #define MV88E6XXX_G1_STATS_OP 0x1d 251*4882a593Smuzhiyun #define MV88E6XXX_G1_STATS_OP_BUSY 0x8000 252*4882a593Smuzhiyun #define MV88E6XXX_G1_STATS_OP_NOP 0x0000 253*4882a593Smuzhiyun #define MV88E6XXX_G1_STATS_OP_FLUSH_ALL 0x1000 254*4882a593Smuzhiyun #define MV88E6XXX_G1_STATS_OP_FLUSH_PORT 0x2000 255*4882a593Smuzhiyun #define MV88E6XXX_G1_STATS_OP_READ_CAPTURED 0x4000 256*4882a593Smuzhiyun #define MV88E6XXX_G1_STATS_OP_CAPTURE_PORT 0x5000 257*4882a593Smuzhiyun #define MV88E6XXX_G1_STATS_OP_HIST_RX 0x0400 258*4882a593Smuzhiyun #define MV88E6XXX_G1_STATS_OP_HIST_TX 0x0800 259*4882a593Smuzhiyun #define MV88E6XXX_G1_STATS_OP_HIST_RX_TX 0x0c00 260*4882a593Smuzhiyun #define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9 0x0200 261*4882a593Smuzhiyun #define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10 0x0400 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun /* Offset 0x1E: Stats Counter Register Bytes 3 & 2 264*4882a593Smuzhiyun * Offset 0x1F: Stats Counter Register Bytes 1 & 0 265*4882a593Smuzhiyun */ 266*4882a593Smuzhiyun #define MV88E6XXX_G1_STATS_COUNTER_32 0x1e 267*4882a593Smuzhiyun #define MV88E6XXX_G1_STATS_COUNTER_01 0x1f 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val); 270*4882a593Smuzhiyun int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val); 271*4882a593Smuzhiyun int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int 272*4882a593Smuzhiyun bit, int val); 273*4882a593Smuzhiyun int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg, 274*4882a593Smuzhiyun u16 mask, u16 val); 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr); 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip); 279*4882a593Smuzhiyun int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip); 280*4882a593Smuzhiyun int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip); 281*4882a593Smuzhiyun void mv88e6xxx_g1_wait_eeprom_done(struct mv88e6xxx_chip *chip); 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip); 284*4882a593Smuzhiyun int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip); 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu); 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port); 289*4882a593Smuzhiyun int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port); 290*4882a593Smuzhiyun int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port); 291*4882a593Smuzhiyun int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip); 292*4882a593Smuzhiyun int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip); 293*4882a593Smuzhiyun void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val); 294*4882a593Smuzhiyun int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip); 295*4882a593Smuzhiyun int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, 296*4882a593Smuzhiyun enum mv88e6xxx_egress_direction direction, 297*4882a593Smuzhiyun int port); 298*4882a593Smuzhiyun int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, 299*4882a593Smuzhiyun enum mv88e6xxx_egress_direction direction, 300*4882a593Smuzhiyun int port); 301*4882a593Smuzhiyun int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port); 302*4882a593Smuzhiyun int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port); 303*4882a593Smuzhiyun int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip); 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip); 308*4882a593Smuzhiyun int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip); 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port); 311*4882a593Smuzhiyun 312*4882a593Smuzhiyun int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip); 313*4882a593Smuzhiyun int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip); 314*4882a593Smuzhiyun int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip); 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index); 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all); 319*4882a593Smuzhiyun int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip, 320*4882a593Smuzhiyun unsigned int msecs); 321*4882a593Smuzhiyun int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, 322*4882a593Smuzhiyun struct mv88e6xxx_atu_entry *entry); 323*4882a593Smuzhiyun int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid, 324*4882a593Smuzhiyun struct mv88e6xxx_atu_entry *entry); 325*4882a593Smuzhiyun int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all); 326*4882a593Smuzhiyun int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port, 327*4882a593Smuzhiyun bool all); 328*4882a593Smuzhiyun int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip *chip); 329*4882a593Smuzhiyun void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip *chip); 330*4882a593Smuzhiyun int mv88e6165_g1_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash); 331*4882a593Smuzhiyun int mv88e6165_g1_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash); 332*4882a593Smuzhiyun 333*4882a593Smuzhiyun int mv88e6185_g1_vtu_getnext(struct mv88e6xxx_chip *chip, 334*4882a593Smuzhiyun struct mv88e6xxx_vtu_entry *entry); 335*4882a593Smuzhiyun int mv88e6185_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip, 336*4882a593Smuzhiyun struct mv88e6xxx_vtu_entry *entry); 337*4882a593Smuzhiyun int mv88e6250_g1_vtu_getnext(struct mv88e6xxx_chip *chip, 338*4882a593Smuzhiyun struct mv88e6xxx_vtu_entry *entry); 339*4882a593Smuzhiyun int mv88e6250_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip, 340*4882a593Smuzhiyun struct mv88e6xxx_vtu_entry *entry); 341*4882a593Smuzhiyun int mv88e6352_g1_vtu_getnext(struct mv88e6xxx_chip *chip, 342*4882a593Smuzhiyun struct mv88e6xxx_vtu_entry *entry); 343*4882a593Smuzhiyun int mv88e6352_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip, 344*4882a593Smuzhiyun struct mv88e6xxx_vtu_entry *entry); 345*4882a593Smuzhiyun int mv88e6390_g1_vtu_getnext(struct mv88e6xxx_chip *chip, 346*4882a593Smuzhiyun struct mv88e6xxx_vtu_entry *entry); 347*4882a593Smuzhiyun int mv88e6390_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip, 348*4882a593Smuzhiyun struct mv88e6xxx_vtu_entry *entry); 349*4882a593Smuzhiyun int mv88e6xxx_g1_vtu_flush(struct mv88e6xxx_chip *chip); 350*4882a593Smuzhiyun int mv88e6xxx_g1_vtu_prob_irq_setup(struct mv88e6xxx_chip *chip); 351*4882a593Smuzhiyun void mv88e6xxx_g1_vtu_prob_irq_free(struct mv88e6xxx_chip *chip); 352*4882a593Smuzhiyun int mv88e6xxx_g1_atu_get_next(struct mv88e6xxx_chip *chip, u16 fid); 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun #endif /* _MV88E6XXX_GLOBAL1_H */ 355