xref: /OK3568_Linux_fs/kernel/drivers/net/dsa/microchip/ksz8795.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Microchip KSZ8795 switch driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2017 Microchip Technology Inc.
6*4882a593Smuzhiyun  *	Tristram Ha <Tristram.Ha@microchip.com>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/delay.h>
10*4882a593Smuzhiyun #include <linux/export.h>
11*4882a593Smuzhiyun #include <linux/gpio.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/platform_data/microchip-ksz.h>
15*4882a593Smuzhiyun #include <linux/phy.h>
16*4882a593Smuzhiyun #include <linux/etherdevice.h>
17*4882a593Smuzhiyun #include <linux/if_bridge.h>
18*4882a593Smuzhiyun #include <net/dsa.h>
19*4882a593Smuzhiyun #include <net/switchdev.h>
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #include "ksz_common.h"
22*4882a593Smuzhiyun #include "ksz8795_reg.h"
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun static const struct {
25*4882a593Smuzhiyun 	char string[ETH_GSTRING_LEN];
26*4882a593Smuzhiyun } mib_names[TOTAL_SWITCH_COUNTER_NUM] = {
27*4882a593Smuzhiyun 	{ "rx_hi" },
28*4882a593Smuzhiyun 	{ "rx_undersize" },
29*4882a593Smuzhiyun 	{ "rx_fragments" },
30*4882a593Smuzhiyun 	{ "rx_oversize" },
31*4882a593Smuzhiyun 	{ "rx_jabbers" },
32*4882a593Smuzhiyun 	{ "rx_symbol_err" },
33*4882a593Smuzhiyun 	{ "rx_crc_err" },
34*4882a593Smuzhiyun 	{ "rx_align_err" },
35*4882a593Smuzhiyun 	{ "rx_mac_ctrl" },
36*4882a593Smuzhiyun 	{ "rx_pause" },
37*4882a593Smuzhiyun 	{ "rx_bcast" },
38*4882a593Smuzhiyun 	{ "rx_mcast" },
39*4882a593Smuzhiyun 	{ "rx_ucast" },
40*4882a593Smuzhiyun 	{ "rx_64_or_less" },
41*4882a593Smuzhiyun 	{ "rx_65_127" },
42*4882a593Smuzhiyun 	{ "rx_128_255" },
43*4882a593Smuzhiyun 	{ "rx_256_511" },
44*4882a593Smuzhiyun 	{ "rx_512_1023" },
45*4882a593Smuzhiyun 	{ "rx_1024_1522" },
46*4882a593Smuzhiyun 	{ "rx_1523_2000" },
47*4882a593Smuzhiyun 	{ "rx_2001" },
48*4882a593Smuzhiyun 	{ "tx_hi" },
49*4882a593Smuzhiyun 	{ "tx_late_col" },
50*4882a593Smuzhiyun 	{ "tx_pause" },
51*4882a593Smuzhiyun 	{ "tx_bcast" },
52*4882a593Smuzhiyun 	{ "tx_mcast" },
53*4882a593Smuzhiyun 	{ "tx_ucast" },
54*4882a593Smuzhiyun 	{ "tx_deferred" },
55*4882a593Smuzhiyun 	{ "tx_total_col" },
56*4882a593Smuzhiyun 	{ "tx_exc_col" },
57*4882a593Smuzhiyun 	{ "tx_single_col" },
58*4882a593Smuzhiyun 	{ "tx_mult_col" },
59*4882a593Smuzhiyun 	{ "rx_total" },
60*4882a593Smuzhiyun 	{ "tx_total" },
61*4882a593Smuzhiyun 	{ "rx_discards" },
62*4882a593Smuzhiyun 	{ "tx_discards" },
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun 
ksz_cfg(struct ksz_device * dev,u32 addr,u8 bits,bool set)65*4882a593Smuzhiyun static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun 	regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun 
ksz_port_cfg(struct ksz_device * dev,int port,int offset,u8 bits,bool set)70*4882a593Smuzhiyun static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits,
71*4882a593Smuzhiyun 			 bool set)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun 	regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset),
74*4882a593Smuzhiyun 			   bits, set ? bits : 0);
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun 
ksz8795_reset_switch(struct ksz_device * dev)77*4882a593Smuzhiyun static int ksz8795_reset_switch(struct ksz_device *dev)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun 	/* reset switch */
80*4882a593Smuzhiyun 	ksz_write8(dev, REG_POWER_MANAGEMENT_1,
81*4882a593Smuzhiyun 		   SW_SOFTWARE_POWER_DOWN << SW_POWER_MANAGEMENT_MODE_S);
82*4882a593Smuzhiyun 	ksz_write8(dev, REG_POWER_MANAGEMENT_1, 0);
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun 	return 0;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun 
ksz8795_set_prio_queue(struct ksz_device * dev,int port,int queue)87*4882a593Smuzhiyun static void ksz8795_set_prio_queue(struct ksz_device *dev, int port, int queue)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun 	u8 hi, lo;
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	/* Number of queues can only be 1, 2, or 4. */
92*4882a593Smuzhiyun 	switch (queue) {
93*4882a593Smuzhiyun 	case 4:
94*4882a593Smuzhiyun 	case 3:
95*4882a593Smuzhiyun 		queue = PORT_QUEUE_SPLIT_4;
96*4882a593Smuzhiyun 		break;
97*4882a593Smuzhiyun 	case 2:
98*4882a593Smuzhiyun 		queue = PORT_QUEUE_SPLIT_2;
99*4882a593Smuzhiyun 		break;
100*4882a593Smuzhiyun 	default:
101*4882a593Smuzhiyun 		queue = PORT_QUEUE_SPLIT_1;
102*4882a593Smuzhiyun 	}
103*4882a593Smuzhiyun 	ksz_pread8(dev, port, REG_PORT_CTRL_0, &lo);
104*4882a593Smuzhiyun 	ksz_pread8(dev, port, P_DROP_TAG_CTRL, &hi);
105*4882a593Smuzhiyun 	lo &= ~PORT_QUEUE_SPLIT_L;
106*4882a593Smuzhiyun 	if (queue & PORT_QUEUE_SPLIT_2)
107*4882a593Smuzhiyun 		lo |= PORT_QUEUE_SPLIT_L;
108*4882a593Smuzhiyun 	hi &= ~PORT_QUEUE_SPLIT_H;
109*4882a593Smuzhiyun 	if (queue & PORT_QUEUE_SPLIT_4)
110*4882a593Smuzhiyun 		hi |= PORT_QUEUE_SPLIT_H;
111*4882a593Smuzhiyun 	ksz_pwrite8(dev, port, REG_PORT_CTRL_0, lo);
112*4882a593Smuzhiyun 	ksz_pwrite8(dev, port, P_DROP_TAG_CTRL, hi);
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	/* Default is port based for egress rate limit. */
115*4882a593Smuzhiyun 	if (queue != PORT_QUEUE_SPLIT_1)
116*4882a593Smuzhiyun 		ksz_cfg(dev, REG_SW_CTRL_19, SW_OUT_RATE_LIMIT_QUEUE_BASED,
117*4882a593Smuzhiyun 			true);
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun 
ksz8795_r_mib_cnt(struct ksz_device * dev,int port,u16 addr,u64 * cnt)120*4882a593Smuzhiyun static void ksz8795_r_mib_cnt(struct ksz_device *dev, int port, u16 addr,
121*4882a593Smuzhiyun 			      u64 *cnt)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun 	u16 ctrl_addr;
124*4882a593Smuzhiyun 	u32 data;
125*4882a593Smuzhiyun 	u8 check;
126*4882a593Smuzhiyun 	int loop;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	ctrl_addr = addr + SWITCH_COUNTER_NUM * port;
129*4882a593Smuzhiyun 	ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	mutex_lock(&dev->alu_mutex);
132*4882a593Smuzhiyun 	ksz_write16(dev, REG_IND_CTRL_0, ctrl_addr);
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	/* It is almost guaranteed to always read the valid bit because of
135*4882a593Smuzhiyun 	 * slow SPI speed.
136*4882a593Smuzhiyun 	 */
137*4882a593Smuzhiyun 	for (loop = 2; loop > 0; loop--) {
138*4882a593Smuzhiyun 		ksz_read8(dev, REG_IND_MIB_CHECK, &check);
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 		if (check & MIB_COUNTER_VALID) {
141*4882a593Smuzhiyun 			ksz_read32(dev, REG_IND_DATA_LO, &data);
142*4882a593Smuzhiyun 			if (check & MIB_COUNTER_OVERFLOW)
143*4882a593Smuzhiyun 				*cnt += MIB_COUNTER_VALUE + 1;
144*4882a593Smuzhiyun 			*cnt += data & MIB_COUNTER_VALUE;
145*4882a593Smuzhiyun 			break;
146*4882a593Smuzhiyun 		}
147*4882a593Smuzhiyun 	}
148*4882a593Smuzhiyun 	mutex_unlock(&dev->alu_mutex);
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun 
ksz8795_r_mib_pkt(struct ksz_device * dev,int port,u16 addr,u64 * dropped,u64 * cnt)151*4882a593Smuzhiyun static void ksz8795_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
152*4882a593Smuzhiyun 			      u64 *dropped, u64 *cnt)
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun 	u16 ctrl_addr;
155*4882a593Smuzhiyun 	u32 data;
156*4882a593Smuzhiyun 	u8 check;
157*4882a593Smuzhiyun 	int loop;
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	addr -= SWITCH_COUNTER_NUM;
160*4882a593Smuzhiyun 	ctrl_addr = (KS_MIB_TOTAL_RX_1 - KS_MIB_TOTAL_RX_0) * port;
161*4882a593Smuzhiyun 	ctrl_addr += addr + KS_MIB_TOTAL_RX_0;
162*4882a593Smuzhiyun 	ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	mutex_lock(&dev->alu_mutex);
165*4882a593Smuzhiyun 	ksz_write16(dev, REG_IND_CTRL_0, ctrl_addr);
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	/* It is almost guaranteed to always read the valid bit because of
168*4882a593Smuzhiyun 	 * slow SPI speed.
169*4882a593Smuzhiyun 	 */
170*4882a593Smuzhiyun 	for (loop = 2; loop > 0; loop--) {
171*4882a593Smuzhiyun 		ksz_read8(dev, REG_IND_MIB_CHECK, &check);
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 		if (check & MIB_COUNTER_VALID) {
174*4882a593Smuzhiyun 			ksz_read32(dev, REG_IND_DATA_LO, &data);
175*4882a593Smuzhiyun 			if (addr < 2) {
176*4882a593Smuzhiyun 				u64 total;
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 				total = check & MIB_TOTAL_BYTES_H;
179*4882a593Smuzhiyun 				total <<= 32;
180*4882a593Smuzhiyun 				*cnt += total;
181*4882a593Smuzhiyun 				*cnt += data;
182*4882a593Smuzhiyun 				if (check & MIB_COUNTER_OVERFLOW) {
183*4882a593Smuzhiyun 					total = MIB_TOTAL_BYTES_H + 1;
184*4882a593Smuzhiyun 					total <<= 32;
185*4882a593Smuzhiyun 					*cnt += total;
186*4882a593Smuzhiyun 				}
187*4882a593Smuzhiyun 			} else {
188*4882a593Smuzhiyun 				if (check & MIB_COUNTER_OVERFLOW)
189*4882a593Smuzhiyun 					*cnt += MIB_PACKET_DROPPED + 1;
190*4882a593Smuzhiyun 				*cnt += data & MIB_PACKET_DROPPED;
191*4882a593Smuzhiyun 			}
192*4882a593Smuzhiyun 			break;
193*4882a593Smuzhiyun 		}
194*4882a593Smuzhiyun 	}
195*4882a593Smuzhiyun 	mutex_unlock(&dev->alu_mutex);
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun 
ksz8795_freeze_mib(struct ksz_device * dev,int port,bool freeze)198*4882a593Smuzhiyun static void ksz8795_freeze_mib(struct ksz_device *dev, int port, bool freeze)
199*4882a593Smuzhiyun {
200*4882a593Smuzhiyun 	/* enable the port for flush/freeze function */
201*4882a593Smuzhiyun 	if (freeze)
202*4882a593Smuzhiyun 		ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
203*4882a593Smuzhiyun 	ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FREEZE, freeze);
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 	/* disable the port after freeze is done */
206*4882a593Smuzhiyun 	if (!freeze)
207*4882a593Smuzhiyun 		ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun 
ksz8795_port_init_cnt(struct ksz_device * dev,int port)210*4882a593Smuzhiyun static void ksz8795_port_init_cnt(struct ksz_device *dev, int port)
211*4882a593Smuzhiyun {
212*4882a593Smuzhiyun 	struct ksz_port_mib *mib = &dev->ports[port].mib;
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	/* flush all enabled port MIB counters */
215*4882a593Smuzhiyun 	ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
216*4882a593Smuzhiyun 	ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FLUSH, true);
217*4882a593Smuzhiyun 	ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 	mib->cnt_ptr = 0;
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 	/* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
222*4882a593Smuzhiyun 	while (mib->cnt_ptr < dev->reg_mib_cnt) {
223*4882a593Smuzhiyun 		dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
224*4882a593Smuzhiyun 					&mib->counters[mib->cnt_ptr]);
225*4882a593Smuzhiyun 		++mib->cnt_ptr;
226*4882a593Smuzhiyun 	}
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 	/* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
229*4882a593Smuzhiyun 	while (mib->cnt_ptr < dev->mib_cnt) {
230*4882a593Smuzhiyun 		dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
231*4882a593Smuzhiyun 					NULL, &mib->counters[mib->cnt_ptr]);
232*4882a593Smuzhiyun 		++mib->cnt_ptr;
233*4882a593Smuzhiyun 	}
234*4882a593Smuzhiyun 	mib->cnt_ptr = 0;
235*4882a593Smuzhiyun 	memset(mib->counters, 0, dev->mib_cnt * sizeof(u64));
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun 
ksz8795_r_table(struct ksz_device * dev,int table,u16 addr,u64 * data)238*4882a593Smuzhiyun static void ksz8795_r_table(struct ksz_device *dev, int table, u16 addr,
239*4882a593Smuzhiyun 			    u64 *data)
240*4882a593Smuzhiyun {
241*4882a593Smuzhiyun 	u16 ctrl_addr;
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr;
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	mutex_lock(&dev->alu_mutex);
246*4882a593Smuzhiyun 	ksz_write16(dev, REG_IND_CTRL_0, ctrl_addr);
247*4882a593Smuzhiyun 	ksz_read64(dev, REG_IND_DATA_HI, data);
248*4882a593Smuzhiyun 	mutex_unlock(&dev->alu_mutex);
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun 
ksz8795_w_table(struct ksz_device * dev,int table,u16 addr,u64 data)251*4882a593Smuzhiyun static void ksz8795_w_table(struct ksz_device *dev, int table, u16 addr,
252*4882a593Smuzhiyun 			    u64 data)
253*4882a593Smuzhiyun {
254*4882a593Smuzhiyun 	u16 ctrl_addr;
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	ctrl_addr = IND_ACC_TABLE(table) | addr;
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun 	mutex_lock(&dev->alu_mutex);
259*4882a593Smuzhiyun 	ksz_write64(dev, REG_IND_DATA_HI, data);
260*4882a593Smuzhiyun 	ksz_write16(dev, REG_IND_CTRL_0, ctrl_addr);
261*4882a593Smuzhiyun 	mutex_unlock(&dev->alu_mutex);
262*4882a593Smuzhiyun }
263*4882a593Smuzhiyun 
ksz8795_valid_dyn_entry(struct ksz_device * dev,u8 * data)264*4882a593Smuzhiyun static int ksz8795_valid_dyn_entry(struct ksz_device *dev, u8 *data)
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun 	int timeout = 100;
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	do {
269*4882a593Smuzhiyun 		ksz_read8(dev, REG_IND_DATA_CHECK, data);
270*4882a593Smuzhiyun 		timeout--;
271*4882a593Smuzhiyun 	} while ((*data & DYNAMIC_MAC_TABLE_NOT_READY) && timeout);
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	/* Entry is not ready for accessing. */
274*4882a593Smuzhiyun 	if (*data & DYNAMIC_MAC_TABLE_NOT_READY) {
275*4882a593Smuzhiyun 		return -EAGAIN;
276*4882a593Smuzhiyun 	/* Entry is ready for accessing. */
277*4882a593Smuzhiyun 	} else {
278*4882a593Smuzhiyun 		ksz_read8(dev, REG_IND_DATA_8, data);
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun 		/* There is no valid entry in the table. */
281*4882a593Smuzhiyun 		if (*data & DYNAMIC_MAC_TABLE_MAC_EMPTY)
282*4882a593Smuzhiyun 			return -ENXIO;
283*4882a593Smuzhiyun 	}
284*4882a593Smuzhiyun 	return 0;
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun 
ksz8795_r_dyn_mac_table(struct ksz_device * dev,u16 addr,u8 * mac_addr,u8 * fid,u8 * src_port,u8 * timestamp,u16 * entries)287*4882a593Smuzhiyun static int ksz8795_r_dyn_mac_table(struct ksz_device *dev, u16 addr,
288*4882a593Smuzhiyun 				   u8 *mac_addr, u8 *fid, u8 *src_port,
289*4882a593Smuzhiyun 				   u8 *timestamp, u16 *entries)
290*4882a593Smuzhiyun {
291*4882a593Smuzhiyun 	u32 data_hi, data_lo;
292*4882a593Smuzhiyun 	u16 ctrl_addr;
293*4882a593Smuzhiyun 	u8 data;
294*4882a593Smuzhiyun 	int rc;
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun 	ctrl_addr = IND_ACC_TABLE(TABLE_DYNAMIC_MAC | TABLE_READ) | addr;
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 	mutex_lock(&dev->alu_mutex);
299*4882a593Smuzhiyun 	ksz_write16(dev, REG_IND_CTRL_0, ctrl_addr);
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun 	rc = ksz8795_valid_dyn_entry(dev, &data);
302*4882a593Smuzhiyun 	if (rc == -EAGAIN) {
303*4882a593Smuzhiyun 		if (addr == 0)
304*4882a593Smuzhiyun 			*entries = 0;
305*4882a593Smuzhiyun 	} else if (rc == -ENXIO) {
306*4882a593Smuzhiyun 		*entries = 0;
307*4882a593Smuzhiyun 	/* At least one valid entry in the table. */
308*4882a593Smuzhiyun 	} else {
309*4882a593Smuzhiyun 		u64 buf = 0;
310*4882a593Smuzhiyun 		int cnt;
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 		ksz_read64(dev, REG_IND_DATA_HI, &buf);
313*4882a593Smuzhiyun 		data_hi = (u32)(buf >> 32);
314*4882a593Smuzhiyun 		data_lo = (u32)buf;
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun 		/* Check out how many valid entry in the table. */
317*4882a593Smuzhiyun 		cnt = data & DYNAMIC_MAC_TABLE_ENTRIES_H;
318*4882a593Smuzhiyun 		cnt <<= DYNAMIC_MAC_ENTRIES_H_S;
319*4882a593Smuzhiyun 		cnt |= (data_hi & DYNAMIC_MAC_TABLE_ENTRIES) >>
320*4882a593Smuzhiyun 			DYNAMIC_MAC_ENTRIES_S;
321*4882a593Smuzhiyun 		*entries = cnt + 1;
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun 		*fid = (data_hi & DYNAMIC_MAC_TABLE_FID) >>
324*4882a593Smuzhiyun 			DYNAMIC_MAC_FID_S;
325*4882a593Smuzhiyun 		*src_port = (data_hi & DYNAMIC_MAC_TABLE_SRC_PORT) >>
326*4882a593Smuzhiyun 			DYNAMIC_MAC_SRC_PORT_S;
327*4882a593Smuzhiyun 		*timestamp = (data_hi & DYNAMIC_MAC_TABLE_TIMESTAMP) >>
328*4882a593Smuzhiyun 			DYNAMIC_MAC_TIMESTAMP_S;
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun 		mac_addr[5] = (u8)data_lo;
331*4882a593Smuzhiyun 		mac_addr[4] = (u8)(data_lo >> 8);
332*4882a593Smuzhiyun 		mac_addr[3] = (u8)(data_lo >> 16);
333*4882a593Smuzhiyun 		mac_addr[2] = (u8)(data_lo >> 24);
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun 		mac_addr[1] = (u8)data_hi;
336*4882a593Smuzhiyun 		mac_addr[0] = (u8)(data_hi >> 8);
337*4882a593Smuzhiyun 		rc = 0;
338*4882a593Smuzhiyun 	}
339*4882a593Smuzhiyun 	mutex_unlock(&dev->alu_mutex);
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun 	return rc;
342*4882a593Smuzhiyun }
343*4882a593Smuzhiyun 
ksz8795_r_sta_mac_table(struct ksz_device * dev,u16 addr,struct alu_struct * alu)344*4882a593Smuzhiyun static int ksz8795_r_sta_mac_table(struct ksz_device *dev, u16 addr,
345*4882a593Smuzhiyun 				   struct alu_struct *alu)
346*4882a593Smuzhiyun {
347*4882a593Smuzhiyun 	u32 data_hi, data_lo;
348*4882a593Smuzhiyun 	u64 data;
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun 	ksz8795_r_table(dev, TABLE_STATIC_MAC, addr, &data);
351*4882a593Smuzhiyun 	data_hi = data >> 32;
352*4882a593Smuzhiyun 	data_lo = (u32)data;
353*4882a593Smuzhiyun 	if (data_hi & (STATIC_MAC_TABLE_VALID | STATIC_MAC_TABLE_OVERRIDE)) {
354*4882a593Smuzhiyun 		alu->mac[5] = (u8)data_lo;
355*4882a593Smuzhiyun 		alu->mac[4] = (u8)(data_lo >> 8);
356*4882a593Smuzhiyun 		alu->mac[3] = (u8)(data_lo >> 16);
357*4882a593Smuzhiyun 		alu->mac[2] = (u8)(data_lo >> 24);
358*4882a593Smuzhiyun 		alu->mac[1] = (u8)data_hi;
359*4882a593Smuzhiyun 		alu->mac[0] = (u8)(data_hi >> 8);
360*4882a593Smuzhiyun 		alu->port_forward = (data_hi & STATIC_MAC_TABLE_FWD_PORTS) >>
361*4882a593Smuzhiyun 			STATIC_MAC_FWD_PORTS_S;
362*4882a593Smuzhiyun 		alu->is_override =
363*4882a593Smuzhiyun 			(data_hi & STATIC_MAC_TABLE_OVERRIDE) ? 1 : 0;
364*4882a593Smuzhiyun 		data_hi >>= 1;
365*4882a593Smuzhiyun 		alu->is_use_fid = (data_hi & STATIC_MAC_TABLE_USE_FID) ? 1 : 0;
366*4882a593Smuzhiyun 		alu->fid = (data_hi & STATIC_MAC_TABLE_FID) >>
367*4882a593Smuzhiyun 			STATIC_MAC_FID_S;
368*4882a593Smuzhiyun 		return 0;
369*4882a593Smuzhiyun 	}
370*4882a593Smuzhiyun 	return -ENXIO;
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun 
ksz8795_w_sta_mac_table(struct ksz_device * dev,u16 addr,struct alu_struct * alu)373*4882a593Smuzhiyun static void ksz8795_w_sta_mac_table(struct ksz_device *dev, u16 addr,
374*4882a593Smuzhiyun 				    struct alu_struct *alu)
375*4882a593Smuzhiyun {
376*4882a593Smuzhiyun 	u32 data_hi, data_lo;
377*4882a593Smuzhiyun 	u64 data;
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun 	data_lo = ((u32)alu->mac[2] << 24) |
380*4882a593Smuzhiyun 		((u32)alu->mac[3] << 16) |
381*4882a593Smuzhiyun 		((u32)alu->mac[4] << 8) | alu->mac[5];
382*4882a593Smuzhiyun 	data_hi = ((u32)alu->mac[0] << 8) | alu->mac[1];
383*4882a593Smuzhiyun 	data_hi |= (u32)alu->port_forward << STATIC_MAC_FWD_PORTS_S;
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun 	if (alu->is_override)
386*4882a593Smuzhiyun 		data_hi |= STATIC_MAC_TABLE_OVERRIDE;
387*4882a593Smuzhiyun 	if (alu->is_use_fid) {
388*4882a593Smuzhiyun 		data_hi |= STATIC_MAC_TABLE_USE_FID;
389*4882a593Smuzhiyun 		data_hi |= (u32)alu->fid << STATIC_MAC_FID_S;
390*4882a593Smuzhiyun 	}
391*4882a593Smuzhiyun 	if (alu->is_static)
392*4882a593Smuzhiyun 		data_hi |= STATIC_MAC_TABLE_VALID;
393*4882a593Smuzhiyun 	else
394*4882a593Smuzhiyun 		data_hi &= ~STATIC_MAC_TABLE_OVERRIDE;
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun 	data = (u64)data_hi << 32 | data_lo;
397*4882a593Smuzhiyun 	ksz8795_w_table(dev, TABLE_STATIC_MAC, addr, data);
398*4882a593Smuzhiyun }
399*4882a593Smuzhiyun 
ksz8795_from_vlan(u16 vlan,u8 * fid,u8 * member,u8 * valid)400*4882a593Smuzhiyun static void ksz8795_from_vlan(u16 vlan, u8 *fid, u8 *member, u8 *valid)
401*4882a593Smuzhiyun {
402*4882a593Smuzhiyun 	*fid = vlan & VLAN_TABLE_FID;
403*4882a593Smuzhiyun 	*member = (vlan & VLAN_TABLE_MEMBERSHIP) >> VLAN_TABLE_MEMBERSHIP_S;
404*4882a593Smuzhiyun 	*valid = !!(vlan & VLAN_TABLE_VALID);
405*4882a593Smuzhiyun }
406*4882a593Smuzhiyun 
ksz8795_to_vlan(u8 fid,u8 member,u8 valid,u16 * vlan)407*4882a593Smuzhiyun static void ksz8795_to_vlan(u8 fid, u8 member, u8 valid, u16 *vlan)
408*4882a593Smuzhiyun {
409*4882a593Smuzhiyun 	*vlan = fid;
410*4882a593Smuzhiyun 	*vlan |= (u16)member << VLAN_TABLE_MEMBERSHIP_S;
411*4882a593Smuzhiyun 	if (valid)
412*4882a593Smuzhiyun 		*vlan |= VLAN_TABLE_VALID;
413*4882a593Smuzhiyun }
414*4882a593Smuzhiyun 
ksz8795_r_vlan_entries(struct ksz_device * dev,u16 addr)415*4882a593Smuzhiyun static void ksz8795_r_vlan_entries(struct ksz_device *dev, u16 addr)
416*4882a593Smuzhiyun {
417*4882a593Smuzhiyun 	u64 data;
418*4882a593Smuzhiyun 	int i;
419*4882a593Smuzhiyun 
420*4882a593Smuzhiyun 	ksz8795_r_table(dev, TABLE_VLAN, addr, &data);
421*4882a593Smuzhiyun 	addr *= 4;
422*4882a593Smuzhiyun 	for (i = 0; i < 4; i++) {
423*4882a593Smuzhiyun 		dev->vlan_cache[addr + i].table[0] = (u16)data;
424*4882a593Smuzhiyun 		data >>= VLAN_TABLE_S;
425*4882a593Smuzhiyun 	}
426*4882a593Smuzhiyun }
427*4882a593Smuzhiyun 
ksz8795_r_vlan_table(struct ksz_device * dev,u16 vid,u16 * vlan)428*4882a593Smuzhiyun static void ksz8795_r_vlan_table(struct ksz_device *dev, u16 vid, u16 *vlan)
429*4882a593Smuzhiyun {
430*4882a593Smuzhiyun 	int index;
431*4882a593Smuzhiyun 	u16 *data;
432*4882a593Smuzhiyun 	u16 addr;
433*4882a593Smuzhiyun 	u64 buf;
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun 	data = (u16 *)&buf;
436*4882a593Smuzhiyun 	addr = vid / 4;
437*4882a593Smuzhiyun 	index = vid & 3;
438*4882a593Smuzhiyun 	ksz8795_r_table(dev, TABLE_VLAN, addr, &buf);
439*4882a593Smuzhiyun 	*vlan = data[index];
440*4882a593Smuzhiyun }
441*4882a593Smuzhiyun 
ksz8795_w_vlan_table(struct ksz_device * dev,u16 vid,u16 vlan)442*4882a593Smuzhiyun static void ksz8795_w_vlan_table(struct ksz_device *dev, u16 vid, u16 vlan)
443*4882a593Smuzhiyun {
444*4882a593Smuzhiyun 	int index;
445*4882a593Smuzhiyun 	u16 *data;
446*4882a593Smuzhiyun 	u16 addr;
447*4882a593Smuzhiyun 	u64 buf;
448*4882a593Smuzhiyun 
449*4882a593Smuzhiyun 	data = (u16 *)&buf;
450*4882a593Smuzhiyun 	addr = vid / 4;
451*4882a593Smuzhiyun 	index = vid & 3;
452*4882a593Smuzhiyun 	ksz8795_r_table(dev, TABLE_VLAN, addr, &buf);
453*4882a593Smuzhiyun 	data[index] = vlan;
454*4882a593Smuzhiyun 	dev->vlan_cache[vid].table[0] = vlan;
455*4882a593Smuzhiyun 	ksz8795_w_table(dev, TABLE_VLAN, addr, buf);
456*4882a593Smuzhiyun }
457*4882a593Smuzhiyun 
ksz8795_r_phy(struct ksz_device * dev,u16 phy,u16 reg,u16 * val)458*4882a593Smuzhiyun static void ksz8795_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val)
459*4882a593Smuzhiyun {
460*4882a593Smuzhiyun 	u8 restart, speed, ctrl, link;
461*4882a593Smuzhiyun 	int processed = true;
462*4882a593Smuzhiyun 	u16 data = 0;
463*4882a593Smuzhiyun 	u8 p = phy;
464*4882a593Smuzhiyun 
465*4882a593Smuzhiyun 	switch (reg) {
466*4882a593Smuzhiyun 	case PHY_REG_CTRL:
467*4882a593Smuzhiyun 		ksz_pread8(dev, p, P_NEG_RESTART_CTRL, &restart);
468*4882a593Smuzhiyun 		ksz_pread8(dev, p, P_SPEED_STATUS, &speed);
469*4882a593Smuzhiyun 		ksz_pread8(dev, p, P_FORCE_CTRL, &ctrl);
470*4882a593Smuzhiyun 		if (restart & PORT_PHY_LOOPBACK)
471*4882a593Smuzhiyun 			data |= PHY_LOOPBACK;
472*4882a593Smuzhiyun 		if (ctrl & PORT_FORCE_100_MBIT)
473*4882a593Smuzhiyun 			data |= PHY_SPEED_100MBIT;
474*4882a593Smuzhiyun 		if (!(ctrl & PORT_AUTO_NEG_DISABLE))
475*4882a593Smuzhiyun 			data |= PHY_AUTO_NEG_ENABLE;
476*4882a593Smuzhiyun 		if (restart & PORT_POWER_DOWN)
477*4882a593Smuzhiyun 			data |= PHY_POWER_DOWN;
478*4882a593Smuzhiyun 		if (restart & PORT_AUTO_NEG_RESTART)
479*4882a593Smuzhiyun 			data |= PHY_AUTO_NEG_RESTART;
480*4882a593Smuzhiyun 		if (ctrl & PORT_FORCE_FULL_DUPLEX)
481*4882a593Smuzhiyun 			data |= PHY_FULL_DUPLEX;
482*4882a593Smuzhiyun 		if (speed & PORT_HP_MDIX)
483*4882a593Smuzhiyun 			data |= PHY_HP_MDIX;
484*4882a593Smuzhiyun 		if (restart & PORT_FORCE_MDIX)
485*4882a593Smuzhiyun 			data |= PHY_FORCE_MDIX;
486*4882a593Smuzhiyun 		if (restart & PORT_AUTO_MDIX_DISABLE)
487*4882a593Smuzhiyun 			data |= PHY_AUTO_MDIX_DISABLE;
488*4882a593Smuzhiyun 		if (restart & PORT_TX_DISABLE)
489*4882a593Smuzhiyun 			data |= PHY_TRANSMIT_DISABLE;
490*4882a593Smuzhiyun 		if (restart & PORT_LED_OFF)
491*4882a593Smuzhiyun 			data |= PHY_LED_DISABLE;
492*4882a593Smuzhiyun 		break;
493*4882a593Smuzhiyun 	case PHY_REG_STATUS:
494*4882a593Smuzhiyun 		ksz_pread8(dev, p, P_LINK_STATUS, &link);
495*4882a593Smuzhiyun 		data = PHY_100BTX_FD_CAPABLE |
496*4882a593Smuzhiyun 		       PHY_100BTX_CAPABLE |
497*4882a593Smuzhiyun 		       PHY_10BT_FD_CAPABLE |
498*4882a593Smuzhiyun 		       PHY_10BT_CAPABLE |
499*4882a593Smuzhiyun 		       PHY_AUTO_NEG_CAPABLE;
500*4882a593Smuzhiyun 		if (link & PORT_AUTO_NEG_COMPLETE)
501*4882a593Smuzhiyun 			data |= PHY_AUTO_NEG_ACKNOWLEDGE;
502*4882a593Smuzhiyun 		if (link & PORT_STAT_LINK_GOOD)
503*4882a593Smuzhiyun 			data |= PHY_LINK_STATUS;
504*4882a593Smuzhiyun 		break;
505*4882a593Smuzhiyun 	case PHY_REG_ID_1:
506*4882a593Smuzhiyun 		data = KSZ8795_ID_HI;
507*4882a593Smuzhiyun 		break;
508*4882a593Smuzhiyun 	case PHY_REG_ID_2:
509*4882a593Smuzhiyun 		data = KSZ8795_ID_LO;
510*4882a593Smuzhiyun 		break;
511*4882a593Smuzhiyun 	case PHY_REG_AUTO_NEGOTIATION:
512*4882a593Smuzhiyun 		ksz_pread8(dev, p, P_LOCAL_CTRL, &ctrl);
513*4882a593Smuzhiyun 		data = PHY_AUTO_NEG_802_3;
514*4882a593Smuzhiyun 		if (ctrl & PORT_AUTO_NEG_SYM_PAUSE)
515*4882a593Smuzhiyun 			data |= PHY_AUTO_NEG_SYM_PAUSE;
516*4882a593Smuzhiyun 		if (ctrl & PORT_AUTO_NEG_100BTX_FD)
517*4882a593Smuzhiyun 			data |= PHY_AUTO_NEG_100BTX_FD;
518*4882a593Smuzhiyun 		if (ctrl & PORT_AUTO_NEG_100BTX)
519*4882a593Smuzhiyun 			data |= PHY_AUTO_NEG_100BTX;
520*4882a593Smuzhiyun 		if (ctrl & PORT_AUTO_NEG_10BT_FD)
521*4882a593Smuzhiyun 			data |= PHY_AUTO_NEG_10BT_FD;
522*4882a593Smuzhiyun 		if (ctrl & PORT_AUTO_NEG_10BT)
523*4882a593Smuzhiyun 			data |= PHY_AUTO_NEG_10BT;
524*4882a593Smuzhiyun 		break;
525*4882a593Smuzhiyun 	case PHY_REG_REMOTE_CAPABILITY:
526*4882a593Smuzhiyun 		ksz_pread8(dev, p, P_REMOTE_STATUS, &link);
527*4882a593Smuzhiyun 		data = PHY_AUTO_NEG_802_3;
528*4882a593Smuzhiyun 		if (link & PORT_REMOTE_SYM_PAUSE)
529*4882a593Smuzhiyun 			data |= PHY_AUTO_NEG_SYM_PAUSE;
530*4882a593Smuzhiyun 		if (link & PORT_REMOTE_100BTX_FD)
531*4882a593Smuzhiyun 			data |= PHY_AUTO_NEG_100BTX_FD;
532*4882a593Smuzhiyun 		if (link & PORT_REMOTE_100BTX)
533*4882a593Smuzhiyun 			data |= PHY_AUTO_NEG_100BTX;
534*4882a593Smuzhiyun 		if (link & PORT_REMOTE_10BT_FD)
535*4882a593Smuzhiyun 			data |= PHY_AUTO_NEG_10BT_FD;
536*4882a593Smuzhiyun 		if (link & PORT_REMOTE_10BT)
537*4882a593Smuzhiyun 			data |= PHY_AUTO_NEG_10BT;
538*4882a593Smuzhiyun 		if (data & ~PHY_AUTO_NEG_802_3)
539*4882a593Smuzhiyun 			data |= PHY_REMOTE_ACKNOWLEDGE_NOT;
540*4882a593Smuzhiyun 		break;
541*4882a593Smuzhiyun 	default:
542*4882a593Smuzhiyun 		processed = false;
543*4882a593Smuzhiyun 		break;
544*4882a593Smuzhiyun 	}
545*4882a593Smuzhiyun 	if (processed)
546*4882a593Smuzhiyun 		*val = data;
547*4882a593Smuzhiyun }
548*4882a593Smuzhiyun 
ksz8795_w_phy(struct ksz_device * dev,u16 phy,u16 reg,u16 val)549*4882a593Smuzhiyun static void ksz8795_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val)
550*4882a593Smuzhiyun {
551*4882a593Smuzhiyun 	u8 p = phy;
552*4882a593Smuzhiyun 	u8 restart, speed, ctrl, data;
553*4882a593Smuzhiyun 
554*4882a593Smuzhiyun 	switch (reg) {
555*4882a593Smuzhiyun 	case PHY_REG_CTRL:
556*4882a593Smuzhiyun 
557*4882a593Smuzhiyun 		/* Do not support PHY reset function. */
558*4882a593Smuzhiyun 		if (val & PHY_RESET)
559*4882a593Smuzhiyun 			break;
560*4882a593Smuzhiyun 		ksz_pread8(dev, p, P_SPEED_STATUS, &speed);
561*4882a593Smuzhiyun 		data = speed;
562*4882a593Smuzhiyun 		if (val & PHY_HP_MDIX)
563*4882a593Smuzhiyun 			data |= PORT_HP_MDIX;
564*4882a593Smuzhiyun 		else
565*4882a593Smuzhiyun 			data &= ~PORT_HP_MDIX;
566*4882a593Smuzhiyun 		if (data != speed)
567*4882a593Smuzhiyun 			ksz_pwrite8(dev, p, P_SPEED_STATUS, data);
568*4882a593Smuzhiyun 		ksz_pread8(dev, p, P_FORCE_CTRL, &ctrl);
569*4882a593Smuzhiyun 		data = ctrl;
570*4882a593Smuzhiyun 		if (!(val & PHY_AUTO_NEG_ENABLE))
571*4882a593Smuzhiyun 			data |= PORT_AUTO_NEG_DISABLE;
572*4882a593Smuzhiyun 		else
573*4882a593Smuzhiyun 			data &= ~PORT_AUTO_NEG_DISABLE;
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun 		/* Fiber port does not support auto-negotiation. */
576*4882a593Smuzhiyun 		if (dev->ports[p].fiber)
577*4882a593Smuzhiyun 			data |= PORT_AUTO_NEG_DISABLE;
578*4882a593Smuzhiyun 		if (val & PHY_SPEED_100MBIT)
579*4882a593Smuzhiyun 			data |= PORT_FORCE_100_MBIT;
580*4882a593Smuzhiyun 		else
581*4882a593Smuzhiyun 			data &= ~PORT_FORCE_100_MBIT;
582*4882a593Smuzhiyun 		if (val & PHY_FULL_DUPLEX)
583*4882a593Smuzhiyun 			data |= PORT_FORCE_FULL_DUPLEX;
584*4882a593Smuzhiyun 		else
585*4882a593Smuzhiyun 			data &= ~PORT_FORCE_FULL_DUPLEX;
586*4882a593Smuzhiyun 		if (data != ctrl)
587*4882a593Smuzhiyun 			ksz_pwrite8(dev, p, P_FORCE_CTRL, data);
588*4882a593Smuzhiyun 		ksz_pread8(dev, p, P_NEG_RESTART_CTRL, &restart);
589*4882a593Smuzhiyun 		data = restart;
590*4882a593Smuzhiyun 		if (val & PHY_LED_DISABLE)
591*4882a593Smuzhiyun 			data |= PORT_LED_OFF;
592*4882a593Smuzhiyun 		else
593*4882a593Smuzhiyun 			data &= ~PORT_LED_OFF;
594*4882a593Smuzhiyun 		if (val & PHY_TRANSMIT_DISABLE)
595*4882a593Smuzhiyun 			data |= PORT_TX_DISABLE;
596*4882a593Smuzhiyun 		else
597*4882a593Smuzhiyun 			data &= ~PORT_TX_DISABLE;
598*4882a593Smuzhiyun 		if (val & PHY_AUTO_NEG_RESTART)
599*4882a593Smuzhiyun 			data |= PORT_AUTO_NEG_RESTART;
600*4882a593Smuzhiyun 		else
601*4882a593Smuzhiyun 			data &= ~(PORT_AUTO_NEG_RESTART);
602*4882a593Smuzhiyun 		if (val & PHY_POWER_DOWN)
603*4882a593Smuzhiyun 			data |= PORT_POWER_DOWN;
604*4882a593Smuzhiyun 		else
605*4882a593Smuzhiyun 			data &= ~PORT_POWER_DOWN;
606*4882a593Smuzhiyun 		if (val & PHY_AUTO_MDIX_DISABLE)
607*4882a593Smuzhiyun 			data |= PORT_AUTO_MDIX_DISABLE;
608*4882a593Smuzhiyun 		else
609*4882a593Smuzhiyun 			data &= ~PORT_AUTO_MDIX_DISABLE;
610*4882a593Smuzhiyun 		if (val & PHY_FORCE_MDIX)
611*4882a593Smuzhiyun 			data |= PORT_FORCE_MDIX;
612*4882a593Smuzhiyun 		else
613*4882a593Smuzhiyun 			data &= ~PORT_FORCE_MDIX;
614*4882a593Smuzhiyun 		if (val & PHY_LOOPBACK)
615*4882a593Smuzhiyun 			data |= PORT_PHY_LOOPBACK;
616*4882a593Smuzhiyun 		else
617*4882a593Smuzhiyun 			data &= ~PORT_PHY_LOOPBACK;
618*4882a593Smuzhiyun 		if (data != restart)
619*4882a593Smuzhiyun 			ksz_pwrite8(dev, p, P_NEG_RESTART_CTRL, data);
620*4882a593Smuzhiyun 		break;
621*4882a593Smuzhiyun 	case PHY_REG_AUTO_NEGOTIATION:
622*4882a593Smuzhiyun 		ksz_pread8(dev, p, P_LOCAL_CTRL, &ctrl);
623*4882a593Smuzhiyun 		data = ctrl;
624*4882a593Smuzhiyun 		data &= ~(PORT_AUTO_NEG_SYM_PAUSE |
625*4882a593Smuzhiyun 			  PORT_AUTO_NEG_100BTX_FD |
626*4882a593Smuzhiyun 			  PORT_AUTO_NEG_100BTX |
627*4882a593Smuzhiyun 			  PORT_AUTO_NEG_10BT_FD |
628*4882a593Smuzhiyun 			  PORT_AUTO_NEG_10BT);
629*4882a593Smuzhiyun 		if (val & PHY_AUTO_NEG_SYM_PAUSE)
630*4882a593Smuzhiyun 			data |= PORT_AUTO_NEG_SYM_PAUSE;
631*4882a593Smuzhiyun 		if (val & PHY_AUTO_NEG_100BTX_FD)
632*4882a593Smuzhiyun 			data |= PORT_AUTO_NEG_100BTX_FD;
633*4882a593Smuzhiyun 		if (val & PHY_AUTO_NEG_100BTX)
634*4882a593Smuzhiyun 			data |= PORT_AUTO_NEG_100BTX;
635*4882a593Smuzhiyun 		if (val & PHY_AUTO_NEG_10BT_FD)
636*4882a593Smuzhiyun 			data |= PORT_AUTO_NEG_10BT_FD;
637*4882a593Smuzhiyun 		if (val & PHY_AUTO_NEG_10BT)
638*4882a593Smuzhiyun 			data |= PORT_AUTO_NEG_10BT;
639*4882a593Smuzhiyun 		if (data != ctrl)
640*4882a593Smuzhiyun 			ksz_pwrite8(dev, p, P_LOCAL_CTRL, data);
641*4882a593Smuzhiyun 		break;
642*4882a593Smuzhiyun 	default:
643*4882a593Smuzhiyun 		break;
644*4882a593Smuzhiyun 	}
645*4882a593Smuzhiyun }
646*4882a593Smuzhiyun 
ksz8795_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mp)647*4882a593Smuzhiyun static enum dsa_tag_protocol ksz8795_get_tag_protocol(struct dsa_switch *ds,
648*4882a593Smuzhiyun 						      int port,
649*4882a593Smuzhiyun 						      enum dsa_tag_protocol mp)
650*4882a593Smuzhiyun {
651*4882a593Smuzhiyun 	return DSA_TAG_PROTO_KSZ8795;
652*4882a593Smuzhiyun }
653*4882a593Smuzhiyun 
ksz8795_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * buf)654*4882a593Smuzhiyun static void ksz8795_get_strings(struct dsa_switch *ds, int port,
655*4882a593Smuzhiyun 				u32 stringset, uint8_t *buf)
656*4882a593Smuzhiyun {
657*4882a593Smuzhiyun 	int i;
658*4882a593Smuzhiyun 
659*4882a593Smuzhiyun 	for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) {
660*4882a593Smuzhiyun 		memcpy(buf + i * ETH_GSTRING_LEN, mib_names[i].string,
661*4882a593Smuzhiyun 		       ETH_GSTRING_LEN);
662*4882a593Smuzhiyun 	}
663*4882a593Smuzhiyun }
664*4882a593Smuzhiyun 
ksz8795_cfg_port_member(struct ksz_device * dev,int port,u8 member)665*4882a593Smuzhiyun static void ksz8795_cfg_port_member(struct ksz_device *dev, int port,
666*4882a593Smuzhiyun 				    u8 member)
667*4882a593Smuzhiyun {
668*4882a593Smuzhiyun 	u8 data;
669*4882a593Smuzhiyun 
670*4882a593Smuzhiyun 	ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
671*4882a593Smuzhiyun 	data &= ~PORT_VLAN_MEMBERSHIP;
672*4882a593Smuzhiyun 	data |= (member & dev->port_mask);
673*4882a593Smuzhiyun 	ksz_pwrite8(dev, port, P_MIRROR_CTRL, data);
674*4882a593Smuzhiyun 	dev->ports[port].member = member;
675*4882a593Smuzhiyun }
676*4882a593Smuzhiyun 
ksz8795_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)677*4882a593Smuzhiyun static void ksz8795_port_stp_state_set(struct dsa_switch *ds, int port,
678*4882a593Smuzhiyun 				       u8 state)
679*4882a593Smuzhiyun {
680*4882a593Smuzhiyun 	struct ksz_device *dev = ds->priv;
681*4882a593Smuzhiyun 	int forward = dev->member;
682*4882a593Smuzhiyun 	struct ksz_port *p;
683*4882a593Smuzhiyun 	int member = -1;
684*4882a593Smuzhiyun 	u8 data;
685*4882a593Smuzhiyun 
686*4882a593Smuzhiyun 	p = &dev->ports[port];
687*4882a593Smuzhiyun 
688*4882a593Smuzhiyun 	ksz_pread8(dev, port, P_STP_CTRL, &data);
689*4882a593Smuzhiyun 	data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
690*4882a593Smuzhiyun 
691*4882a593Smuzhiyun 	switch (state) {
692*4882a593Smuzhiyun 	case BR_STATE_DISABLED:
693*4882a593Smuzhiyun 		data |= PORT_LEARN_DISABLE;
694*4882a593Smuzhiyun 		if (port < SWITCH_PORT_NUM)
695*4882a593Smuzhiyun 			member = 0;
696*4882a593Smuzhiyun 		break;
697*4882a593Smuzhiyun 	case BR_STATE_LISTENING:
698*4882a593Smuzhiyun 		data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
699*4882a593Smuzhiyun 		if (port < SWITCH_PORT_NUM &&
700*4882a593Smuzhiyun 		    p->stp_state == BR_STATE_DISABLED)
701*4882a593Smuzhiyun 			member = dev->host_mask | p->vid_member;
702*4882a593Smuzhiyun 		break;
703*4882a593Smuzhiyun 	case BR_STATE_LEARNING:
704*4882a593Smuzhiyun 		data |= PORT_RX_ENABLE;
705*4882a593Smuzhiyun 		break;
706*4882a593Smuzhiyun 	case BR_STATE_FORWARDING:
707*4882a593Smuzhiyun 		data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
708*4882a593Smuzhiyun 
709*4882a593Smuzhiyun 		/* This function is also used internally. */
710*4882a593Smuzhiyun 		if (port == dev->cpu_port)
711*4882a593Smuzhiyun 			break;
712*4882a593Smuzhiyun 
713*4882a593Smuzhiyun 		/* Port is a member of a bridge. */
714*4882a593Smuzhiyun 		if (dev->br_member & BIT(port)) {
715*4882a593Smuzhiyun 			dev->member |= BIT(port);
716*4882a593Smuzhiyun 			member = dev->member;
717*4882a593Smuzhiyun 		} else {
718*4882a593Smuzhiyun 			member = dev->host_mask | p->vid_member;
719*4882a593Smuzhiyun 		}
720*4882a593Smuzhiyun 		break;
721*4882a593Smuzhiyun 	case BR_STATE_BLOCKING:
722*4882a593Smuzhiyun 		data |= PORT_LEARN_DISABLE;
723*4882a593Smuzhiyun 		if (port < SWITCH_PORT_NUM &&
724*4882a593Smuzhiyun 		    p->stp_state == BR_STATE_DISABLED)
725*4882a593Smuzhiyun 			member = dev->host_mask | p->vid_member;
726*4882a593Smuzhiyun 		break;
727*4882a593Smuzhiyun 	default:
728*4882a593Smuzhiyun 		dev_err(ds->dev, "invalid STP state: %d\n", state);
729*4882a593Smuzhiyun 		return;
730*4882a593Smuzhiyun 	}
731*4882a593Smuzhiyun 
732*4882a593Smuzhiyun 	ksz_pwrite8(dev, port, P_STP_CTRL, data);
733*4882a593Smuzhiyun 	p->stp_state = state;
734*4882a593Smuzhiyun 	/* Port membership may share register with STP state. */
735*4882a593Smuzhiyun 	if (member >= 0 && member != p->member)
736*4882a593Smuzhiyun 		ksz8795_cfg_port_member(dev, port, (u8)member);
737*4882a593Smuzhiyun 
738*4882a593Smuzhiyun 	/* Check if forwarding needs to be updated. */
739*4882a593Smuzhiyun 	if (state != BR_STATE_FORWARDING) {
740*4882a593Smuzhiyun 		if (dev->br_member & BIT(port))
741*4882a593Smuzhiyun 			dev->member &= ~BIT(port);
742*4882a593Smuzhiyun 	}
743*4882a593Smuzhiyun 
744*4882a593Smuzhiyun 	/* When topology has changed the function ksz_update_port_member
745*4882a593Smuzhiyun 	 * should be called to modify port forwarding behavior.
746*4882a593Smuzhiyun 	 */
747*4882a593Smuzhiyun 	if (forward != dev->member)
748*4882a593Smuzhiyun 		ksz_update_port_member(dev, port);
749*4882a593Smuzhiyun }
750*4882a593Smuzhiyun 
ksz8795_flush_dyn_mac_table(struct ksz_device * dev,int port)751*4882a593Smuzhiyun static void ksz8795_flush_dyn_mac_table(struct ksz_device *dev, int port)
752*4882a593Smuzhiyun {
753*4882a593Smuzhiyun 	u8 learn[TOTAL_PORT_NUM];
754*4882a593Smuzhiyun 	int first, index, cnt;
755*4882a593Smuzhiyun 	struct ksz_port *p;
756*4882a593Smuzhiyun 
757*4882a593Smuzhiyun 	if ((uint)port < TOTAL_PORT_NUM) {
758*4882a593Smuzhiyun 		first = port;
759*4882a593Smuzhiyun 		cnt = port + 1;
760*4882a593Smuzhiyun 	} else {
761*4882a593Smuzhiyun 		/* Flush all ports. */
762*4882a593Smuzhiyun 		first = 0;
763*4882a593Smuzhiyun 		cnt = dev->mib_port_cnt;
764*4882a593Smuzhiyun 	}
765*4882a593Smuzhiyun 	for (index = first; index < cnt; index++) {
766*4882a593Smuzhiyun 		p = &dev->ports[index];
767*4882a593Smuzhiyun 		if (!p->on)
768*4882a593Smuzhiyun 			continue;
769*4882a593Smuzhiyun 		ksz_pread8(dev, index, P_STP_CTRL, &learn[index]);
770*4882a593Smuzhiyun 		if (!(learn[index] & PORT_LEARN_DISABLE))
771*4882a593Smuzhiyun 			ksz_pwrite8(dev, index, P_STP_CTRL,
772*4882a593Smuzhiyun 				    learn[index] | PORT_LEARN_DISABLE);
773*4882a593Smuzhiyun 	}
774*4882a593Smuzhiyun 	ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true);
775*4882a593Smuzhiyun 	for (index = first; index < cnt; index++) {
776*4882a593Smuzhiyun 		p = &dev->ports[index];
777*4882a593Smuzhiyun 		if (!p->on)
778*4882a593Smuzhiyun 			continue;
779*4882a593Smuzhiyun 		if (!(learn[index] & PORT_LEARN_DISABLE))
780*4882a593Smuzhiyun 			ksz_pwrite8(dev, index, P_STP_CTRL, learn[index]);
781*4882a593Smuzhiyun 	}
782*4882a593Smuzhiyun }
783*4882a593Smuzhiyun 
ksz8795_port_vlan_filtering(struct dsa_switch * ds,int port,bool flag,struct switchdev_trans * trans)784*4882a593Smuzhiyun static int ksz8795_port_vlan_filtering(struct dsa_switch *ds, int port,
785*4882a593Smuzhiyun 				       bool flag,
786*4882a593Smuzhiyun 				       struct switchdev_trans *trans)
787*4882a593Smuzhiyun {
788*4882a593Smuzhiyun 	struct ksz_device *dev = ds->priv;
789*4882a593Smuzhiyun 
790*4882a593Smuzhiyun 	if (switchdev_trans_ph_prepare(trans))
791*4882a593Smuzhiyun 		return 0;
792*4882a593Smuzhiyun 
793*4882a593Smuzhiyun 	/* Discard packets with VID not enabled on the switch */
794*4882a593Smuzhiyun 	ksz_cfg(dev, S_MIRROR_CTRL, SW_VLAN_ENABLE, flag);
795*4882a593Smuzhiyun 
796*4882a593Smuzhiyun 	/* Discard packets with VID not enabled on the ingress port */
797*4882a593Smuzhiyun 	for (port = 0; port < dev->phy_port_cnt; ++port)
798*4882a593Smuzhiyun 		ksz_port_cfg(dev, port, REG_PORT_CTRL_2, PORT_INGRESS_FILTER,
799*4882a593Smuzhiyun 			     flag);
800*4882a593Smuzhiyun 
801*4882a593Smuzhiyun 	return 0;
802*4882a593Smuzhiyun }
803*4882a593Smuzhiyun 
ksz8795_port_vlan_changes_remove_tag(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)804*4882a593Smuzhiyun static bool ksz8795_port_vlan_changes_remove_tag(
805*4882a593Smuzhiyun 	struct dsa_switch *ds, int port,
806*4882a593Smuzhiyun 	const struct switchdev_obj_port_vlan *vlan)
807*4882a593Smuzhiyun {
808*4882a593Smuzhiyun 	bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
809*4882a593Smuzhiyun 	struct ksz_device *dev = ds->priv;
810*4882a593Smuzhiyun 	struct ksz_port *p = &dev->ports[port];
811*4882a593Smuzhiyun 
812*4882a593Smuzhiyun 	/* If a VLAN is added with untagged flag different from the
813*4882a593Smuzhiyun 	 * port's Remove Tag flag, we need to change the latter.
814*4882a593Smuzhiyun 	 * Ignore VID 0, which is always untagged.
815*4882a593Smuzhiyun 	 * Ignore CPU port, which will always be tagged.
816*4882a593Smuzhiyun 	 */
817*4882a593Smuzhiyun 	return untagged != p->remove_tag &&
818*4882a593Smuzhiyun 		!(vlan->vid_begin == 0 && vlan->vid_end == 0) &&
819*4882a593Smuzhiyun 		port != dev->cpu_port;
820*4882a593Smuzhiyun }
821*4882a593Smuzhiyun 
ksz8795_port_vlan_prepare(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)822*4882a593Smuzhiyun int ksz8795_port_vlan_prepare(struct dsa_switch *ds, int port,
823*4882a593Smuzhiyun 			      const struct switchdev_obj_port_vlan *vlan)
824*4882a593Smuzhiyun {
825*4882a593Smuzhiyun 	struct ksz_device *dev = ds->priv;
826*4882a593Smuzhiyun 
827*4882a593Smuzhiyun 	/* Reject attempts to add a VLAN that requires the Remove Tag
828*4882a593Smuzhiyun 	 * flag to be changed, unless there are no other VLANs
829*4882a593Smuzhiyun 	 * currently configured.
830*4882a593Smuzhiyun 	 */
831*4882a593Smuzhiyun 	if (ksz8795_port_vlan_changes_remove_tag(ds, port, vlan)) {
832*4882a593Smuzhiyun 		unsigned int vid;
833*4882a593Smuzhiyun 
834*4882a593Smuzhiyun 		for (vid = 1; vid < dev->num_vlans; ++vid) {
835*4882a593Smuzhiyun 			u8 fid, member, valid;
836*4882a593Smuzhiyun 
837*4882a593Smuzhiyun 			/* Skip the VIDs we are going to add or reconfigure */
838*4882a593Smuzhiyun 			if (vid == vlan->vid_begin) {
839*4882a593Smuzhiyun 				vid = vlan->vid_end;
840*4882a593Smuzhiyun 				continue;
841*4882a593Smuzhiyun 			}
842*4882a593Smuzhiyun 
843*4882a593Smuzhiyun 			ksz8795_from_vlan(dev->vlan_cache[vid].table[0],
844*4882a593Smuzhiyun 					  &fid, &member, &valid);
845*4882a593Smuzhiyun 			if (valid && (member & BIT(port)))
846*4882a593Smuzhiyun 				return -EINVAL;
847*4882a593Smuzhiyun 		}
848*4882a593Smuzhiyun 	}
849*4882a593Smuzhiyun 
850*4882a593Smuzhiyun 	return ksz_port_vlan_prepare(ds, port, vlan);
851*4882a593Smuzhiyun }
852*4882a593Smuzhiyun 
ksz8795_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)853*4882a593Smuzhiyun static void ksz8795_port_vlan_add(struct dsa_switch *ds, int port,
854*4882a593Smuzhiyun 				  const struct switchdev_obj_port_vlan *vlan)
855*4882a593Smuzhiyun {
856*4882a593Smuzhiyun 	bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
857*4882a593Smuzhiyun 	struct ksz_device *dev = ds->priv;
858*4882a593Smuzhiyun 	struct ksz_port *p = &dev->ports[port];
859*4882a593Smuzhiyun 	u16 data, vid, new_pvid = 0;
860*4882a593Smuzhiyun 	u8 fid, member, valid;
861*4882a593Smuzhiyun 
862*4882a593Smuzhiyun 	if (ksz8795_port_vlan_changes_remove_tag(ds, port, vlan)) {
863*4882a593Smuzhiyun 		ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged);
864*4882a593Smuzhiyun 		p->remove_tag = untagged;
865*4882a593Smuzhiyun 	}
866*4882a593Smuzhiyun 
867*4882a593Smuzhiyun 	for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
868*4882a593Smuzhiyun 		ksz8795_r_vlan_table(dev, vid, &data);
869*4882a593Smuzhiyun 		ksz8795_from_vlan(data, &fid, &member, &valid);
870*4882a593Smuzhiyun 
871*4882a593Smuzhiyun 		/* First time to setup the VLAN entry. */
872*4882a593Smuzhiyun 		if (!valid) {
873*4882a593Smuzhiyun 			/* Need to find a way to map VID to FID. */
874*4882a593Smuzhiyun 			fid = 1;
875*4882a593Smuzhiyun 			valid = 1;
876*4882a593Smuzhiyun 		}
877*4882a593Smuzhiyun 		member |= BIT(port);
878*4882a593Smuzhiyun 
879*4882a593Smuzhiyun 		ksz8795_to_vlan(fid, member, valid, &data);
880*4882a593Smuzhiyun 		ksz8795_w_vlan_table(dev, vid, data);
881*4882a593Smuzhiyun 
882*4882a593Smuzhiyun 		/* change PVID */
883*4882a593Smuzhiyun 		if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
884*4882a593Smuzhiyun 			new_pvid = vid;
885*4882a593Smuzhiyun 	}
886*4882a593Smuzhiyun 
887*4882a593Smuzhiyun 	if (new_pvid) {
888*4882a593Smuzhiyun 		ksz_pread16(dev, port, REG_PORT_CTRL_VID, &vid);
889*4882a593Smuzhiyun 		vid &= ~VLAN_VID_MASK;
890*4882a593Smuzhiyun 		vid |= new_pvid;
891*4882a593Smuzhiyun 		ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, vid);
892*4882a593Smuzhiyun 
893*4882a593Smuzhiyun 		ksz_pwrite8(dev, port, REG_PORT_CTRL_12, 0x0f);
894*4882a593Smuzhiyun 	}
895*4882a593Smuzhiyun }
896*4882a593Smuzhiyun 
ksz8795_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)897*4882a593Smuzhiyun static int ksz8795_port_vlan_del(struct dsa_switch *ds, int port,
898*4882a593Smuzhiyun 				 const struct switchdev_obj_port_vlan *vlan)
899*4882a593Smuzhiyun {
900*4882a593Smuzhiyun 	struct ksz_device *dev = ds->priv;
901*4882a593Smuzhiyun 	u16 data, vid, pvid;
902*4882a593Smuzhiyun 	u8 fid, member, valid;
903*4882a593Smuzhiyun 	bool del_pvid = false;
904*4882a593Smuzhiyun 
905*4882a593Smuzhiyun 	ksz_pread16(dev, port, REG_PORT_CTRL_VID, &pvid);
906*4882a593Smuzhiyun 	pvid = pvid & 0xFFF;
907*4882a593Smuzhiyun 
908*4882a593Smuzhiyun 	for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
909*4882a593Smuzhiyun 		ksz8795_r_vlan_table(dev, vid, &data);
910*4882a593Smuzhiyun 		ksz8795_from_vlan(data, &fid, &member, &valid);
911*4882a593Smuzhiyun 
912*4882a593Smuzhiyun 		member &= ~BIT(port);
913*4882a593Smuzhiyun 
914*4882a593Smuzhiyun 		/* Invalidate the entry if no more member. */
915*4882a593Smuzhiyun 		if (!member) {
916*4882a593Smuzhiyun 			fid = 0;
917*4882a593Smuzhiyun 			valid = 0;
918*4882a593Smuzhiyun 		}
919*4882a593Smuzhiyun 
920*4882a593Smuzhiyun 		if (pvid == vid)
921*4882a593Smuzhiyun 			del_pvid = true;
922*4882a593Smuzhiyun 
923*4882a593Smuzhiyun 		ksz8795_to_vlan(fid, member, valid, &data);
924*4882a593Smuzhiyun 		ksz8795_w_vlan_table(dev, vid, data);
925*4882a593Smuzhiyun 	}
926*4882a593Smuzhiyun 
927*4882a593Smuzhiyun 	if (del_pvid)
928*4882a593Smuzhiyun 		ksz_pwrite8(dev, port, REG_PORT_CTRL_12, 0x00);
929*4882a593Smuzhiyun 
930*4882a593Smuzhiyun 	return 0;
931*4882a593Smuzhiyun }
932*4882a593Smuzhiyun 
ksz8795_port_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress)933*4882a593Smuzhiyun static int ksz8795_port_mirror_add(struct dsa_switch *ds, int port,
934*4882a593Smuzhiyun 				   struct dsa_mall_mirror_tc_entry *mirror,
935*4882a593Smuzhiyun 				   bool ingress)
936*4882a593Smuzhiyun {
937*4882a593Smuzhiyun 	struct ksz_device *dev = ds->priv;
938*4882a593Smuzhiyun 
939*4882a593Smuzhiyun 	if (ingress) {
940*4882a593Smuzhiyun 		ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true);
941*4882a593Smuzhiyun 		dev->mirror_rx |= BIT(port);
942*4882a593Smuzhiyun 	} else {
943*4882a593Smuzhiyun 		ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true);
944*4882a593Smuzhiyun 		dev->mirror_tx |= BIT(port);
945*4882a593Smuzhiyun 	}
946*4882a593Smuzhiyun 
947*4882a593Smuzhiyun 	ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false);
948*4882a593Smuzhiyun 
949*4882a593Smuzhiyun 	/* configure mirror port */
950*4882a593Smuzhiyun 	if (dev->mirror_rx || dev->mirror_tx)
951*4882a593Smuzhiyun 		ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
952*4882a593Smuzhiyun 			     PORT_MIRROR_SNIFFER, true);
953*4882a593Smuzhiyun 
954*4882a593Smuzhiyun 	return 0;
955*4882a593Smuzhiyun }
956*4882a593Smuzhiyun 
ksz8795_port_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)957*4882a593Smuzhiyun static void ksz8795_port_mirror_del(struct dsa_switch *ds, int port,
958*4882a593Smuzhiyun 				    struct dsa_mall_mirror_tc_entry *mirror)
959*4882a593Smuzhiyun {
960*4882a593Smuzhiyun 	struct ksz_device *dev = ds->priv;
961*4882a593Smuzhiyun 	u8 data;
962*4882a593Smuzhiyun 
963*4882a593Smuzhiyun 	if (mirror->ingress) {
964*4882a593Smuzhiyun 		ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false);
965*4882a593Smuzhiyun 		dev->mirror_rx &= ~BIT(port);
966*4882a593Smuzhiyun 	} else {
967*4882a593Smuzhiyun 		ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false);
968*4882a593Smuzhiyun 		dev->mirror_tx &= ~BIT(port);
969*4882a593Smuzhiyun 	}
970*4882a593Smuzhiyun 
971*4882a593Smuzhiyun 	ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
972*4882a593Smuzhiyun 
973*4882a593Smuzhiyun 	if (!dev->mirror_rx && !dev->mirror_tx)
974*4882a593Smuzhiyun 		ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
975*4882a593Smuzhiyun 			     PORT_MIRROR_SNIFFER, false);
976*4882a593Smuzhiyun }
977*4882a593Smuzhiyun 
ksz8795_port_setup(struct ksz_device * dev,int port,bool cpu_port)978*4882a593Smuzhiyun static void ksz8795_port_setup(struct ksz_device *dev, int port, bool cpu_port)
979*4882a593Smuzhiyun {
980*4882a593Smuzhiyun 	struct ksz_port *p = &dev->ports[port];
981*4882a593Smuzhiyun 	u8 data8, member;
982*4882a593Smuzhiyun 
983*4882a593Smuzhiyun 	/* enable broadcast storm limit */
984*4882a593Smuzhiyun 	ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true);
985*4882a593Smuzhiyun 
986*4882a593Smuzhiyun 	ksz8795_set_prio_queue(dev, port, 4);
987*4882a593Smuzhiyun 
988*4882a593Smuzhiyun 	/* disable DiffServ priority */
989*4882a593Smuzhiyun 	ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_ENABLE, false);
990*4882a593Smuzhiyun 
991*4882a593Smuzhiyun 	/* replace priority */
992*4882a593Smuzhiyun 	ksz_port_cfg(dev, port, P_802_1P_CTRL, PORT_802_1P_REMAPPING, false);
993*4882a593Smuzhiyun 
994*4882a593Smuzhiyun 	/* enable 802.1p priority */
995*4882a593Smuzhiyun 	ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_ENABLE, true);
996*4882a593Smuzhiyun 
997*4882a593Smuzhiyun 	if (cpu_port) {
998*4882a593Smuzhiyun 		if (!p->interface && dev->compat_interface) {
999*4882a593Smuzhiyun 			dev_warn(dev->dev,
1000*4882a593Smuzhiyun 				 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. "
1001*4882a593Smuzhiyun 				 "Please update your device tree.\n",
1002*4882a593Smuzhiyun 				 port);
1003*4882a593Smuzhiyun 			p->interface = dev->compat_interface;
1004*4882a593Smuzhiyun 		}
1005*4882a593Smuzhiyun 
1006*4882a593Smuzhiyun 		/* Configure MII interface for proper network communication. */
1007*4882a593Smuzhiyun 		ksz_read8(dev, REG_PORT_5_CTRL_6, &data8);
1008*4882a593Smuzhiyun 		data8 &= ~PORT_INTERFACE_TYPE;
1009*4882a593Smuzhiyun 		data8 &= ~PORT_GMII_1GPS_MODE;
1010*4882a593Smuzhiyun 		switch (p->interface) {
1011*4882a593Smuzhiyun 		case PHY_INTERFACE_MODE_MII:
1012*4882a593Smuzhiyun 			p->phydev.speed = SPEED_100;
1013*4882a593Smuzhiyun 			break;
1014*4882a593Smuzhiyun 		case PHY_INTERFACE_MODE_RMII:
1015*4882a593Smuzhiyun 			data8 |= PORT_INTERFACE_RMII;
1016*4882a593Smuzhiyun 			p->phydev.speed = SPEED_100;
1017*4882a593Smuzhiyun 			break;
1018*4882a593Smuzhiyun 		case PHY_INTERFACE_MODE_GMII:
1019*4882a593Smuzhiyun 			data8 |= PORT_GMII_1GPS_MODE;
1020*4882a593Smuzhiyun 			data8 |= PORT_INTERFACE_GMII;
1021*4882a593Smuzhiyun 			p->phydev.speed = SPEED_1000;
1022*4882a593Smuzhiyun 			break;
1023*4882a593Smuzhiyun 		default:
1024*4882a593Smuzhiyun 			data8 &= ~PORT_RGMII_ID_IN_ENABLE;
1025*4882a593Smuzhiyun 			data8 &= ~PORT_RGMII_ID_OUT_ENABLE;
1026*4882a593Smuzhiyun 			if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1027*4882a593Smuzhiyun 			    p->interface == PHY_INTERFACE_MODE_RGMII_RXID)
1028*4882a593Smuzhiyun 				data8 |= PORT_RGMII_ID_IN_ENABLE;
1029*4882a593Smuzhiyun 			if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1030*4882a593Smuzhiyun 			    p->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1031*4882a593Smuzhiyun 				data8 |= PORT_RGMII_ID_OUT_ENABLE;
1032*4882a593Smuzhiyun 			data8 |= PORT_GMII_1GPS_MODE;
1033*4882a593Smuzhiyun 			data8 |= PORT_INTERFACE_RGMII;
1034*4882a593Smuzhiyun 			p->phydev.speed = SPEED_1000;
1035*4882a593Smuzhiyun 			break;
1036*4882a593Smuzhiyun 		}
1037*4882a593Smuzhiyun 		ksz_write8(dev, REG_PORT_5_CTRL_6, data8);
1038*4882a593Smuzhiyun 		p->phydev.duplex = 1;
1039*4882a593Smuzhiyun 
1040*4882a593Smuzhiyun 		member = dev->port_mask;
1041*4882a593Smuzhiyun 	} else {
1042*4882a593Smuzhiyun 		member = dev->host_mask | p->vid_member;
1043*4882a593Smuzhiyun 	}
1044*4882a593Smuzhiyun 	ksz8795_cfg_port_member(dev, port, member);
1045*4882a593Smuzhiyun }
1046*4882a593Smuzhiyun 
ksz8795_config_cpu_port(struct dsa_switch * ds)1047*4882a593Smuzhiyun static void ksz8795_config_cpu_port(struct dsa_switch *ds)
1048*4882a593Smuzhiyun {
1049*4882a593Smuzhiyun 	struct ksz_device *dev = ds->priv;
1050*4882a593Smuzhiyun 	struct ksz_port *p;
1051*4882a593Smuzhiyun 	u8 remote;
1052*4882a593Smuzhiyun 	int i;
1053*4882a593Smuzhiyun 
1054*4882a593Smuzhiyun 	ds->num_ports = dev->port_cnt + 1;
1055*4882a593Smuzhiyun 
1056*4882a593Smuzhiyun 	/* Switch marks the maximum frame with extra byte as oversize. */
1057*4882a593Smuzhiyun 	ksz_cfg(dev, REG_SW_CTRL_2, SW_LEGAL_PACKET_DISABLE, true);
1058*4882a593Smuzhiyun 	ksz_cfg(dev, S_TAIL_TAG_CTRL, SW_TAIL_TAG_ENABLE, true);
1059*4882a593Smuzhiyun 
1060*4882a593Smuzhiyun 	p = &dev->ports[dev->cpu_port];
1061*4882a593Smuzhiyun 	p->vid_member = dev->port_mask;
1062*4882a593Smuzhiyun 	p->on = 1;
1063*4882a593Smuzhiyun 
1064*4882a593Smuzhiyun 	ksz8795_port_setup(dev, dev->cpu_port, true);
1065*4882a593Smuzhiyun 	dev->member = dev->host_mask;
1066*4882a593Smuzhiyun 
1067*4882a593Smuzhiyun 	for (i = 0; i < SWITCH_PORT_NUM; i++) {
1068*4882a593Smuzhiyun 		p = &dev->ports[i];
1069*4882a593Smuzhiyun 
1070*4882a593Smuzhiyun 		/* Initialize to non-zero so that ksz_cfg_port_member() will
1071*4882a593Smuzhiyun 		 * be called.
1072*4882a593Smuzhiyun 		 */
1073*4882a593Smuzhiyun 		p->vid_member = BIT(i);
1074*4882a593Smuzhiyun 		p->member = dev->port_mask;
1075*4882a593Smuzhiyun 		ksz8795_port_stp_state_set(ds, i, BR_STATE_DISABLED);
1076*4882a593Smuzhiyun 
1077*4882a593Smuzhiyun 		/* Last port may be disabled. */
1078*4882a593Smuzhiyun 		if (i == dev->port_cnt)
1079*4882a593Smuzhiyun 			break;
1080*4882a593Smuzhiyun 		p->on = 1;
1081*4882a593Smuzhiyun 		p->phy = 1;
1082*4882a593Smuzhiyun 	}
1083*4882a593Smuzhiyun 	for (i = 0; i < dev->phy_port_cnt; i++) {
1084*4882a593Smuzhiyun 		p = &dev->ports[i];
1085*4882a593Smuzhiyun 		if (!p->on)
1086*4882a593Smuzhiyun 			continue;
1087*4882a593Smuzhiyun 		ksz_pread8(dev, i, P_REMOTE_STATUS, &remote);
1088*4882a593Smuzhiyun 		if (remote & PORT_FIBER_MODE)
1089*4882a593Smuzhiyun 			p->fiber = 1;
1090*4882a593Smuzhiyun 		if (p->fiber)
1091*4882a593Smuzhiyun 			ksz_port_cfg(dev, i, P_STP_CTRL, PORT_FORCE_FLOW_CTRL,
1092*4882a593Smuzhiyun 				     true);
1093*4882a593Smuzhiyun 		else
1094*4882a593Smuzhiyun 			ksz_port_cfg(dev, i, P_STP_CTRL, PORT_FORCE_FLOW_CTRL,
1095*4882a593Smuzhiyun 				     false);
1096*4882a593Smuzhiyun 	}
1097*4882a593Smuzhiyun }
1098*4882a593Smuzhiyun 
ksz8795_setup(struct dsa_switch * ds)1099*4882a593Smuzhiyun static int ksz8795_setup(struct dsa_switch *ds)
1100*4882a593Smuzhiyun {
1101*4882a593Smuzhiyun 	struct ksz_device *dev = ds->priv;
1102*4882a593Smuzhiyun 	struct alu_struct alu;
1103*4882a593Smuzhiyun 	int i, ret = 0;
1104*4882a593Smuzhiyun 
1105*4882a593Smuzhiyun 	dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
1106*4882a593Smuzhiyun 				       dev->num_vlans, GFP_KERNEL);
1107*4882a593Smuzhiyun 	if (!dev->vlan_cache)
1108*4882a593Smuzhiyun 		return -ENOMEM;
1109*4882a593Smuzhiyun 
1110*4882a593Smuzhiyun 	ret = ksz8795_reset_switch(dev);
1111*4882a593Smuzhiyun 	if (ret) {
1112*4882a593Smuzhiyun 		dev_err(ds->dev, "failed to reset switch\n");
1113*4882a593Smuzhiyun 		return ret;
1114*4882a593Smuzhiyun 	}
1115*4882a593Smuzhiyun 
1116*4882a593Smuzhiyun 	ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_FLOW_CTRL, true);
1117*4882a593Smuzhiyun 
1118*4882a593Smuzhiyun 	/* Enable automatic fast aging when link changed detected. */
1119*4882a593Smuzhiyun 	ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true);
1120*4882a593Smuzhiyun 
1121*4882a593Smuzhiyun 	/* Enable aggressive back off algorithm in half duplex mode. */
1122*4882a593Smuzhiyun 	regmap_update_bits(dev->regmap[0], REG_SW_CTRL_1,
1123*4882a593Smuzhiyun 			   SW_AGGR_BACKOFF, SW_AGGR_BACKOFF);
1124*4882a593Smuzhiyun 
1125*4882a593Smuzhiyun 	/*
1126*4882a593Smuzhiyun 	 * Make sure unicast VLAN boundary is set as default and
1127*4882a593Smuzhiyun 	 * enable no excessive collision drop.
1128*4882a593Smuzhiyun 	 */
1129*4882a593Smuzhiyun 	regmap_update_bits(dev->regmap[0], REG_SW_CTRL_2,
1130*4882a593Smuzhiyun 			   UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP,
1131*4882a593Smuzhiyun 			   UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP);
1132*4882a593Smuzhiyun 
1133*4882a593Smuzhiyun 	ksz8795_config_cpu_port(ds);
1134*4882a593Smuzhiyun 
1135*4882a593Smuzhiyun 	ksz_cfg(dev, REG_SW_CTRL_2, MULTICAST_STORM_DISABLE, true);
1136*4882a593Smuzhiyun 
1137*4882a593Smuzhiyun 	ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_REPLACE_VID, false);
1138*4882a593Smuzhiyun 
1139*4882a593Smuzhiyun 	ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
1140*4882a593Smuzhiyun 
1141*4882a593Smuzhiyun 	ksz_cfg(dev, REG_SW_CTRL_19, SW_INS_TAG_ENABLE, true);
1142*4882a593Smuzhiyun 
1143*4882a593Smuzhiyun 	/* set broadcast storm protection 10% rate */
1144*4882a593Smuzhiyun 	regmap_update_bits(dev->regmap[1], S_REPLACE_VID_CTRL,
1145*4882a593Smuzhiyun 			   BROADCAST_STORM_RATE,
1146*4882a593Smuzhiyun 			   (BROADCAST_STORM_VALUE *
1147*4882a593Smuzhiyun 			   BROADCAST_STORM_PROT_RATE) / 100);
1148*4882a593Smuzhiyun 
1149*4882a593Smuzhiyun 	for (i = 0; i < VLAN_TABLE_ENTRIES; i++)
1150*4882a593Smuzhiyun 		ksz8795_r_vlan_entries(dev, i);
1151*4882a593Smuzhiyun 
1152*4882a593Smuzhiyun 	/* Setup STP address for STP operation. */
1153*4882a593Smuzhiyun 	memset(&alu, 0, sizeof(alu));
1154*4882a593Smuzhiyun 	ether_addr_copy(alu.mac, eth_stp_addr);
1155*4882a593Smuzhiyun 	alu.is_static = true;
1156*4882a593Smuzhiyun 	alu.is_override = true;
1157*4882a593Smuzhiyun 	alu.port_forward = dev->host_mask;
1158*4882a593Smuzhiyun 
1159*4882a593Smuzhiyun 	ksz8795_w_sta_mac_table(dev, 0, &alu);
1160*4882a593Smuzhiyun 
1161*4882a593Smuzhiyun 	ksz_init_mib_timer(dev);
1162*4882a593Smuzhiyun 
1163*4882a593Smuzhiyun 	return 0;
1164*4882a593Smuzhiyun }
1165*4882a593Smuzhiyun 
1166*4882a593Smuzhiyun static const struct dsa_switch_ops ksz8795_switch_ops = {
1167*4882a593Smuzhiyun 	.get_tag_protocol	= ksz8795_get_tag_protocol,
1168*4882a593Smuzhiyun 	.setup			= ksz8795_setup,
1169*4882a593Smuzhiyun 	.phy_read		= ksz_phy_read16,
1170*4882a593Smuzhiyun 	.phy_write		= ksz_phy_write16,
1171*4882a593Smuzhiyun 	.phylink_mac_link_down	= ksz_mac_link_down,
1172*4882a593Smuzhiyun 	.port_enable		= ksz_enable_port,
1173*4882a593Smuzhiyun 	.get_strings		= ksz8795_get_strings,
1174*4882a593Smuzhiyun 	.get_ethtool_stats	= ksz_get_ethtool_stats,
1175*4882a593Smuzhiyun 	.get_sset_count		= ksz_sset_count,
1176*4882a593Smuzhiyun 	.port_bridge_join	= ksz_port_bridge_join,
1177*4882a593Smuzhiyun 	.port_bridge_leave	= ksz_port_bridge_leave,
1178*4882a593Smuzhiyun 	.port_stp_state_set	= ksz8795_port_stp_state_set,
1179*4882a593Smuzhiyun 	.port_fast_age		= ksz_port_fast_age,
1180*4882a593Smuzhiyun 	.port_vlan_filtering	= ksz8795_port_vlan_filtering,
1181*4882a593Smuzhiyun 	.port_vlan_prepare	= ksz8795_port_vlan_prepare,
1182*4882a593Smuzhiyun 	.port_vlan_add		= ksz8795_port_vlan_add,
1183*4882a593Smuzhiyun 	.port_vlan_del		= ksz8795_port_vlan_del,
1184*4882a593Smuzhiyun 	.port_fdb_dump		= ksz_port_fdb_dump,
1185*4882a593Smuzhiyun 	.port_mdb_prepare       = ksz_port_mdb_prepare,
1186*4882a593Smuzhiyun 	.port_mdb_add           = ksz_port_mdb_add,
1187*4882a593Smuzhiyun 	.port_mdb_del           = ksz_port_mdb_del,
1188*4882a593Smuzhiyun 	.port_mirror_add	= ksz8795_port_mirror_add,
1189*4882a593Smuzhiyun 	.port_mirror_del	= ksz8795_port_mirror_del,
1190*4882a593Smuzhiyun };
1191*4882a593Smuzhiyun 
ksz8795_get_port_addr(int port,int offset)1192*4882a593Smuzhiyun static u32 ksz8795_get_port_addr(int port, int offset)
1193*4882a593Smuzhiyun {
1194*4882a593Smuzhiyun 	return PORT_CTRL_ADDR(port, offset);
1195*4882a593Smuzhiyun }
1196*4882a593Smuzhiyun 
ksz8795_switch_detect(struct ksz_device * dev)1197*4882a593Smuzhiyun static int ksz8795_switch_detect(struct ksz_device *dev)
1198*4882a593Smuzhiyun {
1199*4882a593Smuzhiyun 	u8 id1, id2;
1200*4882a593Smuzhiyun 	u16 id16;
1201*4882a593Smuzhiyun 	int ret;
1202*4882a593Smuzhiyun 
1203*4882a593Smuzhiyun 	/* read chip id */
1204*4882a593Smuzhiyun 	ret = ksz_read16(dev, REG_CHIP_ID0, &id16);
1205*4882a593Smuzhiyun 	if (ret)
1206*4882a593Smuzhiyun 		return ret;
1207*4882a593Smuzhiyun 
1208*4882a593Smuzhiyun 	id1 = id16 >> 8;
1209*4882a593Smuzhiyun 	id2 = id16 & SW_CHIP_ID_M;
1210*4882a593Smuzhiyun 	if (id1 != FAMILY_ID ||
1211*4882a593Smuzhiyun 	    (id2 != CHIP_ID_94 && id2 != CHIP_ID_95))
1212*4882a593Smuzhiyun 		return -ENODEV;
1213*4882a593Smuzhiyun 
1214*4882a593Smuzhiyun 	dev->mib_port_cnt = TOTAL_PORT_NUM;
1215*4882a593Smuzhiyun 	dev->phy_port_cnt = SWITCH_PORT_NUM;
1216*4882a593Smuzhiyun 	dev->port_cnt = SWITCH_PORT_NUM;
1217*4882a593Smuzhiyun 
1218*4882a593Smuzhiyun 	if (id2 == CHIP_ID_95) {
1219*4882a593Smuzhiyun 		u8 val;
1220*4882a593Smuzhiyun 
1221*4882a593Smuzhiyun 		id2 = 0x95;
1222*4882a593Smuzhiyun 		ksz_read8(dev, REG_PORT_1_STATUS_0, &val);
1223*4882a593Smuzhiyun 		if (val & PORT_FIBER_MODE)
1224*4882a593Smuzhiyun 			id2 = 0x65;
1225*4882a593Smuzhiyun 	} else if (id2 == CHIP_ID_94) {
1226*4882a593Smuzhiyun 		dev->port_cnt--;
1227*4882a593Smuzhiyun 		dev->last_port = dev->port_cnt;
1228*4882a593Smuzhiyun 		id2 = 0x94;
1229*4882a593Smuzhiyun 	}
1230*4882a593Smuzhiyun 	id16 &= ~0xff;
1231*4882a593Smuzhiyun 	id16 |= id2;
1232*4882a593Smuzhiyun 	dev->chip_id = id16;
1233*4882a593Smuzhiyun 
1234*4882a593Smuzhiyun 	dev->cpu_port = dev->mib_port_cnt - 1;
1235*4882a593Smuzhiyun 	dev->host_mask = BIT(dev->cpu_port);
1236*4882a593Smuzhiyun 
1237*4882a593Smuzhiyun 	return 0;
1238*4882a593Smuzhiyun }
1239*4882a593Smuzhiyun 
1240*4882a593Smuzhiyun struct ksz_chip_data {
1241*4882a593Smuzhiyun 	u16 chip_id;
1242*4882a593Smuzhiyun 	const char *dev_name;
1243*4882a593Smuzhiyun 	int num_vlans;
1244*4882a593Smuzhiyun 	int num_alus;
1245*4882a593Smuzhiyun 	int num_statics;
1246*4882a593Smuzhiyun 	int cpu_ports;
1247*4882a593Smuzhiyun 	int port_cnt;
1248*4882a593Smuzhiyun };
1249*4882a593Smuzhiyun 
1250*4882a593Smuzhiyun static const struct ksz_chip_data ksz8795_switch_chips[] = {
1251*4882a593Smuzhiyun 	{
1252*4882a593Smuzhiyun 		.chip_id = 0x8795,
1253*4882a593Smuzhiyun 		.dev_name = "KSZ8795",
1254*4882a593Smuzhiyun 		.num_vlans = 4096,
1255*4882a593Smuzhiyun 		.num_alus = 0,
1256*4882a593Smuzhiyun 		.num_statics = 8,
1257*4882a593Smuzhiyun 		.cpu_ports = 0x10,	/* can be configured as cpu port */
1258*4882a593Smuzhiyun 		.port_cnt = 4,		/* total physical port count */
1259*4882a593Smuzhiyun 	},
1260*4882a593Smuzhiyun 	{
1261*4882a593Smuzhiyun 		.chip_id = 0x8794,
1262*4882a593Smuzhiyun 		.dev_name = "KSZ8794",
1263*4882a593Smuzhiyun 		.num_vlans = 4096,
1264*4882a593Smuzhiyun 		.num_alus = 0,
1265*4882a593Smuzhiyun 		.num_statics = 8,
1266*4882a593Smuzhiyun 		.cpu_ports = 0x10,	/* can be configured as cpu port */
1267*4882a593Smuzhiyun 		.port_cnt = 3,		/* total physical port count */
1268*4882a593Smuzhiyun 	},
1269*4882a593Smuzhiyun 	{
1270*4882a593Smuzhiyun 		.chip_id = 0x8765,
1271*4882a593Smuzhiyun 		.dev_name = "KSZ8765",
1272*4882a593Smuzhiyun 		.num_vlans = 4096,
1273*4882a593Smuzhiyun 		.num_alus = 0,
1274*4882a593Smuzhiyun 		.num_statics = 8,
1275*4882a593Smuzhiyun 		.cpu_ports = 0x10,	/* can be configured as cpu port */
1276*4882a593Smuzhiyun 		.port_cnt = 4,		/* total physical port count */
1277*4882a593Smuzhiyun 	},
1278*4882a593Smuzhiyun };
1279*4882a593Smuzhiyun 
ksz8795_switch_init(struct ksz_device * dev)1280*4882a593Smuzhiyun static int ksz8795_switch_init(struct ksz_device *dev)
1281*4882a593Smuzhiyun {
1282*4882a593Smuzhiyun 	int i;
1283*4882a593Smuzhiyun 
1284*4882a593Smuzhiyun 	dev->ds->ops = &ksz8795_switch_ops;
1285*4882a593Smuzhiyun 
1286*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(ksz8795_switch_chips); i++) {
1287*4882a593Smuzhiyun 		const struct ksz_chip_data *chip = &ksz8795_switch_chips[i];
1288*4882a593Smuzhiyun 
1289*4882a593Smuzhiyun 		if (dev->chip_id == chip->chip_id) {
1290*4882a593Smuzhiyun 			dev->name = chip->dev_name;
1291*4882a593Smuzhiyun 			dev->num_vlans = chip->num_vlans;
1292*4882a593Smuzhiyun 			dev->num_alus = chip->num_alus;
1293*4882a593Smuzhiyun 			dev->num_statics = chip->num_statics;
1294*4882a593Smuzhiyun 			dev->port_cnt = chip->port_cnt;
1295*4882a593Smuzhiyun 			dev->cpu_ports = chip->cpu_ports;
1296*4882a593Smuzhiyun 
1297*4882a593Smuzhiyun 			break;
1298*4882a593Smuzhiyun 		}
1299*4882a593Smuzhiyun 	}
1300*4882a593Smuzhiyun 
1301*4882a593Smuzhiyun 	/* no switch found */
1302*4882a593Smuzhiyun 	if (!dev->cpu_ports)
1303*4882a593Smuzhiyun 		return -ENODEV;
1304*4882a593Smuzhiyun 
1305*4882a593Smuzhiyun 	dev->port_mask = BIT(dev->port_cnt) - 1;
1306*4882a593Smuzhiyun 	dev->port_mask |= dev->host_mask;
1307*4882a593Smuzhiyun 
1308*4882a593Smuzhiyun 	dev->reg_mib_cnt = SWITCH_COUNTER_NUM;
1309*4882a593Smuzhiyun 	dev->mib_cnt = TOTAL_SWITCH_COUNTER_NUM;
1310*4882a593Smuzhiyun 
1311*4882a593Smuzhiyun 	i = dev->mib_port_cnt;
1312*4882a593Smuzhiyun 	dev->ports = devm_kzalloc(dev->dev, sizeof(struct ksz_port) * i,
1313*4882a593Smuzhiyun 				  GFP_KERNEL);
1314*4882a593Smuzhiyun 	if (!dev->ports)
1315*4882a593Smuzhiyun 		return -ENOMEM;
1316*4882a593Smuzhiyun 	for (i = 0; i < dev->mib_port_cnt; i++) {
1317*4882a593Smuzhiyun 		mutex_init(&dev->ports[i].mib.cnt_mutex);
1318*4882a593Smuzhiyun 		dev->ports[i].mib.counters =
1319*4882a593Smuzhiyun 			devm_kzalloc(dev->dev,
1320*4882a593Smuzhiyun 				     sizeof(u64) *
1321*4882a593Smuzhiyun 				     (TOTAL_SWITCH_COUNTER_NUM + 1),
1322*4882a593Smuzhiyun 				     GFP_KERNEL);
1323*4882a593Smuzhiyun 		if (!dev->ports[i].mib.counters)
1324*4882a593Smuzhiyun 			return -ENOMEM;
1325*4882a593Smuzhiyun 	}
1326*4882a593Smuzhiyun 
1327*4882a593Smuzhiyun 	/* set the real number of ports */
1328*4882a593Smuzhiyun 	dev->ds->num_ports = dev->port_cnt + 1;
1329*4882a593Smuzhiyun 
1330*4882a593Smuzhiyun 	/* We rely on software untagging on the CPU port, so that we
1331*4882a593Smuzhiyun 	 * can support both tagged and untagged VLANs
1332*4882a593Smuzhiyun 	 */
1333*4882a593Smuzhiyun 	dev->ds->untag_bridge_pvid = true;
1334*4882a593Smuzhiyun 
1335*4882a593Smuzhiyun 	/* VLAN filtering is partly controlled by the global VLAN
1336*4882a593Smuzhiyun 	 * Enable flag
1337*4882a593Smuzhiyun 	 */
1338*4882a593Smuzhiyun 	dev->ds->vlan_filtering_is_global = true;
1339*4882a593Smuzhiyun 
1340*4882a593Smuzhiyun 	return 0;
1341*4882a593Smuzhiyun }
1342*4882a593Smuzhiyun 
ksz8795_switch_exit(struct ksz_device * dev)1343*4882a593Smuzhiyun static void ksz8795_switch_exit(struct ksz_device *dev)
1344*4882a593Smuzhiyun {
1345*4882a593Smuzhiyun 	ksz8795_reset_switch(dev);
1346*4882a593Smuzhiyun }
1347*4882a593Smuzhiyun 
1348*4882a593Smuzhiyun static const struct ksz_dev_ops ksz8795_dev_ops = {
1349*4882a593Smuzhiyun 	.get_port_addr = ksz8795_get_port_addr,
1350*4882a593Smuzhiyun 	.cfg_port_member = ksz8795_cfg_port_member,
1351*4882a593Smuzhiyun 	.flush_dyn_mac_table = ksz8795_flush_dyn_mac_table,
1352*4882a593Smuzhiyun 	.port_setup = ksz8795_port_setup,
1353*4882a593Smuzhiyun 	.r_phy = ksz8795_r_phy,
1354*4882a593Smuzhiyun 	.w_phy = ksz8795_w_phy,
1355*4882a593Smuzhiyun 	.r_dyn_mac_table = ksz8795_r_dyn_mac_table,
1356*4882a593Smuzhiyun 	.r_sta_mac_table = ksz8795_r_sta_mac_table,
1357*4882a593Smuzhiyun 	.w_sta_mac_table = ksz8795_w_sta_mac_table,
1358*4882a593Smuzhiyun 	.r_mib_cnt = ksz8795_r_mib_cnt,
1359*4882a593Smuzhiyun 	.r_mib_pkt = ksz8795_r_mib_pkt,
1360*4882a593Smuzhiyun 	.freeze_mib = ksz8795_freeze_mib,
1361*4882a593Smuzhiyun 	.port_init_cnt = ksz8795_port_init_cnt,
1362*4882a593Smuzhiyun 	.shutdown = ksz8795_reset_switch,
1363*4882a593Smuzhiyun 	.detect = ksz8795_switch_detect,
1364*4882a593Smuzhiyun 	.init = ksz8795_switch_init,
1365*4882a593Smuzhiyun 	.exit = ksz8795_switch_exit,
1366*4882a593Smuzhiyun };
1367*4882a593Smuzhiyun 
ksz8795_switch_register(struct ksz_device * dev)1368*4882a593Smuzhiyun int ksz8795_switch_register(struct ksz_device *dev)
1369*4882a593Smuzhiyun {
1370*4882a593Smuzhiyun 	return ksz_switch_register(dev, &ksz8795_dev_ops);
1371*4882a593Smuzhiyun }
1372*4882a593Smuzhiyun EXPORT_SYMBOL(ksz8795_switch_register);
1373*4882a593Smuzhiyun 
1374*4882a593Smuzhiyun MODULE_AUTHOR("Tristram Ha <Tristram.Ha@microchip.com>");
1375*4882a593Smuzhiyun MODULE_DESCRIPTION("Microchip KSZ8795 Series Switch DSA Driver");
1376*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1377