1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Northstar Plus switch SerDes/SGMII PHY definitions
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2018 Florian Fainelli <f.fainelli@gmail.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/phy.h>
9*4882a593Smuzhiyun #include <linux/types.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun /* Non-standard page used to access SerDes PHY registers on NorthStar Plus */
12*4882a593Smuzhiyun #define B53_SERDES_PAGE 0x16
13*4882a593Smuzhiyun #define B53_SERDES_BLKADDR 0x3e
14*4882a593Smuzhiyun #define B53_SERDES_LANE 0x3c
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define B53_SERDES_ID0 0x20
17*4882a593Smuzhiyun #define SERDES_ID0_MODEL_MASK 0x3f
18*4882a593Smuzhiyun #define SERDES_ID0_REV_NUM_SHIFT 11
19*4882a593Smuzhiyun #define SERDES_ID0_REV_NUM_MASK 0x7
20*4882a593Smuzhiyun #define SERDES_ID0_REV_LETTER_SHIFT 14
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define B53_SERDES_MII_REG(x) (0x20 + (x) * 2)
23*4882a593Smuzhiyun #define B53_SERDES_DIGITAL_CONTROL(x) (0x1e + (x) * 2)
24*4882a593Smuzhiyun #define B53_SERDES_DIGITAL_STATUS 0x28
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* SERDES_DIGITAL_CONTROL1 */
27*4882a593Smuzhiyun #define FIBER_MODE_1000X BIT(0)
28*4882a593Smuzhiyun #define TBI_INTERFACE BIT(1)
29*4882a593Smuzhiyun #define SIGNAL_DETECT_EN BIT(2)
30*4882a593Smuzhiyun #define INVERT_SIGNAL_DETECT BIT(3)
31*4882a593Smuzhiyun #define AUTODET_EN BIT(4)
32*4882a593Smuzhiyun #define SGMII_MASTER_MODE BIT(5)
33*4882a593Smuzhiyun #define DISABLE_DLL_PWRDOWN BIT(6)
34*4882a593Smuzhiyun #define CRC_CHECKER_DIS BIT(7)
35*4882a593Smuzhiyun #define COMMA_DET_EN BIT(8)
36*4882a593Smuzhiyun #define ZERO_COMMA_DET_EN BIT(9)
37*4882a593Smuzhiyun #define REMOTE_LOOPBACK BIT(10)
38*4882a593Smuzhiyun #define SEL_RX_PKTS_FOR_CNTR BIT(11)
39*4882a593Smuzhiyun #define MASTER_MDIO_PHY_SEL BIT(13)
40*4882a593Smuzhiyun #define DISABLE_SIGNAL_DETECT_FLT BIT(14)
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /* SERDES_DIGITAL_CONTROL2 */
43*4882a593Smuzhiyun #define EN_PARALLEL_DET BIT(0)
44*4882a593Smuzhiyun #define DIS_FALSE_LINK BIT(1)
45*4882a593Smuzhiyun #define FLT_FORCE_LINK BIT(2)
46*4882a593Smuzhiyun #define EN_AUTONEG_ERR_TIMER BIT(3)
47*4882a593Smuzhiyun #define DIS_REMOTE_FAULT_SENSING BIT(4)
48*4882a593Smuzhiyun #define FORCE_XMIT_DATA BIT(5)
49*4882a593Smuzhiyun #define AUTONEG_FAST_TIMERS BIT(6)
50*4882a593Smuzhiyun #define DIS_CARRIER_EXTEND BIT(7)
51*4882a593Smuzhiyun #define DIS_TRRR_GENERATION BIT(8)
52*4882a593Smuzhiyun #define BYPASS_PCS_RX BIT(9)
53*4882a593Smuzhiyun #define BYPASS_PCS_TX BIT(10)
54*4882a593Smuzhiyun #define TEST_CNTR_EN BIT(11)
55*4882a593Smuzhiyun #define TX_PACKET_SEQ_TEST BIT(12)
56*4882a593Smuzhiyun #define TX_IDLE_JAM_SEQ_TEST BIT(13)
57*4882a593Smuzhiyun #define CLR_BER_CNTR BIT(14)
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* SERDES_DIGITAL_CONTROL3 */
60*4882a593Smuzhiyun #define TX_FIFO_RST BIT(0)
61*4882a593Smuzhiyun #define FIFO_ELAST_TX_RX_SHIFT 1
62*4882a593Smuzhiyun #define FIFO_ELAST_TX_RX_5K 0
63*4882a593Smuzhiyun #define FIFO_ELAST_TX_RX_10K 1
64*4882a593Smuzhiyun #define FIFO_ELAST_TX_RX_13_5K 2
65*4882a593Smuzhiyun #define FIFO_ELAST_TX_RX_18_5K 3
66*4882a593Smuzhiyun #define BLOCK_TXEN_MODE BIT(9)
67*4882a593Smuzhiyun #define JAM_FALSE_CARRIER_MODE BIT(10)
68*4882a593Smuzhiyun #define EXT_PHY_CRS_MODE BIT(11)
69*4882a593Smuzhiyun #define INVERT_EXT_PHY_CRS BIT(12)
70*4882a593Smuzhiyun #define DISABLE_TX_CRS BIT(13)
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* SERDES_DIGITAL_STATUS */
73*4882a593Smuzhiyun #define SGMII_MODE BIT(0)
74*4882a593Smuzhiyun #define LINK_STATUS BIT(1)
75*4882a593Smuzhiyun #define DUPLEX_STATUS BIT(2)
76*4882a593Smuzhiyun #define SPEED_STATUS_SHIFT 3
77*4882a593Smuzhiyun #define SPEED_STATUS_10 0
78*4882a593Smuzhiyun #define SPEED_STATUS_100 1
79*4882a593Smuzhiyun #define SPEED_STATUS_1000 2
80*4882a593Smuzhiyun #define SPEED_STATUS_2500 3
81*4882a593Smuzhiyun #define SPEED_STATUS_MASK SPEED_STATUS_2500
82*4882a593Smuzhiyun #define PAUSE_RESOLUTION_TX_SIDE BIT(5)
83*4882a593Smuzhiyun #define PAUSE_RESOLUTION_RX_SIDE BIT(6)
84*4882a593Smuzhiyun #define LINK_STATUS_CHANGE BIT(7)
85*4882a593Smuzhiyun #define EARLY_END_EXT_DET BIT(8)
86*4882a593Smuzhiyun #define CARRIER_EXT_ERR_DET BIT(9)
87*4882a593Smuzhiyun #define RX_ERR_DET BIT(10)
88*4882a593Smuzhiyun #define TX_ERR_DET BIT(11)
89*4882a593Smuzhiyun #define CRC_ERR_DET BIT(12)
90*4882a593Smuzhiyun #define FALSE_CARRIER_ERR_DET BIT(13)
91*4882a593Smuzhiyun #define RXFIFO_ERR_DET BIT(14)
92*4882a593Smuzhiyun #define TXFIFO_ERR_DET BIT(15)
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* Block offsets */
95*4882a593Smuzhiyun #define SERDES_DIGITAL_BLK 0x8300
96*4882a593Smuzhiyun #define SERDES_ID0 0x8310
97*4882a593Smuzhiyun #define SERDES_MII_BLK 0xffe0
98*4882a593Smuzhiyun #define SERDES_XGXSBLK0_BLOCKADDRESS 0xffd0
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun struct phylink_link_state;
101*4882a593Smuzhiyun
b53_serdes_map_lane(struct b53_device * dev,int port)102*4882a593Smuzhiyun static inline u8 b53_serdes_map_lane(struct b53_device *dev, int port)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun if (!dev->ops->serdes_map_lane)
105*4882a593Smuzhiyun return B53_INVALID_LANE;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun return dev->ops->serdes_map_lane(dev, port);
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun int b53_serdes_get_link(struct b53_device *dev, int port);
111*4882a593Smuzhiyun int b53_serdes_link_state(struct b53_device *dev, int port,
112*4882a593Smuzhiyun struct phylink_link_state *state);
113*4882a593Smuzhiyun void b53_serdes_config(struct b53_device *dev, int port, unsigned int mode,
114*4882a593Smuzhiyun const struct phylink_link_state *state);
115*4882a593Smuzhiyun void b53_serdes_an_restart(struct b53_device *dev, int port);
116*4882a593Smuzhiyun void b53_serdes_link_set(struct b53_device *dev, int port, unsigned int mode,
117*4882a593Smuzhiyun phy_interface_t interface, bool link_up);
118*4882a593Smuzhiyun void b53_serdes_phylink_validate(struct b53_device *dev, int port,
119*4882a593Smuzhiyun unsigned long *supported,
120*4882a593Smuzhiyun struct phylink_link_state *state);
121*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_B53_SERDES)
122*4882a593Smuzhiyun int b53_serdes_init(struct b53_device *dev, int port);
123*4882a593Smuzhiyun #else
b53_serdes_init(struct b53_device * dev,int port)124*4882a593Smuzhiyun static inline int b53_serdes_init(struct b53_device *dev, int port)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun return -ENODEV;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun #endif
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