1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // mcp251xfd - Microchip MCP251xFD Family CAN controller driver
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (c) 2019, 2020 Pengutronix,
6*4882a593Smuzhiyun // Marc Kleine-Budde <kernel@pengutronix.de>
7*4882a593Smuzhiyun //
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include "mcp251xfd.h"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <asm/unaligned.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun static const struct regmap_config mcp251xfd_regmap_crc;
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun static int
mcp251xfd_regmap_nocrc_write(void * context,const void * data,size_t count)16*4882a593Smuzhiyun mcp251xfd_regmap_nocrc_write(void *context, const void *data, size_t count)
17*4882a593Smuzhiyun {
18*4882a593Smuzhiyun struct spi_device *spi = context;
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun return spi_write(spi, data, count);
21*4882a593Smuzhiyun }
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun static int
mcp251xfd_regmap_nocrc_gather_write(void * context,const void * reg,size_t reg_len,const void * val,size_t val_len)24*4882a593Smuzhiyun mcp251xfd_regmap_nocrc_gather_write(void *context,
25*4882a593Smuzhiyun const void *reg, size_t reg_len,
26*4882a593Smuzhiyun const void *val, size_t val_len)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun struct spi_device *spi = context;
29*4882a593Smuzhiyun struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
30*4882a593Smuzhiyun struct mcp251xfd_map_buf_nocrc *buf_tx = priv->map_buf_nocrc_tx;
31*4882a593Smuzhiyun struct spi_transfer xfer[] = {
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun .tx_buf = buf_tx,
34*4882a593Smuzhiyun .len = sizeof(buf_tx->cmd) + val_len,
35*4882a593Smuzhiyun },
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16));
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY) &&
41*4882a593Smuzhiyun reg_len != sizeof(buf_tx->cmd.cmd))
42*4882a593Smuzhiyun return -EINVAL;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun memcpy(&buf_tx->cmd, reg, sizeof(buf_tx->cmd));
45*4882a593Smuzhiyun memcpy(buf_tx->data, val, val_len);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun return spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer));
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
mcp251xfd_update_bits_read_reg(unsigned int reg)50*4882a593Smuzhiyun static inline bool mcp251xfd_update_bits_read_reg(unsigned int reg)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun switch (reg) {
53*4882a593Smuzhiyun case MCP251XFD_REG_INT:
54*4882a593Smuzhiyun case MCP251XFD_REG_TEFCON:
55*4882a593Smuzhiyun case MCP251XFD_REG_FIFOCON(MCP251XFD_RX_FIFO(0)):
56*4882a593Smuzhiyun case MCP251XFD_REG_FLTCON(0):
57*4882a593Smuzhiyun case MCP251XFD_REG_ECCSTAT:
58*4882a593Smuzhiyun case MCP251XFD_REG_CRC:
59*4882a593Smuzhiyun return false;
60*4882a593Smuzhiyun case MCP251XFD_REG_CON:
61*4882a593Smuzhiyun case MCP251XFD_REG_FIFOSTA(MCP251XFD_RX_FIFO(0)):
62*4882a593Smuzhiyun case MCP251XFD_REG_OSC:
63*4882a593Smuzhiyun case MCP251XFD_REG_ECCCON:
64*4882a593Smuzhiyun return true;
65*4882a593Smuzhiyun default:
66*4882a593Smuzhiyun WARN(1, "Status of reg 0x%04x unknown.\n", reg);
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun return true;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun static int
mcp251xfd_regmap_nocrc_update_bits(void * context,unsigned int reg,unsigned int mask,unsigned int val)73*4882a593Smuzhiyun mcp251xfd_regmap_nocrc_update_bits(void *context, unsigned int reg,
74*4882a593Smuzhiyun unsigned int mask, unsigned int val)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun struct spi_device *spi = context;
77*4882a593Smuzhiyun struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
78*4882a593Smuzhiyun struct mcp251xfd_map_buf_nocrc *buf_rx = priv->map_buf_nocrc_rx;
79*4882a593Smuzhiyun struct mcp251xfd_map_buf_nocrc *buf_tx = priv->map_buf_nocrc_tx;
80*4882a593Smuzhiyun __le32 orig_le32 = 0, mask_le32, val_le32, tmp_le32;
81*4882a593Smuzhiyun u8 first_byte, last_byte, len;
82*4882a593Smuzhiyun int err;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(buf_rx->cmd) != sizeof(__be16));
85*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16));
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY) &&
88*4882a593Smuzhiyun mask == 0)
89*4882a593Smuzhiyun return -EINVAL;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun first_byte = mcp251xfd_first_byte_set(mask);
92*4882a593Smuzhiyun last_byte = mcp251xfd_last_byte_set(mask);
93*4882a593Smuzhiyun len = last_byte - first_byte + 1;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun if (mcp251xfd_update_bits_read_reg(reg)) {
96*4882a593Smuzhiyun struct spi_transfer xfer[2] = { };
97*4882a593Smuzhiyun struct spi_message msg;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun spi_message_init(&msg);
100*4882a593Smuzhiyun spi_message_add_tail(&xfer[0], &msg);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun if (priv->devtype_data.quirks & MCP251XFD_QUIRK_HALF_DUPLEX) {
103*4882a593Smuzhiyun xfer[0].tx_buf = buf_tx;
104*4882a593Smuzhiyun xfer[0].len = sizeof(buf_tx->cmd);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun xfer[1].rx_buf = buf_rx->data;
107*4882a593Smuzhiyun xfer[1].len = len;
108*4882a593Smuzhiyun spi_message_add_tail(&xfer[1], &msg);
109*4882a593Smuzhiyun } else {
110*4882a593Smuzhiyun xfer[0].tx_buf = buf_tx;
111*4882a593Smuzhiyun xfer[0].rx_buf = buf_rx;
112*4882a593Smuzhiyun xfer[0].len = sizeof(buf_tx->cmd) + len;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun if (MCP251XFD_SANITIZE_SPI)
115*4882a593Smuzhiyun memset(buf_tx->data, 0x0, len);
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun mcp251xfd_spi_cmd_read_nocrc(&buf_tx->cmd, reg + first_byte);
119*4882a593Smuzhiyun err = spi_sync(spi, &msg);
120*4882a593Smuzhiyun if (err)
121*4882a593Smuzhiyun return err;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun memcpy(&orig_le32, buf_rx->data, len);
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun mask_le32 = cpu_to_le32(mask >> BITS_PER_BYTE * first_byte);
127*4882a593Smuzhiyun val_le32 = cpu_to_le32(val >> BITS_PER_BYTE * first_byte);
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun tmp_le32 = orig_le32 & ~mask_le32;
130*4882a593Smuzhiyun tmp_le32 |= val_le32 & mask_le32;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun mcp251xfd_spi_cmd_write_nocrc(&buf_tx->cmd, reg + first_byte);
133*4882a593Smuzhiyun memcpy(buf_tx->data, &tmp_le32, len);
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun return spi_write(spi, buf_tx, sizeof(buf_tx->cmd) + len);
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun static int
mcp251xfd_regmap_nocrc_read(void * context,const void * reg,size_t reg_len,void * val_buf,size_t val_len)139*4882a593Smuzhiyun mcp251xfd_regmap_nocrc_read(void *context,
140*4882a593Smuzhiyun const void *reg, size_t reg_len,
141*4882a593Smuzhiyun void *val_buf, size_t val_len)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun struct spi_device *spi = context;
144*4882a593Smuzhiyun struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
145*4882a593Smuzhiyun struct mcp251xfd_map_buf_nocrc *buf_rx = priv->map_buf_nocrc_rx;
146*4882a593Smuzhiyun struct mcp251xfd_map_buf_nocrc *buf_tx = priv->map_buf_nocrc_tx;
147*4882a593Smuzhiyun struct spi_transfer xfer[2] = { };
148*4882a593Smuzhiyun struct spi_message msg;
149*4882a593Smuzhiyun int err;
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(buf_rx->cmd) != sizeof(__be16));
152*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16));
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY) &&
155*4882a593Smuzhiyun reg_len != sizeof(buf_tx->cmd.cmd))
156*4882a593Smuzhiyun return -EINVAL;
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun spi_message_init(&msg);
159*4882a593Smuzhiyun spi_message_add_tail(&xfer[0], &msg);
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun if (priv->devtype_data.quirks & MCP251XFD_QUIRK_HALF_DUPLEX) {
162*4882a593Smuzhiyun xfer[0].tx_buf = reg;
163*4882a593Smuzhiyun xfer[0].len = sizeof(buf_tx->cmd);
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun xfer[1].rx_buf = val_buf;
166*4882a593Smuzhiyun xfer[1].len = val_len;
167*4882a593Smuzhiyun spi_message_add_tail(&xfer[1], &msg);
168*4882a593Smuzhiyun } else {
169*4882a593Smuzhiyun xfer[0].tx_buf = buf_tx;
170*4882a593Smuzhiyun xfer[0].rx_buf = buf_rx;
171*4882a593Smuzhiyun xfer[0].len = sizeof(buf_tx->cmd) + val_len;
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun memcpy(&buf_tx->cmd, reg, sizeof(buf_tx->cmd));
174*4882a593Smuzhiyun if (MCP251XFD_SANITIZE_SPI)
175*4882a593Smuzhiyun memset(buf_tx->data, 0x0, val_len);
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun err = spi_sync(spi, &msg);
179*4882a593Smuzhiyun if (err)
180*4882a593Smuzhiyun return err;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun if (!(priv->devtype_data.quirks & MCP251XFD_QUIRK_HALF_DUPLEX))
183*4882a593Smuzhiyun memcpy(val_buf, buf_rx->data, val_len);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun return 0;
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun static int
mcp251xfd_regmap_crc_gather_write(void * context,const void * reg_p,size_t reg_len,const void * val,size_t val_len)189*4882a593Smuzhiyun mcp251xfd_regmap_crc_gather_write(void *context,
190*4882a593Smuzhiyun const void *reg_p, size_t reg_len,
191*4882a593Smuzhiyun const void *val, size_t val_len)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun struct spi_device *spi = context;
194*4882a593Smuzhiyun struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
195*4882a593Smuzhiyun struct mcp251xfd_map_buf_crc *buf_tx = priv->map_buf_crc_tx;
196*4882a593Smuzhiyun struct spi_transfer xfer[] = {
197*4882a593Smuzhiyun {
198*4882a593Smuzhiyun .tx_buf = buf_tx,
199*4882a593Smuzhiyun .len = sizeof(buf_tx->cmd) + val_len +
200*4882a593Smuzhiyun sizeof(buf_tx->crc),
201*4882a593Smuzhiyun },
202*4882a593Smuzhiyun };
203*4882a593Smuzhiyun u16 reg = *(u16 *)reg_p;
204*4882a593Smuzhiyun u16 crc;
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16) + sizeof(u8));
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY) &&
209*4882a593Smuzhiyun reg_len != sizeof(buf_tx->cmd.cmd) +
210*4882a593Smuzhiyun mcp251xfd_regmap_crc.pad_bits / BITS_PER_BYTE)
211*4882a593Smuzhiyun return -EINVAL;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun mcp251xfd_spi_cmd_write_crc(&buf_tx->cmd, reg, val_len);
214*4882a593Smuzhiyun memcpy(buf_tx->data, val, val_len);
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun crc = mcp251xfd_crc16_compute(buf_tx, sizeof(buf_tx->cmd) + val_len);
217*4882a593Smuzhiyun put_unaligned_be16(crc, buf_tx->data + val_len);
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun return spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer));
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun static int
mcp251xfd_regmap_crc_write(void * context,const void * data,size_t count)223*4882a593Smuzhiyun mcp251xfd_regmap_crc_write(void *context,
224*4882a593Smuzhiyun const void *data, size_t count)
225*4882a593Smuzhiyun {
226*4882a593Smuzhiyun const size_t data_offset = sizeof(__be16) +
227*4882a593Smuzhiyun mcp251xfd_regmap_crc.pad_bits / BITS_PER_BYTE;
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun return mcp251xfd_regmap_crc_gather_write(context,
230*4882a593Smuzhiyun data, data_offset,
231*4882a593Smuzhiyun data + data_offset,
232*4882a593Smuzhiyun count - data_offset);
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun static int
mcp251xfd_regmap_crc_read_one(struct mcp251xfd_priv * priv,struct spi_message * msg,unsigned int data_len)236*4882a593Smuzhiyun mcp251xfd_regmap_crc_read_one(struct mcp251xfd_priv *priv,
237*4882a593Smuzhiyun struct spi_message *msg, unsigned int data_len)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun const struct mcp251xfd_map_buf_crc *buf_rx = priv->map_buf_crc_rx;
240*4882a593Smuzhiyun const struct mcp251xfd_map_buf_crc *buf_tx = priv->map_buf_crc_tx;
241*4882a593Smuzhiyun u16 crc_received, crc_calculated;
242*4882a593Smuzhiyun int err;
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(buf_rx->cmd) != sizeof(__be16) + sizeof(u8));
245*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16) + sizeof(u8));
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun err = spi_sync(priv->spi, msg);
248*4882a593Smuzhiyun if (err)
249*4882a593Smuzhiyun return err;
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun crc_received = get_unaligned_be16(buf_rx->data + data_len);
252*4882a593Smuzhiyun crc_calculated = mcp251xfd_crc16_compute2(&buf_tx->cmd,
253*4882a593Smuzhiyun sizeof(buf_tx->cmd),
254*4882a593Smuzhiyun buf_rx->data,
255*4882a593Smuzhiyun data_len);
256*4882a593Smuzhiyun if (crc_received != crc_calculated)
257*4882a593Smuzhiyun return -EBADMSG;
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun return 0;
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun static int
mcp251xfd_regmap_crc_read(void * context,const void * reg_p,size_t reg_len,void * val_buf,size_t val_len)263*4882a593Smuzhiyun mcp251xfd_regmap_crc_read(void *context,
264*4882a593Smuzhiyun const void *reg_p, size_t reg_len,
265*4882a593Smuzhiyun void *val_buf, size_t val_len)
266*4882a593Smuzhiyun {
267*4882a593Smuzhiyun struct spi_device *spi = context;
268*4882a593Smuzhiyun struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
269*4882a593Smuzhiyun struct mcp251xfd_map_buf_crc *buf_rx = priv->map_buf_crc_rx;
270*4882a593Smuzhiyun struct mcp251xfd_map_buf_crc *buf_tx = priv->map_buf_crc_tx;
271*4882a593Smuzhiyun struct spi_transfer xfer[2] = { };
272*4882a593Smuzhiyun struct spi_message msg;
273*4882a593Smuzhiyun u16 reg = *(u16 *)reg_p;
274*4882a593Smuzhiyun int i, err;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(buf_rx->cmd) != sizeof(__be16) + sizeof(u8));
277*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16) + sizeof(u8));
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY) &&
280*4882a593Smuzhiyun reg_len != sizeof(buf_tx->cmd.cmd) +
281*4882a593Smuzhiyun mcp251xfd_regmap_crc.pad_bits / BITS_PER_BYTE)
282*4882a593Smuzhiyun return -EINVAL;
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun spi_message_init(&msg);
285*4882a593Smuzhiyun spi_message_add_tail(&xfer[0], &msg);
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun if (priv->devtype_data.quirks & MCP251XFD_QUIRK_HALF_DUPLEX) {
288*4882a593Smuzhiyun xfer[0].tx_buf = buf_tx;
289*4882a593Smuzhiyun xfer[0].len = sizeof(buf_tx->cmd);
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun xfer[1].rx_buf = buf_rx->data;
292*4882a593Smuzhiyun xfer[1].len = val_len + sizeof(buf_tx->crc);
293*4882a593Smuzhiyun spi_message_add_tail(&xfer[1], &msg);
294*4882a593Smuzhiyun } else {
295*4882a593Smuzhiyun xfer[0].tx_buf = buf_tx;
296*4882a593Smuzhiyun xfer[0].rx_buf = buf_rx;
297*4882a593Smuzhiyun xfer[0].len = sizeof(buf_tx->cmd) + val_len +
298*4882a593Smuzhiyun sizeof(buf_tx->crc);
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun if (MCP251XFD_SANITIZE_SPI)
301*4882a593Smuzhiyun memset(buf_tx->data, 0x0, val_len +
302*4882a593Smuzhiyun sizeof(buf_tx->crc));
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun mcp251xfd_spi_cmd_read_crc(&buf_tx->cmd, reg, val_len);
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun for (i = 0; i < MCP251XFD_READ_CRC_RETRIES_MAX; i++) {
308*4882a593Smuzhiyun err = mcp251xfd_regmap_crc_read_one(priv, &msg, val_len);
309*4882a593Smuzhiyun if (!err)
310*4882a593Smuzhiyun goto out;
311*4882a593Smuzhiyun if (err != -EBADMSG)
312*4882a593Smuzhiyun return err;
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun /* MCP251XFD_REG_OSC is the first ever reg we read from.
315*4882a593Smuzhiyun *
316*4882a593Smuzhiyun * The chip may be in deep sleep and this SPI transfer
317*4882a593Smuzhiyun * (i.e. the assertion of the CS) will wake the chip
318*4882a593Smuzhiyun * up. This takes about 3ms. The CRC of this transfer
319*4882a593Smuzhiyun * is wrong.
320*4882a593Smuzhiyun *
321*4882a593Smuzhiyun * Or there isn't a chip at all, in this case the CRC
322*4882a593Smuzhiyun * will be wrong, too.
323*4882a593Smuzhiyun *
324*4882a593Smuzhiyun * In both cases ignore the CRC and copy the read data
325*4882a593Smuzhiyun * to the caller. It will take care of both cases.
326*4882a593Smuzhiyun *
327*4882a593Smuzhiyun */
328*4882a593Smuzhiyun if (reg == MCP251XFD_REG_OSC) {
329*4882a593Smuzhiyun err = 0;
330*4882a593Smuzhiyun goto out;
331*4882a593Smuzhiyun }
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun netdev_info(priv->ndev,
334*4882a593Smuzhiyun "CRC read error at address 0x%04x (length=%zd, data=%*ph, CRC=0x%04x) retrying.\n",
335*4882a593Smuzhiyun reg, val_len, (int)val_len, buf_rx->data,
336*4882a593Smuzhiyun get_unaligned_be16(buf_rx->data + val_len));
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun if (err) {
340*4882a593Smuzhiyun netdev_err(priv->ndev,
341*4882a593Smuzhiyun "CRC read error at address 0x%04x (length=%zd, data=%*ph, CRC=0x%04x).\n",
342*4882a593Smuzhiyun reg, val_len, (int)val_len, buf_rx->data,
343*4882a593Smuzhiyun get_unaligned_be16(buf_rx->data + val_len));
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun return err;
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun out:
348*4882a593Smuzhiyun memcpy(val_buf, buf_rx->data, val_len);
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun return 0;
351*4882a593Smuzhiyun }
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun static const struct regmap_range mcp251xfd_reg_table_yes_range[] = {
354*4882a593Smuzhiyun regmap_reg_range(0x000, 0x2ec), /* CAN FD Controller Module SFR */
355*4882a593Smuzhiyun regmap_reg_range(0x400, 0xbfc), /* RAM */
356*4882a593Smuzhiyun regmap_reg_range(0xe00, 0xe14), /* MCP2517/18FD SFR */
357*4882a593Smuzhiyun };
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun static const struct regmap_access_table mcp251xfd_reg_table = {
360*4882a593Smuzhiyun .yes_ranges = mcp251xfd_reg_table_yes_range,
361*4882a593Smuzhiyun .n_yes_ranges = ARRAY_SIZE(mcp251xfd_reg_table_yes_range),
362*4882a593Smuzhiyun };
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun static const struct regmap_config mcp251xfd_regmap_nocrc = {
365*4882a593Smuzhiyun .name = "nocrc",
366*4882a593Smuzhiyun .reg_bits = 16,
367*4882a593Smuzhiyun .reg_stride = 4,
368*4882a593Smuzhiyun .pad_bits = 0,
369*4882a593Smuzhiyun .val_bits = 32,
370*4882a593Smuzhiyun .max_register = 0xffc,
371*4882a593Smuzhiyun .wr_table = &mcp251xfd_reg_table,
372*4882a593Smuzhiyun .rd_table = &mcp251xfd_reg_table,
373*4882a593Smuzhiyun .cache_type = REGCACHE_NONE,
374*4882a593Smuzhiyun .read_flag_mask = (__force unsigned long)
375*4882a593Smuzhiyun cpu_to_be16(MCP251XFD_SPI_INSTRUCTION_READ),
376*4882a593Smuzhiyun .write_flag_mask = (__force unsigned long)
377*4882a593Smuzhiyun cpu_to_be16(MCP251XFD_SPI_INSTRUCTION_WRITE),
378*4882a593Smuzhiyun };
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun static const struct regmap_bus mcp251xfd_bus_nocrc = {
381*4882a593Smuzhiyun .write = mcp251xfd_regmap_nocrc_write,
382*4882a593Smuzhiyun .gather_write = mcp251xfd_regmap_nocrc_gather_write,
383*4882a593Smuzhiyun .reg_update_bits = mcp251xfd_regmap_nocrc_update_bits,
384*4882a593Smuzhiyun .read = mcp251xfd_regmap_nocrc_read,
385*4882a593Smuzhiyun .reg_format_endian_default = REGMAP_ENDIAN_BIG,
386*4882a593Smuzhiyun .val_format_endian_default = REGMAP_ENDIAN_LITTLE,
387*4882a593Smuzhiyun .max_raw_read = sizeof_field(struct mcp251xfd_map_buf_nocrc, data),
388*4882a593Smuzhiyun .max_raw_write = sizeof_field(struct mcp251xfd_map_buf_nocrc, data),
389*4882a593Smuzhiyun };
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun static const struct regmap_config mcp251xfd_regmap_crc = {
392*4882a593Smuzhiyun .name = "crc",
393*4882a593Smuzhiyun .reg_bits = 16,
394*4882a593Smuzhiyun .reg_stride = 4,
395*4882a593Smuzhiyun .pad_bits = 16, /* keep data bits aligned */
396*4882a593Smuzhiyun .val_bits = 32,
397*4882a593Smuzhiyun .max_register = 0xffc,
398*4882a593Smuzhiyun .wr_table = &mcp251xfd_reg_table,
399*4882a593Smuzhiyun .rd_table = &mcp251xfd_reg_table,
400*4882a593Smuzhiyun .cache_type = REGCACHE_NONE,
401*4882a593Smuzhiyun };
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun static const struct regmap_bus mcp251xfd_bus_crc = {
404*4882a593Smuzhiyun .write = mcp251xfd_regmap_crc_write,
405*4882a593Smuzhiyun .gather_write = mcp251xfd_regmap_crc_gather_write,
406*4882a593Smuzhiyun .read = mcp251xfd_regmap_crc_read,
407*4882a593Smuzhiyun .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
408*4882a593Smuzhiyun .val_format_endian_default = REGMAP_ENDIAN_LITTLE,
409*4882a593Smuzhiyun .max_raw_read = sizeof_field(struct mcp251xfd_map_buf_crc, data),
410*4882a593Smuzhiyun .max_raw_write = sizeof_field(struct mcp251xfd_map_buf_crc, data),
411*4882a593Smuzhiyun };
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun static inline bool
mcp251xfd_regmap_use_nocrc(struct mcp251xfd_priv * priv)414*4882a593Smuzhiyun mcp251xfd_regmap_use_nocrc(struct mcp251xfd_priv *priv)
415*4882a593Smuzhiyun {
416*4882a593Smuzhiyun return (!(priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_REG)) ||
417*4882a593Smuzhiyun (!(priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_RX));
418*4882a593Smuzhiyun }
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun static inline bool
mcp251xfd_regmap_use_crc(struct mcp251xfd_priv * priv)421*4882a593Smuzhiyun mcp251xfd_regmap_use_crc(struct mcp251xfd_priv *priv)
422*4882a593Smuzhiyun {
423*4882a593Smuzhiyun return (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_REG) ||
424*4882a593Smuzhiyun (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_RX);
425*4882a593Smuzhiyun }
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun static int
mcp251xfd_regmap_init_nocrc(struct mcp251xfd_priv * priv)428*4882a593Smuzhiyun mcp251xfd_regmap_init_nocrc(struct mcp251xfd_priv *priv)
429*4882a593Smuzhiyun {
430*4882a593Smuzhiyun if (!priv->map_nocrc) {
431*4882a593Smuzhiyun struct regmap *map;
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun map = devm_regmap_init(&priv->spi->dev, &mcp251xfd_bus_nocrc,
434*4882a593Smuzhiyun priv->spi, &mcp251xfd_regmap_nocrc);
435*4882a593Smuzhiyun if (IS_ERR(map))
436*4882a593Smuzhiyun return PTR_ERR(map);
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun priv->map_nocrc = map;
439*4882a593Smuzhiyun }
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun if (!priv->map_buf_nocrc_rx) {
442*4882a593Smuzhiyun priv->map_buf_nocrc_rx =
443*4882a593Smuzhiyun devm_kzalloc(&priv->spi->dev,
444*4882a593Smuzhiyun sizeof(*priv->map_buf_nocrc_rx),
445*4882a593Smuzhiyun GFP_KERNEL);
446*4882a593Smuzhiyun if (!priv->map_buf_nocrc_rx)
447*4882a593Smuzhiyun return -ENOMEM;
448*4882a593Smuzhiyun }
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun if (!priv->map_buf_nocrc_tx) {
451*4882a593Smuzhiyun priv->map_buf_nocrc_tx =
452*4882a593Smuzhiyun devm_kzalloc(&priv->spi->dev,
453*4882a593Smuzhiyun sizeof(*priv->map_buf_nocrc_tx),
454*4882a593Smuzhiyun GFP_KERNEL);
455*4882a593Smuzhiyun if (!priv->map_buf_nocrc_tx)
456*4882a593Smuzhiyun return -ENOMEM;
457*4882a593Smuzhiyun }
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun if (!(priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_REG))
460*4882a593Smuzhiyun priv->map_reg = priv->map_nocrc;
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun if (!(priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_RX))
463*4882a593Smuzhiyun priv->map_rx = priv->map_nocrc;
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun return 0;
466*4882a593Smuzhiyun }
467*4882a593Smuzhiyun
mcp251xfd_regmap_destroy_nocrc(struct mcp251xfd_priv * priv)468*4882a593Smuzhiyun static void mcp251xfd_regmap_destroy_nocrc(struct mcp251xfd_priv *priv)
469*4882a593Smuzhiyun {
470*4882a593Smuzhiyun if (priv->map_buf_nocrc_rx) {
471*4882a593Smuzhiyun devm_kfree(&priv->spi->dev, priv->map_buf_nocrc_rx);
472*4882a593Smuzhiyun priv->map_buf_nocrc_rx = NULL;
473*4882a593Smuzhiyun }
474*4882a593Smuzhiyun if (priv->map_buf_nocrc_tx) {
475*4882a593Smuzhiyun devm_kfree(&priv->spi->dev, priv->map_buf_nocrc_tx);
476*4882a593Smuzhiyun priv->map_buf_nocrc_tx = NULL;
477*4882a593Smuzhiyun }
478*4882a593Smuzhiyun }
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun static int
mcp251xfd_regmap_init_crc(struct mcp251xfd_priv * priv)481*4882a593Smuzhiyun mcp251xfd_regmap_init_crc(struct mcp251xfd_priv *priv)
482*4882a593Smuzhiyun {
483*4882a593Smuzhiyun if (!priv->map_crc) {
484*4882a593Smuzhiyun struct regmap *map;
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun map = devm_regmap_init(&priv->spi->dev, &mcp251xfd_bus_crc,
487*4882a593Smuzhiyun priv->spi, &mcp251xfd_regmap_crc);
488*4882a593Smuzhiyun if (IS_ERR(map))
489*4882a593Smuzhiyun return PTR_ERR(map);
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun priv->map_crc = map;
492*4882a593Smuzhiyun }
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun if (!priv->map_buf_crc_rx) {
495*4882a593Smuzhiyun priv->map_buf_crc_rx =
496*4882a593Smuzhiyun devm_kzalloc(&priv->spi->dev,
497*4882a593Smuzhiyun sizeof(*priv->map_buf_crc_rx),
498*4882a593Smuzhiyun GFP_KERNEL);
499*4882a593Smuzhiyun if (!priv->map_buf_crc_rx)
500*4882a593Smuzhiyun return -ENOMEM;
501*4882a593Smuzhiyun }
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun if (!priv->map_buf_crc_tx) {
504*4882a593Smuzhiyun priv->map_buf_crc_tx =
505*4882a593Smuzhiyun devm_kzalloc(&priv->spi->dev,
506*4882a593Smuzhiyun sizeof(*priv->map_buf_crc_tx),
507*4882a593Smuzhiyun GFP_KERNEL);
508*4882a593Smuzhiyun if (!priv->map_buf_crc_tx)
509*4882a593Smuzhiyun return -ENOMEM;
510*4882a593Smuzhiyun }
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun if (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_REG)
513*4882a593Smuzhiyun priv->map_reg = priv->map_crc;
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun if (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_RX)
516*4882a593Smuzhiyun priv->map_rx = priv->map_crc;
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun return 0;
519*4882a593Smuzhiyun }
520*4882a593Smuzhiyun
mcp251xfd_regmap_destroy_crc(struct mcp251xfd_priv * priv)521*4882a593Smuzhiyun static void mcp251xfd_regmap_destroy_crc(struct mcp251xfd_priv *priv)
522*4882a593Smuzhiyun {
523*4882a593Smuzhiyun if (priv->map_buf_crc_rx) {
524*4882a593Smuzhiyun devm_kfree(&priv->spi->dev, priv->map_buf_crc_rx);
525*4882a593Smuzhiyun priv->map_buf_crc_rx = NULL;
526*4882a593Smuzhiyun }
527*4882a593Smuzhiyun if (priv->map_buf_crc_tx) {
528*4882a593Smuzhiyun devm_kfree(&priv->spi->dev, priv->map_buf_crc_tx);
529*4882a593Smuzhiyun priv->map_buf_crc_tx = NULL;
530*4882a593Smuzhiyun }
531*4882a593Smuzhiyun }
532*4882a593Smuzhiyun
mcp251xfd_regmap_init(struct mcp251xfd_priv * priv)533*4882a593Smuzhiyun int mcp251xfd_regmap_init(struct mcp251xfd_priv *priv)
534*4882a593Smuzhiyun {
535*4882a593Smuzhiyun int err;
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun if (mcp251xfd_regmap_use_nocrc(priv)) {
538*4882a593Smuzhiyun err = mcp251xfd_regmap_init_nocrc(priv);
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun if (err)
541*4882a593Smuzhiyun return err;
542*4882a593Smuzhiyun } else {
543*4882a593Smuzhiyun mcp251xfd_regmap_destroy_nocrc(priv);
544*4882a593Smuzhiyun }
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun if (mcp251xfd_regmap_use_crc(priv)) {
547*4882a593Smuzhiyun err = mcp251xfd_regmap_init_crc(priv);
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun if (err)
550*4882a593Smuzhiyun return err;
551*4882a593Smuzhiyun } else {
552*4882a593Smuzhiyun mcp251xfd_regmap_destroy_crc(priv);
553*4882a593Smuzhiyun }
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun return 0;
556*4882a593Smuzhiyun }
557