1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2009 Wolfgang Grandegger <wg@grandegger.com>
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/kernel.h>
7*4882a593Smuzhiyun #include <linux/module.h>
8*4882a593Smuzhiyun #include <linux/platform_device.h>
9*4882a593Smuzhiyun #include <linux/interrupt.h>
10*4882a593Smuzhiyun #include <linux/netdevice.h>
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/irq.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <linux/can/dev.h>
15*4882a593Smuzhiyun #include <linux/can/platform/sja1000.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include "sja1000.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define DRV_NAME "sja1000_isa"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define MAXDEV 8
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun MODULE_AUTHOR("Wolfgang Grandegger <wg@grandegger.com>");
24*4882a593Smuzhiyun MODULE_DESCRIPTION("Socket-CAN driver for SJA1000 on the ISA bus");
25*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define CLK_DEFAULT 16000000 /* 16 MHz */
28*4882a593Smuzhiyun #define CDR_DEFAULT (CDR_CBP | CDR_CLK_OFF)
29*4882a593Smuzhiyun #define OCR_DEFAULT OCR_TX0_PUSHPULL
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun static unsigned long port[MAXDEV];
32*4882a593Smuzhiyun static unsigned long mem[MAXDEV];
33*4882a593Smuzhiyun static int irq[MAXDEV];
34*4882a593Smuzhiyun static int clk[MAXDEV];
35*4882a593Smuzhiyun static unsigned char cdr[MAXDEV] = {[0 ... (MAXDEV - 1)] = 0xff};
36*4882a593Smuzhiyun static unsigned char ocr[MAXDEV] = {[0 ... (MAXDEV - 1)] = 0xff};
37*4882a593Smuzhiyun static int indirect[MAXDEV] = {[0 ... (MAXDEV - 1)] = -1};
38*4882a593Smuzhiyun static spinlock_t indirect_lock[MAXDEV]; /* lock for indirect access mode */
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun module_param_hw_array(port, ulong, ioport, NULL, 0444);
41*4882a593Smuzhiyun MODULE_PARM_DESC(port, "I/O port number");
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun module_param_hw_array(mem, ulong, iomem, NULL, 0444);
44*4882a593Smuzhiyun MODULE_PARM_DESC(mem, "I/O memory address");
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun module_param_hw_array(indirect, int, ioport, NULL, 0444);
47*4882a593Smuzhiyun MODULE_PARM_DESC(indirect, "Indirect access via address and data port");
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun module_param_hw_array(irq, int, irq, NULL, 0444);
50*4882a593Smuzhiyun MODULE_PARM_DESC(irq, "IRQ number");
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun module_param_array(clk, int, NULL, 0444);
53*4882a593Smuzhiyun MODULE_PARM_DESC(clk, "External oscillator clock frequency "
54*4882a593Smuzhiyun "(default=16000000 [16 MHz])");
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun module_param_array(cdr, byte, NULL, 0444);
57*4882a593Smuzhiyun MODULE_PARM_DESC(cdr, "Clock divider register "
58*4882a593Smuzhiyun "(default=0x48 [CDR_CBP | CDR_CLK_OFF])");
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun module_param_array(ocr, byte, NULL, 0444);
61*4882a593Smuzhiyun MODULE_PARM_DESC(ocr, "Output control register "
62*4882a593Smuzhiyun "(default=0x18 [OCR_TX0_PUSHPULL])");
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun #define SJA1000_IOSIZE 0x20
65*4882a593Smuzhiyun #define SJA1000_IOSIZE_INDIRECT 0x02
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun static struct platform_device *sja1000_isa_devs[MAXDEV];
68*4882a593Smuzhiyun
sja1000_isa_mem_read_reg(const struct sja1000_priv * priv,int reg)69*4882a593Smuzhiyun static u8 sja1000_isa_mem_read_reg(const struct sja1000_priv *priv, int reg)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun return readb(priv->reg_base + reg);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
sja1000_isa_mem_write_reg(const struct sja1000_priv * priv,int reg,u8 val)74*4882a593Smuzhiyun static void sja1000_isa_mem_write_reg(const struct sja1000_priv *priv,
75*4882a593Smuzhiyun int reg, u8 val)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun writeb(val, priv->reg_base + reg);
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
sja1000_isa_port_read_reg(const struct sja1000_priv * priv,int reg)80*4882a593Smuzhiyun static u8 sja1000_isa_port_read_reg(const struct sja1000_priv *priv, int reg)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun return inb((unsigned long)priv->reg_base + reg);
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
sja1000_isa_port_write_reg(const struct sja1000_priv * priv,int reg,u8 val)85*4882a593Smuzhiyun static void sja1000_isa_port_write_reg(const struct sja1000_priv *priv,
86*4882a593Smuzhiyun int reg, u8 val)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun outb(val, (unsigned long)priv->reg_base + reg);
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
sja1000_isa_port_read_reg_indirect(const struct sja1000_priv * priv,int reg)91*4882a593Smuzhiyun static u8 sja1000_isa_port_read_reg_indirect(const struct sja1000_priv *priv,
92*4882a593Smuzhiyun int reg)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun unsigned long flags, base = (unsigned long)priv->reg_base;
95*4882a593Smuzhiyun u8 readval;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun spin_lock_irqsave(&indirect_lock[priv->dev->dev_id], flags);
98*4882a593Smuzhiyun outb(reg, base);
99*4882a593Smuzhiyun readval = inb(base + 1);
100*4882a593Smuzhiyun spin_unlock_irqrestore(&indirect_lock[priv->dev->dev_id], flags);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun return readval;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
sja1000_isa_port_write_reg_indirect(const struct sja1000_priv * priv,int reg,u8 val)105*4882a593Smuzhiyun static void sja1000_isa_port_write_reg_indirect(const struct sja1000_priv *priv,
106*4882a593Smuzhiyun int reg, u8 val)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun unsigned long flags, base = (unsigned long)priv->reg_base;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun spin_lock_irqsave(&indirect_lock[priv->dev->dev_id], flags);
111*4882a593Smuzhiyun outb(reg, base);
112*4882a593Smuzhiyun outb(val, base + 1);
113*4882a593Smuzhiyun spin_unlock_irqrestore(&indirect_lock[priv->dev->dev_id], flags);
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun
sja1000_isa_probe(struct platform_device * pdev)116*4882a593Smuzhiyun static int sja1000_isa_probe(struct platform_device *pdev)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun struct net_device *dev;
119*4882a593Smuzhiyun struct sja1000_priv *priv;
120*4882a593Smuzhiyun void __iomem *base = NULL;
121*4882a593Smuzhiyun int iosize = SJA1000_IOSIZE;
122*4882a593Smuzhiyun int idx = pdev->id;
123*4882a593Smuzhiyun int err;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun dev_dbg(&pdev->dev, "probing idx=%d: port=%#lx, mem=%#lx, irq=%d\n",
126*4882a593Smuzhiyun idx, port[idx], mem[idx], irq[idx]);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun if (mem[idx]) {
129*4882a593Smuzhiyun if (!request_mem_region(mem[idx], iosize, DRV_NAME)) {
130*4882a593Smuzhiyun err = -EBUSY;
131*4882a593Smuzhiyun goto exit;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun base = ioremap(mem[idx], iosize);
134*4882a593Smuzhiyun if (!base) {
135*4882a593Smuzhiyun err = -ENOMEM;
136*4882a593Smuzhiyun goto exit_release;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun } else {
139*4882a593Smuzhiyun if (indirect[idx] > 0 ||
140*4882a593Smuzhiyun (indirect[idx] == -1 && indirect[0] > 0))
141*4882a593Smuzhiyun iosize = SJA1000_IOSIZE_INDIRECT;
142*4882a593Smuzhiyun if (!request_region(port[idx], iosize, DRV_NAME)) {
143*4882a593Smuzhiyun err = -EBUSY;
144*4882a593Smuzhiyun goto exit;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun dev = alloc_sja1000dev(0);
149*4882a593Smuzhiyun if (!dev) {
150*4882a593Smuzhiyun err = -ENOMEM;
151*4882a593Smuzhiyun goto exit_unmap;
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun priv = netdev_priv(dev);
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun dev->irq = irq[idx];
156*4882a593Smuzhiyun priv->irq_flags = IRQF_SHARED;
157*4882a593Smuzhiyun if (mem[idx]) {
158*4882a593Smuzhiyun priv->reg_base = base;
159*4882a593Smuzhiyun dev->base_addr = mem[idx];
160*4882a593Smuzhiyun priv->read_reg = sja1000_isa_mem_read_reg;
161*4882a593Smuzhiyun priv->write_reg = sja1000_isa_mem_write_reg;
162*4882a593Smuzhiyun } else {
163*4882a593Smuzhiyun priv->reg_base = (void __iomem *)port[idx];
164*4882a593Smuzhiyun dev->base_addr = port[idx];
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun if (iosize == SJA1000_IOSIZE_INDIRECT) {
167*4882a593Smuzhiyun priv->read_reg = sja1000_isa_port_read_reg_indirect;
168*4882a593Smuzhiyun priv->write_reg = sja1000_isa_port_write_reg_indirect;
169*4882a593Smuzhiyun spin_lock_init(&indirect_lock[idx]);
170*4882a593Smuzhiyun } else {
171*4882a593Smuzhiyun priv->read_reg = sja1000_isa_port_read_reg;
172*4882a593Smuzhiyun priv->write_reg = sja1000_isa_port_write_reg;
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun if (clk[idx])
177*4882a593Smuzhiyun priv->can.clock.freq = clk[idx] / 2;
178*4882a593Smuzhiyun else if (clk[0])
179*4882a593Smuzhiyun priv->can.clock.freq = clk[0] / 2;
180*4882a593Smuzhiyun else
181*4882a593Smuzhiyun priv->can.clock.freq = CLK_DEFAULT / 2;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun if (ocr[idx] != 0xff)
184*4882a593Smuzhiyun priv->ocr = ocr[idx];
185*4882a593Smuzhiyun else if (ocr[0] != 0xff)
186*4882a593Smuzhiyun priv->ocr = ocr[0];
187*4882a593Smuzhiyun else
188*4882a593Smuzhiyun priv->ocr = OCR_DEFAULT;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun if (cdr[idx] != 0xff)
191*4882a593Smuzhiyun priv->cdr = cdr[idx];
192*4882a593Smuzhiyun else if (cdr[0] != 0xff)
193*4882a593Smuzhiyun priv->cdr = cdr[0];
194*4882a593Smuzhiyun else
195*4882a593Smuzhiyun priv->cdr = CDR_DEFAULT;
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun platform_set_drvdata(pdev, dev);
198*4882a593Smuzhiyun SET_NETDEV_DEV(dev, &pdev->dev);
199*4882a593Smuzhiyun dev->dev_id = idx;
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun err = register_sja1000dev(dev);
202*4882a593Smuzhiyun if (err) {
203*4882a593Smuzhiyun dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
204*4882a593Smuzhiyun DRV_NAME, err);
205*4882a593Smuzhiyun goto exit_free;
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun dev_info(&pdev->dev, "%s device registered (reg_base=0x%p, irq=%d)\n",
209*4882a593Smuzhiyun DRV_NAME, priv->reg_base, dev->irq);
210*4882a593Smuzhiyun return 0;
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun exit_free:
213*4882a593Smuzhiyun free_sja1000dev(dev);
214*4882a593Smuzhiyun exit_unmap:
215*4882a593Smuzhiyun if (mem[idx])
216*4882a593Smuzhiyun iounmap(base);
217*4882a593Smuzhiyun exit_release:
218*4882a593Smuzhiyun if (mem[idx])
219*4882a593Smuzhiyun release_mem_region(mem[idx], iosize);
220*4882a593Smuzhiyun else
221*4882a593Smuzhiyun release_region(port[idx], iosize);
222*4882a593Smuzhiyun exit:
223*4882a593Smuzhiyun return err;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun
sja1000_isa_remove(struct platform_device * pdev)226*4882a593Smuzhiyun static int sja1000_isa_remove(struct platform_device *pdev)
227*4882a593Smuzhiyun {
228*4882a593Smuzhiyun struct net_device *dev = platform_get_drvdata(pdev);
229*4882a593Smuzhiyun struct sja1000_priv *priv = netdev_priv(dev);
230*4882a593Smuzhiyun int idx = pdev->id;
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun unregister_sja1000dev(dev);
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun if (mem[idx]) {
235*4882a593Smuzhiyun iounmap(priv->reg_base);
236*4882a593Smuzhiyun release_mem_region(mem[idx], SJA1000_IOSIZE);
237*4882a593Smuzhiyun } else {
238*4882a593Smuzhiyun if (priv->read_reg == sja1000_isa_port_read_reg_indirect)
239*4882a593Smuzhiyun release_region(port[idx], SJA1000_IOSIZE_INDIRECT);
240*4882a593Smuzhiyun else
241*4882a593Smuzhiyun release_region(port[idx], SJA1000_IOSIZE);
242*4882a593Smuzhiyun }
243*4882a593Smuzhiyun free_sja1000dev(dev);
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun return 0;
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun static struct platform_driver sja1000_isa_driver = {
249*4882a593Smuzhiyun .probe = sja1000_isa_probe,
250*4882a593Smuzhiyun .remove = sja1000_isa_remove,
251*4882a593Smuzhiyun .driver = {
252*4882a593Smuzhiyun .name = DRV_NAME,
253*4882a593Smuzhiyun },
254*4882a593Smuzhiyun };
255*4882a593Smuzhiyun
sja1000_isa_init(void)256*4882a593Smuzhiyun static int __init sja1000_isa_init(void)
257*4882a593Smuzhiyun {
258*4882a593Smuzhiyun int idx, err;
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun for (idx = 0; idx < MAXDEV; idx++) {
261*4882a593Smuzhiyun if ((port[idx] || mem[idx]) && irq[idx]) {
262*4882a593Smuzhiyun sja1000_isa_devs[idx] =
263*4882a593Smuzhiyun platform_device_alloc(DRV_NAME, idx);
264*4882a593Smuzhiyun if (!sja1000_isa_devs[idx]) {
265*4882a593Smuzhiyun err = -ENOMEM;
266*4882a593Smuzhiyun goto exit_free_devices;
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun err = platform_device_add(sja1000_isa_devs[idx]);
269*4882a593Smuzhiyun if (err) {
270*4882a593Smuzhiyun platform_device_put(sja1000_isa_devs[idx]);
271*4882a593Smuzhiyun goto exit_free_devices;
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun pr_debug("%s: platform device %d: port=%#lx, mem=%#lx, "
274*4882a593Smuzhiyun "irq=%d\n",
275*4882a593Smuzhiyun DRV_NAME, idx, port[idx], mem[idx], irq[idx]);
276*4882a593Smuzhiyun } else if (idx == 0 || port[idx] || mem[idx]) {
277*4882a593Smuzhiyun pr_err("%s: insufficient parameters supplied\n",
278*4882a593Smuzhiyun DRV_NAME);
279*4882a593Smuzhiyun err = -EINVAL;
280*4882a593Smuzhiyun goto exit_free_devices;
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun err = platform_driver_register(&sja1000_isa_driver);
285*4882a593Smuzhiyun if (err)
286*4882a593Smuzhiyun goto exit_free_devices;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun pr_info("Legacy %s driver for max. %d devices registered\n",
289*4882a593Smuzhiyun DRV_NAME, MAXDEV);
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun return 0;
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun exit_free_devices:
294*4882a593Smuzhiyun while (--idx >= 0) {
295*4882a593Smuzhiyun if (sja1000_isa_devs[idx])
296*4882a593Smuzhiyun platform_device_unregister(sja1000_isa_devs[idx]);
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun return err;
300*4882a593Smuzhiyun }
301*4882a593Smuzhiyun
sja1000_isa_exit(void)302*4882a593Smuzhiyun static void __exit sja1000_isa_exit(void)
303*4882a593Smuzhiyun {
304*4882a593Smuzhiyun int idx;
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun platform_driver_unregister(&sja1000_isa_driver);
307*4882a593Smuzhiyun for (idx = 0; idx < MAXDEV; idx++) {
308*4882a593Smuzhiyun if (sja1000_isa_devs[idx])
309*4882a593Smuzhiyun platform_device_unregister(sja1000_isa_devs[idx]);
310*4882a593Smuzhiyun }
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun module_init(sja1000_isa_init);
314*4882a593Smuzhiyun module_exit(sja1000_isa_exit);
315