1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* CAN bus driver for Bosch M_CAN controller 3*4882a593Smuzhiyun * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _CAN_M_CAN_H_ 7*4882a593Smuzhiyun #define _CAN_M_CAN_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/can/core.h> 10*4882a593Smuzhiyun #include <linux/can/led.h> 11*4882a593Smuzhiyun #include <linux/completion.h> 12*4882a593Smuzhiyun #include <linux/device.h> 13*4882a593Smuzhiyun #include <linux/dma-mapping.h> 14*4882a593Smuzhiyun #include <linux/freezer.h> 15*4882a593Smuzhiyun #include <linux/slab.h> 16*4882a593Smuzhiyun #include <linux/uaccess.h> 17*4882a593Smuzhiyun #include <linux/clk.h> 18*4882a593Smuzhiyun #include <linux/delay.h> 19*4882a593Smuzhiyun #include <linux/interrupt.h> 20*4882a593Smuzhiyun #include <linux/io.h> 21*4882a593Smuzhiyun #include <linux/kernel.h> 22*4882a593Smuzhiyun #include <linux/module.h> 23*4882a593Smuzhiyun #include <linux/netdevice.h> 24*4882a593Smuzhiyun #include <linux/of.h> 25*4882a593Smuzhiyun #include <linux/of_device.h> 26*4882a593Smuzhiyun #include <linux/pm_runtime.h> 27*4882a593Smuzhiyun #include <linux/iopoll.h> 28*4882a593Smuzhiyun #include <linux/can/dev.h> 29*4882a593Smuzhiyun #include <linux/pinctrl/consumer.h> 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* m_can lec values */ 32*4882a593Smuzhiyun enum m_can_lec_type { 33*4882a593Smuzhiyun LEC_NO_ERROR = 0, 34*4882a593Smuzhiyun LEC_STUFF_ERROR, 35*4882a593Smuzhiyun LEC_FORM_ERROR, 36*4882a593Smuzhiyun LEC_ACK_ERROR, 37*4882a593Smuzhiyun LEC_BIT1_ERROR, 38*4882a593Smuzhiyun LEC_BIT0_ERROR, 39*4882a593Smuzhiyun LEC_CRC_ERROR, 40*4882a593Smuzhiyun LEC_UNUSED, 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun enum m_can_mram_cfg { 44*4882a593Smuzhiyun MRAM_SIDF = 0, 45*4882a593Smuzhiyun MRAM_XIDF, 46*4882a593Smuzhiyun MRAM_RXF0, 47*4882a593Smuzhiyun MRAM_RXF1, 48*4882a593Smuzhiyun MRAM_RXB, 49*4882a593Smuzhiyun MRAM_TXE, 50*4882a593Smuzhiyun MRAM_TXB, 51*4882a593Smuzhiyun MRAM_CFG_NUM, 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* address offset and element number for each FIFO/Buffer in the Message RAM */ 55*4882a593Smuzhiyun struct mram_cfg { 56*4882a593Smuzhiyun u16 off; 57*4882a593Smuzhiyun u8 num; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun struct m_can_classdev; 61*4882a593Smuzhiyun struct m_can_ops { 62*4882a593Smuzhiyun /* Device specific call backs */ 63*4882a593Smuzhiyun int (*clear_interrupts)(struct m_can_classdev *cdev); 64*4882a593Smuzhiyun u32 (*read_reg)(struct m_can_classdev *cdev, int reg); 65*4882a593Smuzhiyun int (*write_reg)(struct m_can_classdev *cdev, int reg, int val); 66*4882a593Smuzhiyun u32 (*read_fifo)(struct m_can_classdev *cdev, int addr_offset); 67*4882a593Smuzhiyun int (*write_fifo)(struct m_can_classdev *cdev, int addr_offset, 68*4882a593Smuzhiyun int val); 69*4882a593Smuzhiyun int (*init)(struct m_can_classdev *cdev); 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun struct m_can_classdev { 73*4882a593Smuzhiyun struct can_priv can; 74*4882a593Smuzhiyun struct napi_struct napi; 75*4882a593Smuzhiyun struct net_device *net; 76*4882a593Smuzhiyun struct device *dev; 77*4882a593Smuzhiyun struct clk *hclk; 78*4882a593Smuzhiyun struct clk *cclk; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun struct workqueue_struct *tx_wq; 81*4882a593Smuzhiyun struct work_struct tx_work; 82*4882a593Smuzhiyun struct sk_buff *tx_skb; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun struct can_bittiming_const *bit_timing; 85*4882a593Smuzhiyun struct can_bittiming_const *data_timing; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun struct m_can_ops *ops; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun void *device_data; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun int version; 92*4882a593Smuzhiyun int freq; 93*4882a593Smuzhiyun u32 irqstatus; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun int pm_clock_support; 96*4882a593Smuzhiyun int is_peripheral; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun struct mram_cfg mcfg[MRAM_CFG_NUM]; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun struct m_can_classdev *m_can_class_allocate_dev(struct device *dev); 102*4882a593Smuzhiyun void m_can_class_free_dev(struct net_device *net); 103*4882a593Smuzhiyun int m_can_class_register(struct m_can_classdev *cdev); 104*4882a593Smuzhiyun void m_can_class_unregister(struct m_can_classdev *cdev); 105*4882a593Smuzhiyun int m_can_class_get_clocks(struct m_can_classdev *cdev); 106*4882a593Smuzhiyun void m_can_init_ram(struct m_can_classdev *priv); 107*4882a593Smuzhiyun void m_can_config_endisable(struct m_can_classdev *priv, bool enable); 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun int m_can_class_suspend(struct device *dev); 110*4882a593Smuzhiyun int m_can_class_resume(struct device *dev); 111*4882a593Smuzhiyun #endif /* _CAN_M_H_ */ 112