1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Driver for CC770 and AN82527 CAN controllers on the legacy ISA bus
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2009, 2011 Wolfgang Grandegger <wg@grandegger.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun /*
9*4882a593Smuzhiyun * Bosch CC770 and Intel AN82527 CAN controllers on the ISA or PC-104 bus.
10*4882a593Smuzhiyun * The I/O port or memory address and the IRQ number must be specified via
11*4882a593Smuzhiyun * module parameters:
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * insmod cc770_isa.ko port=0x310,0x380 irq=7,11
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * for ISA devices using I/O ports or:
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun * insmod cc770_isa.ko mem=0xd1000,0xd1000 irq=7,11
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * for memory mapped ISA devices.
20*4882a593Smuzhiyun *
21*4882a593Smuzhiyun * Indirect access via address and data port is supported as well:
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * insmod cc770_isa.ko port=0x310,0x380 indirect=1 irq=7,11
24*4882a593Smuzhiyun *
25*4882a593Smuzhiyun * Furthermore, the following mode parameter can be defined:
26*4882a593Smuzhiyun *
27*4882a593Smuzhiyun * clk: External oscillator clock frequency (default=16000000 [16 MHz])
28*4882a593Smuzhiyun * cir: CPU interface register (default=0x40 [DSC])
29*4882a593Smuzhiyun * bcr: Bus configuration register (default=0x40 [CBY])
30*4882a593Smuzhiyun * cor: Clockout register (default=0x00)
31*4882a593Smuzhiyun *
32*4882a593Smuzhiyun * Note: for clk, cir, bcr and cor, the first argument re-defines the
33*4882a593Smuzhiyun * default for all other devices, e.g.:
34*4882a593Smuzhiyun *
35*4882a593Smuzhiyun * insmod cc770_isa.ko mem=0xd1000,0xd1000 irq=7,11 clk=24000000
36*4882a593Smuzhiyun *
37*4882a593Smuzhiyun * is equivalent to
38*4882a593Smuzhiyun *
39*4882a593Smuzhiyun * insmod cc770_isa.ko mem=0xd1000,0xd1000 irq=7,11 clk=24000000,24000000
40*4882a593Smuzhiyun */
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #include <linux/kernel.h>
45*4882a593Smuzhiyun #include <linux/module.h>
46*4882a593Smuzhiyun #include <linux/platform_device.h>
47*4882a593Smuzhiyun #include <linux/interrupt.h>
48*4882a593Smuzhiyun #include <linux/netdevice.h>
49*4882a593Smuzhiyun #include <linux/delay.h>
50*4882a593Smuzhiyun #include <linux/irq.h>
51*4882a593Smuzhiyun #include <linux/io.h>
52*4882a593Smuzhiyun #include <linux/can.h>
53*4882a593Smuzhiyun #include <linux/can/dev.h>
54*4882a593Smuzhiyun #include <linux/can/platform/cc770.h>
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun #include "cc770.h"
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun #define MAXDEV 8
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun MODULE_AUTHOR("Wolfgang Grandegger <wg@grandegger.com>");
61*4882a593Smuzhiyun MODULE_DESCRIPTION("Socket-CAN driver for CC770 on the ISA bus");
62*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun #define CLK_DEFAULT 16000000 /* 16 MHz */
65*4882a593Smuzhiyun #define COR_DEFAULT 0x00
66*4882a593Smuzhiyun #define BCR_DEFAULT BUSCFG_CBY
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun static unsigned long port[MAXDEV];
69*4882a593Smuzhiyun static unsigned long mem[MAXDEV];
70*4882a593Smuzhiyun static int irq[MAXDEV];
71*4882a593Smuzhiyun static int clk[MAXDEV];
72*4882a593Smuzhiyun static u8 cir[MAXDEV] = {[0 ... (MAXDEV - 1)] = 0xff};
73*4882a593Smuzhiyun static u8 cor[MAXDEV] = {[0 ... (MAXDEV - 1)] = 0xff};
74*4882a593Smuzhiyun static u8 bcr[MAXDEV] = {[0 ... (MAXDEV - 1)] = 0xff};
75*4882a593Smuzhiyun static int indirect[MAXDEV] = {[0 ... (MAXDEV - 1)] = -1};
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun module_param_hw_array(port, ulong, ioport, NULL, 0444);
78*4882a593Smuzhiyun MODULE_PARM_DESC(port, "I/O port number");
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun module_param_hw_array(mem, ulong, iomem, NULL, 0444);
81*4882a593Smuzhiyun MODULE_PARM_DESC(mem, "I/O memory address");
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun module_param_hw_array(indirect, int, ioport, NULL, 0444);
84*4882a593Smuzhiyun MODULE_PARM_DESC(indirect, "Indirect access via address and data port");
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun module_param_hw_array(irq, int, irq, NULL, 0444);
87*4882a593Smuzhiyun MODULE_PARM_DESC(irq, "IRQ number");
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun module_param_array(clk, int, NULL, 0444);
90*4882a593Smuzhiyun MODULE_PARM_DESC(clk, "External oscillator clock frequency "
91*4882a593Smuzhiyun "(default=16000000 [16 MHz])");
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun module_param_array(cir, byte, NULL, 0444);
94*4882a593Smuzhiyun MODULE_PARM_DESC(cir, "CPU interface register (default=0x40 [DSC])");
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun module_param_array(cor, byte, NULL, 0444);
97*4882a593Smuzhiyun MODULE_PARM_DESC(cor, "Clockout register (default=0x00)");
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun module_param_array(bcr, byte, NULL, 0444);
100*4882a593Smuzhiyun MODULE_PARM_DESC(bcr, "Bus configuration register (default=0x40 [CBY])");
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun #define CC770_IOSIZE 0x20
103*4882a593Smuzhiyun #define CC770_IOSIZE_INDIRECT 0x02
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /* Spinlock for cc770_isa_port_write_reg_indirect
106*4882a593Smuzhiyun * and cc770_isa_port_read_reg_indirect
107*4882a593Smuzhiyun */
108*4882a593Smuzhiyun static DEFINE_SPINLOCK(cc770_isa_port_lock);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun static struct platform_device *cc770_isa_devs[MAXDEV];
111*4882a593Smuzhiyun
cc770_isa_mem_read_reg(const struct cc770_priv * priv,int reg)112*4882a593Smuzhiyun static u8 cc770_isa_mem_read_reg(const struct cc770_priv *priv, int reg)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun return readb(priv->reg_base + reg);
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
cc770_isa_mem_write_reg(const struct cc770_priv * priv,int reg,u8 val)117*4882a593Smuzhiyun static void cc770_isa_mem_write_reg(const struct cc770_priv *priv,
118*4882a593Smuzhiyun int reg, u8 val)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun writeb(val, priv->reg_base + reg);
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
cc770_isa_port_read_reg(const struct cc770_priv * priv,int reg)123*4882a593Smuzhiyun static u8 cc770_isa_port_read_reg(const struct cc770_priv *priv, int reg)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun return inb((unsigned long)priv->reg_base + reg);
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
cc770_isa_port_write_reg(const struct cc770_priv * priv,int reg,u8 val)128*4882a593Smuzhiyun static void cc770_isa_port_write_reg(const struct cc770_priv *priv,
129*4882a593Smuzhiyun int reg, u8 val)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun outb(val, (unsigned long)priv->reg_base + reg);
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
cc770_isa_port_read_reg_indirect(const struct cc770_priv * priv,int reg)134*4882a593Smuzhiyun static u8 cc770_isa_port_read_reg_indirect(const struct cc770_priv *priv,
135*4882a593Smuzhiyun int reg)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun unsigned long base = (unsigned long)priv->reg_base;
138*4882a593Smuzhiyun unsigned long flags;
139*4882a593Smuzhiyun u8 val;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun spin_lock_irqsave(&cc770_isa_port_lock, flags);
142*4882a593Smuzhiyun outb(reg, base);
143*4882a593Smuzhiyun val = inb(base + 1);
144*4882a593Smuzhiyun spin_unlock_irqrestore(&cc770_isa_port_lock, flags);
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun return val;
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun
cc770_isa_port_write_reg_indirect(const struct cc770_priv * priv,int reg,u8 val)149*4882a593Smuzhiyun static void cc770_isa_port_write_reg_indirect(const struct cc770_priv *priv,
150*4882a593Smuzhiyun int reg, u8 val)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun unsigned long base = (unsigned long)priv->reg_base;
153*4882a593Smuzhiyun unsigned long flags;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun spin_lock_irqsave(&cc770_isa_port_lock, flags);
156*4882a593Smuzhiyun outb(reg, base);
157*4882a593Smuzhiyun outb(val, base + 1);
158*4882a593Smuzhiyun spin_unlock_irqrestore(&cc770_isa_port_lock, flags);
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun
cc770_isa_probe(struct platform_device * pdev)161*4882a593Smuzhiyun static int cc770_isa_probe(struct platform_device *pdev)
162*4882a593Smuzhiyun {
163*4882a593Smuzhiyun struct net_device *dev;
164*4882a593Smuzhiyun struct cc770_priv *priv;
165*4882a593Smuzhiyun void __iomem *base = NULL;
166*4882a593Smuzhiyun int iosize = CC770_IOSIZE;
167*4882a593Smuzhiyun int idx = pdev->id;
168*4882a593Smuzhiyun int err;
169*4882a593Smuzhiyun u32 clktmp;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun dev_dbg(&pdev->dev, "probing idx=%d: port=%#lx, mem=%#lx, irq=%d\n",
172*4882a593Smuzhiyun idx, port[idx], mem[idx], irq[idx]);
173*4882a593Smuzhiyun if (mem[idx]) {
174*4882a593Smuzhiyun if (!request_mem_region(mem[idx], iosize, KBUILD_MODNAME)) {
175*4882a593Smuzhiyun err = -EBUSY;
176*4882a593Smuzhiyun goto exit;
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun base = ioremap(mem[idx], iosize);
179*4882a593Smuzhiyun if (!base) {
180*4882a593Smuzhiyun err = -ENOMEM;
181*4882a593Smuzhiyun goto exit_release;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun } else {
184*4882a593Smuzhiyun if (indirect[idx] > 0 ||
185*4882a593Smuzhiyun (indirect[idx] == -1 && indirect[0] > 0))
186*4882a593Smuzhiyun iosize = CC770_IOSIZE_INDIRECT;
187*4882a593Smuzhiyun if (!request_region(port[idx], iosize, KBUILD_MODNAME)) {
188*4882a593Smuzhiyun err = -EBUSY;
189*4882a593Smuzhiyun goto exit;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun dev = alloc_cc770dev(0);
194*4882a593Smuzhiyun if (!dev) {
195*4882a593Smuzhiyun err = -ENOMEM;
196*4882a593Smuzhiyun goto exit_unmap;
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun priv = netdev_priv(dev);
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun dev->irq = irq[idx];
201*4882a593Smuzhiyun priv->irq_flags = IRQF_SHARED;
202*4882a593Smuzhiyun if (mem[idx]) {
203*4882a593Smuzhiyun priv->reg_base = base;
204*4882a593Smuzhiyun dev->base_addr = mem[idx];
205*4882a593Smuzhiyun priv->read_reg = cc770_isa_mem_read_reg;
206*4882a593Smuzhiyun priv->write_reg = cc770_isa_mem_write_reg;
207*4882a593Smuzhiyun } else {
208*4882a593Smuzhiyun priv->reg_base = (void __iomem *)port[idx];
209*4882a593Smuzhiyun dev->base_addr = port[idx];
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun if (iosize == CC770_IOSIZE_INDIRECT) {
212*4882a593Smuzhiyun priv->read_reg = cc770_isa_port_read_reg_indirect;
213*4882a593Smuzhiyun priv->write_reg = cc770_isa_port_write_reg_indirect;
214*4882a593Smuzhiyun } else {
215*4882a593Smuzhiyun priv->read_reg = cc770_isa_port_read_reg;
216*4882a593Smuzhiyun priv->write_reg = cc770_isa_port_write_reg;
217*4882a593Smuzhiyun }
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun if (clk[idx])
221*4882a593Smuzhiyun clktmp = clk[idx];
222*4882a593Smuzhiyun else if (clk[0])
223*4882a593Smuzhiyun clktmp = clk[0];
224*4882a593Smuzhiyun else
225*4882a593Smuzhiyun clktmp = CLK_DEFAULT;
226*4882a593Smuzhiyun priv->can.clock.freq = clktmp;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun if (cir[idx] != 0xff) {
229*4882a593Smuzhiyun priv->cpu_interface = cir[idx];
230*4882a593Smuzhiyun } else if (cir[0] != 0xff) {
231*4882a593Smuzhiyun priv->cpu_interface = cir[0];
232*4882a593Smuzhiyun } else {
233*4882a593Smuzhiyun /* The system clock may not exceed 10 MHz */
234*4882a593Smuzhiyun if (clktmp > 10000000) {
235*4882a593Smuzhiyun priv->cpu_interface |= CPUIF_DSC;
236*4882a593Smuzhiyun clktmp /= 2;
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun /* The memory clock may not exceed 8 MHz */
239*4882a593Smuzhiyun if (clktmp > 8000000)
240*4882a593Smuzhiyun priv->cpu_interface |= CPUIF_DMC;
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun if (priv->cpu_interface & CPUIF_DSC)
244*4882a593Smuzhiyun priv->can.clock.freq /= 2;
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun if (bcr[idx] != 0xff)
247*4882a593Smuzhiyun priv->bus_config = bcr[idx];
248*4882a593Smuzhiyun else if (bcr[0] != 0xff)
249*4882a593Smuzhiyun priv->bus_config = bcr[0];
250*4882a593Smuzhiyun else
251*4882a593Smuzhiyun priv->bus_config = BCR_DEFAULT;
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun if (cor[idx] != 0xff)
254*4882a593Smuzhiyun priv->clkout = cor[idx];
255*4882a593Smuzhiyun else if (cor[0] != 0xff)
256*4882a593Smuzhiyun priv->clkout = cor[0];
257*4882a593Smuzhiyun else
258*4882a593Smuzhiyun priv->clkout = COR_DEFAULT;
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun platform_set_drvdata(pdev, dev);
261*4882a593Smuzhiyun SET_NETDEV_DEV(dev, &pdev->dev);
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun err = register_cc770dev(dev);
264*4882a593Smuzhiyun if (err) {
265*4882a593Smuzhiyun dev_err(&pdev->dev,
266*4882a593Smuzhiyun "couldn't register device (err=%d)\n", err);
267*4882a593Smuzhiyun goto exit_free;
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun dev_info(&pdev->dev, "device registered (reg_base=0x%p, irq=%d)\n",
271*4882a593Smuzhiyun priv->reg_base, dev->irq);
272*4882a593Smuzhiyun return 0;
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun exit_free:
275*4882a593Smuzhiyun free_cc770dev(dev);
276*4882a593Smuzhiyun exit_unmap:
277*4882a593Smuzhiyun if (mem[idx])
278*4882a593Smuzhiyun iounmap(base);
279*4882a593Smuzhiyun exit_release:
280*4882a593Smuzhiyun if (mem[idx])
281*4882a593Smuzhiyun release_mem_region(mem[idx], iosize);
282*4882a593Smuzhiyun else
283*4882a593Smuzhiyun release_region(port[idx], iosize);
284*4882a593Smuzhiyun exit:
285*4882a593Smuzhiyun return err;
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun
cc770_isa_remove(struct platform_device * pdev)288*4882a593Smuzhiyun static int cc770_isa_remove(struct platform_device *pdev)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun struct net_device *dev = platform_get_drvdata(pdev);
291*4882a593Smuzhiyun struct cc770_priv *priv = netdev_priv(dev);
292*4882a593Smuzhiyun int idx = pdev->id;
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun unregister_cc770dev(dev);
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun if (mem[idx]) {
297*4882a593Smuzhiyun iounmap(priv->reg_base);
298*4882a593Smuzhiyun release_mem_region(mem[idx], CC770_IOSIZE);
299*4882a593Smuzhiyun } else {
300*4882a593Smuzhiyun if (priv->read_reg == cc770_isa_port_read_reg_indirect)
301*4882a593Smuzhiyun release_region(port[idx], CC770_IOSIZE_INDIRECT);
302*4882a593Smuzhiyun else
303*4882a593Smuzhiyun release_region(port[idx], CC770_IOSIZE);
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun free_cc770dev(dev);
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun return 0;
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun static struct platform_driver cc770_isa_driver = {
311*4882a593Smuzhiyun .probe = cc770_isa_probe,
312*4882a593Smuzhiyun .remove = cc770_isa_remove,
313*4882a593Smuzhiyun .driver = {
314*4882a593Smuzhiyun .name = KBUILD_MODNAME,
315*4882a593Smuzhiyun },
316*4882a593Smuzhiyun };
317*4882a593Smuzhiyun
cc770_isa_init(void)318*4882a593Smuzhiyun static int __init cc770_isa_init(void)
319*4882a593Smuzhiyun {
320*4882a593Smuzhiyun int idx, err;
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun for (idx = 0; idx < ARRAY_SIZE(cc770_isa_devs); idx++) {
323*4882a593Smuzhiyun if ((port[idx] || mem[idx]) && irq[idx]) {
324*4882a593Smuzhiyun cc770_isa_devs[idx] =
325*4882a593Smuzhiyun platform_device_alloc(KBUILD_MODNAME, idx);
326*4882a593Smuzhiyun if (!cc770_isa_devs[idx]) {
327*4882a593Smuzhiyun err = -ENOMEM;
328*4882a593Smuzhiyun goto exit_free_devices;
329*4882a593Smuzhiyun }
330*4882a593Smuzhiyun err = platform_device_add(cc770_isa_devs[idx]);
331*4882a593Smuzhiyun if (err) {
332*4882a593Smuzhiyun platform_device_put(cc770_isa_devs[idx]);
333*4882a593Smuzhiyun goto exit_free_devices;
334*4882a593Smuzhiyun }
335*4882a593Smuzhiyun pr_debug("platform device %d: port=%#lx, mem=%#lx, "
336*4882a593Smuzhiyun "irq=%d\n",
337*4882a593Smuzhiyun idx, port[idx], mem[idx], irq[idx]);
338*4882a593Smuzhiyun } else if (idx == 0 || port[idx] || mem[idx]) {
339*4882a593Smuzhiyun pr_err("insufficient parameters supplied\n");
340*4882a593Smuzhiyun err = -EINVAL;
341*4882a593Smuzhiyun goto exit_free_devices;
342*4882a593Smuzhiyun }
343*4882a593Smuzhiyun }
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun err = platform_driver_register(&cc770_isa_driver);
346*4882a593Smuzhiyun if (err)
347*4882a593Smuzhiyun goto exit_free_devices;
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun pr_info("driver for max. %d devices registered\n", MAXDEV);
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun return 0;
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun exit_free_devices:
354*4882a593Smuzhiyun while (--idx >= 0) {
355*4882a593Smuzhiyun if (cc770_isa_devs[idx])
356*4882a593Smuzhiyun platform_device_unregister(cc770_isa_devs[idx]);
357*4882a593Smuzhiyun }
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun return err;
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun module_init(cc770_isa_init);
362*4882a593Smuzhiyun
cc770_isa_exit(void)363*4882a593Smuzhiyun static void __exit cc770_isa_exit(void)
364*4882a593Smuzhiyun {
365*4882a593Smuzhiyun int idx;
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun platform_driver_unregister(&cc770_isa_driver);
368*4882a593Smuzhiyun for (idx = 0; idx < ARRAY_SIZE(cc770_isa_devs); idx++) {
369*4882a593Smuzhiyun if (cc770_isa_devs[idx])
370*4882a593Smuzhiyun platform_device_unregister(cc770_isa_devs[idx]);
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun }
373*4882a593Smuzhiyun module_exit(cc770_isa_exit);
374