1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Core driver for the CC770 and AN82527 CAN controllers 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2009, 2011 Wolfgang Grandegger <wg@grandegger.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef CC770_DEV_H 9*4882a593Smuzhiyun #define CC770_DEV_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/can/dev.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct cc770_msgobj { 14*4882a593Smuzhiyun u8 ctrl0; 15*4882a593Smuzhiyun u8 ctrl1; 16*4882a593Smuzhiyun u8 id[4]; 17*4882a593Smuzhiyun u8 config; 18*4882a593Smuzhiyun u8 data[8]; 19*4882a593Smuzhiyun u8 dontuse; /* padding */ 20*4882a593Smuzhiyun } __packed; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun struct cc770_regs { 23*4882a593Smuzhiyun union { 24*4882a593Smuzhiyun struct cc770_msgobj msgobj[16]; /* Message object 1..15 */ 25*4882a593Smuzhiyun struct { 26*4882a593Smuzhiyun u8 control; /* Control Register */ 27*4882a593Smuzhiyun u8 status; /* Status Register */ 28*4882a593Smuzhiyun u8 cpu_interface; /* CPU Interface Register */ 29*4882a593Smuzhiyun u8 dontuse1; 30*4882a593Smuzhiyun u8 high_speed_read[2]; /* High Speed Read */ 31*4882a593Smuzhiyun u8 global_mask_std[2]; /* Standard Global Mask */ 32*4882a593Smuzhiyun u8 global_mask_ext[4]; /* Extended Global Mask */ 33*4882a593Smuzhiyun u8 msg15_mask[4]; /* Message 15 Mask */ 34*4882a593Smuzhiyun u8 dontuse2[15]; 35*4882a593Smuzhiyun u8 clkout; /* Clock Out Register */ 36*4882a593Smuzhiyun u8 dontuse3[15]; 37*4882a593Smuzhiyun u8 bus_config; /* Bus Configuration Register */ 38*4882a593Smuzhiyun u8 dontuse4[15]; 39*4882a593Smuzhiyun u8 bit_timing_0; /* Bit Timing Register byte 0 */ 40*4882a593Smuzhiyun u8 dontuse5[15]; 41*4882a593Smuzhiyun u8 bit_timing_1; /* Bit Timing Register byte 1 */ 42*4882a593Smuzhiyun u8 dontuse6[15]; 43*4882a593Smuzhiyun u8 interrupt; /* Interrupt Register */ 44*4882a593Smuzhiyun u8 dontuse7[15]; 45*4882a593Smuzhiyun u8 rx_error_counter; /* Receive Error Counter */ 46*4882a593Smuzhiyun u8 dontuse8[15]; 47*4882a593Smuzhiyun u8 tx_error_counter; /* Transmit Error Counter */ 48*4882a593Smuzhiyun u8 dontuse9[31]; 49*4882a593Smuzhiyun u8 p1_conf; 50*4882a593Smuzhiyun u8 dontuse10[15]; 51*4882a593Smuzhiyun u8 p2_conf; 52*4882a593Smuzhiyun u8 dontuse11[15]; 53*4882a593Smuzhiyun u8 p1_in; 54*4882a593Smuzhiyun u8 dontuse12[15]; 55*4882a593Smuzhiyun u8 p2_in; 56*4882a593Smuzhiyun u8 dontuse13[15]; 57*4882a593Smuzhiyun u8 p1_out; 58*4882a593Smuzhiyun u8 dontuse14[15]; 59*4882a593Smuzhiyun u8 p2_out; 60*4882a593Smuzhiyun u8 dontuse15[15]; 61*4882a593Smuzhiyun u8 serial_reset_addr; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun } __packed; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* Control Register (0x00) */ 67*4882a593Smuzhiyun #define CTRL_INI 0x01 /* Initialization */ 68*4882a593Smuzhiyun #define CTRL_IE 0x02 /* Interrupt Enable */ 69*4882a593Smuzhiyun #define CTRL_SIE 0x04 /* Status Interrupt Enable */ 70*4882a593Smuzhiyun #define CTRL_EIE 0x08 /* Error Interrupt Enable */ 71*4882a593Smuzhiyun #define CTRL_EAF 0x20 /* Enable additional functions */ 72*4882a593Smuzhiyun #define CTRL_CCE 0x40 /* Change Configuration Enable */ 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* Status Register (0x01) */ 75*4882a593Smuzhiyun #define STAT_LEC_STUFF 0x01 /* Stuff error */ 76*4882a593Smuzhiyun #define STAT_LEC_FORM 0x02 /* Form error */ 77*4882a593Smuzhiyun #define STAT_LEC_ACK 0x03 /* Acknowledgement error */ 78*4882a593Smuzhiyun #define STAT_LEC_BIT1 0x04 /* Bit1 error */ 79*4882a593Smuzhiyun #define STAT_LEC_BIT0 0x05 /* Bit0 error */ 80*4882a593Smuzhiyun #define STAT_LEC_CRC 0x06 /* CRC error */ 81*4882a593Smuzhiyun #define STAT_LEC_MASK 0x07 /* Last Error Code mask */ 82*4882a593Smuzhiyun #define STAT_TXOK 0x08 /* Transmit Message Successfully */ 83*4882a593Smuzhiyun #define STAT_RXOK 0x10 /* Receive Message Successfully */ 84*4882a593Smuzhiyun #define STAT_WAKE 0x20 /* Wake Up Status */ 85*4882a593Smuzhiyun #define STAT_WARN 0x40 /* Warning Status */ 86*4882a593Smuzhiyun #define STAT_BOFF 0x80 /* Bus Off Status */ 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* 89*4882a593Smuzhiyun * CPU Interface Register (0x02) 90*4882a593Smuzhiyun * Clock Out Register (0x1f) 91*4882a593Smuzhiyun * Bus Configuration Register (0x2f) 92*4882a593Smuzhiyun * 93*4882a593Smuzhiyun * see include/linux/can/platform/cc770.h 94*4882a593Smuzhiyun */ 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* Message Control Register 0 (Base Address + 0x0) */ 97*4882a593Smuzhiyun #define INTPND_RES 0x01 /* No Interrupt pending */ 98*4882a593Smuzhiyun #define INTPND_SET 0x02 /* Interrupt pending */ 99*4882a593Smuzhiyun #define INTPND_UNC 0x03 100*4882a593Smuzhiyun #define RXIE_RES 0x04 /* Receive Interrupt Disable */ 101*4882a593Smuzhiyun #define RXIE_SET 0x08 /* Receive Interrupt Enable */ 102*4882a593Smuzhiyun #define RXIE_UNC 0x0c 103*4882a593Smuzhiyun #define TXIE_RES 0x10 /* Transmit Interrupt Disable */ 104*4882a593Smuzhiyun #define TXIE_SET 0x20 /* Transmit Interrupt Enable */ 105*4882a593Smuzhiyun #define TXIE_UNC 0x30 106*4882a593Smuzhiyun #define MSGVAL_RES 0x40 /* Message Invalid */ 107*4882a593Smuzhiyun #define MSGVAL_SET 0x80 /* Message Valid */ 108*4882a593Smuzhiyun #define MSGVAL_UNC 0xc0 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* Message Control Register 1 (Base Address + 0x01) */ 111*4882a593Smuzhiyun #define NEWDAT_RES 0x01 /* No New Data */ 112*4882a593Smuzhiyun #define NEWDAT_SET 0x02 /* New Data */ 113*4882a593Smuzhiyun #define NEWDAT_UNC 0x03 114*4882a593Smuzhiyun #define MSGLST_RES 0x04 /* No Message Lost */ 115*4882a593Smuzhiyun #define MSGLST_SET 0x08 /* Message Lost */ 116*4882a593Smuzhiyun #define MSGLST_UNC 0x0c 117*4882a593Smuzhiyun #define CPUUPD_RES 0x04 /* No CPU Updating */ 118*4882a593Smuzhiyun #define CPUUPD_SET 0x08 /* CPU Updating */ 119*4882a593Smuzhiyun #define CPUUPD_UNC 0x0c 120*4882a593Smuzhiyun #define TXRQST_RES 0x10 /* No Transmission Request */ 121*4882a593Smuzhiyun #define TXRQST_SET 0x20 /* Transmission Request */ 122*4882a593Smuzhiyun #define TXRQST_UNC 0x30 123*4882a593Smuzhiyun #define RMTPND_RES 0x40 /* No Remote Request Pending */ 124*4882a593Smuzhiyun #define RMTPND_SET 0x80 /* Remote Request Pending */ 125*4882a593Smuzhiyun #define RMTPND_UNC 0xc0 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun /* Message Configuration Register (Base Address + 0x06) */ 128*4882a593Smuzhiyun #define MSGCFG_XTD 0x04 /* Extended Identifier */ 129*4882a593Smuzhiyun #define MSGCFG_DIR 0x08 /* Direction is Transmit */ 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #define MSGOBJ_FIRST 1 132*4882a593Smuzhiyun #define MSGOBJ_LAST 15 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #define CC770_IO_SIZE 0x100 135*4882a593Smuzhiyun #define CC770_MAX_IRQ 20 /* max. number of interrupts handled in ISR */ 136*4882a593Smuzhiyun #define CC770_MAX_MSG 4 /* max. number of messages handled in ISR */ 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun #define CC770_ECHO_SKB_MAX 1 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun #define cc770_read_reg(priv, member) \ 141*4882a593Smuzhiyun priv->read_reg(priv, offsetof(struct cc770_regs, member)) 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #define cc770_write_reg(priv, member, value) \ 144*4882a593Smuzhiyun priv->write_reg(priv, offsetof(struct cc770_regs, member), value) 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /* 147*4882a593Smuzhiyun * Message objects and flags used by this driver 148*4882a593Smuzhiyun */ 149*4882a593Smuzhiyun #define CC770_OBJ_FLAG_RX 0x01 150*4882a593Smuzhiyun #define CC770_OBJ_FLAG_RTR 0x02 151*4882a593Smuzhiyun #define CC770_OBJ_FLAG_EFF 0x04 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun enum { 154*4882a593Smuzhiyun CC770_OBJ_RX0 = 0, /* for receiving normal messages */ 155*4882a593Smuzhiyun CC770_OBJ_RX1, /* for receiving normal messages */ 156*4882a593Smuzhiyun CC770_OBJ_RX_RTR0, /* for receiving remote transmission requests */ 157*4882a593Smuzhiyun CC770_OBJ_RX_RTR1, /* for receiving remote transmission requests */ 158*4882a593Smuzhiyun CC770_OBJ_TX, /* for sending messages */ 159*4882a593Smuzhiyun CC770_OBJ_MAX 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun #define obj2msgobj(o) (MSGOBJ_LAST - (o)) /* message object 11..15 */ 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun /* 165*4882a593Smuzhiyun * CC770 private data structure 166*4882a593Smuzhiyun */ 167*4882a593Smuzhiyun struct cc770_priv { 168*4882a593Smuzhiyun struct can_priv can; /* must be the first member */ 169*4882a593Smuzhiyun struct sk_buff *echo_skb; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun /* the lower-layer is responsible for appropriate locking */ 172*4882a593Smuzhiyun u8 (*read_reg)(const struct cc770_priv *priv, int reg); 173*4882a593Smuzhiyun void (*write_reg)(const struct cc770_priv *priv, int reg, u8 val); 174*4882a593Smuzhiyun void (*pre_irq)(const struct cc770_priv *priv); 175*4882a593Smuzhiyun void (*post_irq)(const struct cc770_priv *priv); 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun void *priv; /* for board-specific data */ 178*4882a593Smuzhiyun struct net_device *dev; 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun void __iomem *reg_base; /* ioremap'ed address to registers */ 181*4882a593Smuzhiyun unsigned long irq_flags; /* for request_irq() */ 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun unsigned char obj_flags[CC770_OBJ_MAX]; 184*4882a593Smuzhiyun u8 control_normal_mode; /* Control register for normal mode */ 185*4882a593Smuzhiyun u8 cpu_interface; /* CPU interface register */ 186*4882a593Smuzhiyun u8 clkout; /* Clock out register */ 187*4882a593Smuzhiyun u8 bus_config; /* Bus configuration register */ 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun struct sk_buff *tx_skb; 190*4882a593Smuzhiyun }; 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun struct net_device *alloc_cc770dev(int sizeof_priv); 193*4882a593Smuzhiyun void free_cc770dev(struct net_device *dev); 194*4882a593Smuzhiyun int register_cc770dev(struct net_device *dev); 195*4882a593Smuzhiyun void unregister_cc770dev(struct net_device *dev); 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun #endif /* CC770_DEV_H */ 198