1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * ADGS1408/ADGS1409 SPI MUX driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2018 Analog Devices Inc.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/err.h>
9*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/mux/driver.h>
12*4882a593Smuzhiyun #include <linux/property.h>
13*4882a593Smuzhiyun #include <linux/spi/spi.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define ADGS1408_SW_DATA (0x01)
16*4882a593Smuzhiyun #define ADGS1408_REG_READ(reg) ((reg) | 0x80)
17*4882a593Smuzhiyun #define ADGS1408_DISABLE (0x00)
18*4882a593Smuzhiyun #define ADGS1408_MUX(state) (((state) << 1) | 1)
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun enum adgs1408_chip_id {
21*4882a593Smuzhiyun ADGS1408 = 1,
22*4882a593Smuzhiyun ADGS1409,
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun
adgs1408_spi_reg_write(struct spi_device * spi,u8 reg_addr,u8 reg_data)25*4882a593Smuzhiyun static int adgs1408_spi_reg_write(struct spi_device *spi,
26*4882a593Smuzhiyun u8 reg_addr, u8 reg_data)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun u8 tx_buf[2];
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun tx_buf[0] = reg_addr;
31*4882a593Smuzhiyun tx_buf[1] = reg_data;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun return spi_write_then_read(spi, tx_buf, sizeof(tx_buf), NULL, 0);
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
adgs1408_set(struct mux_control * mux,int state)36*4882a593Smuzhiyun static int adgs1408_set(struct mux_control *mux, int state)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun struct spi_device *spi = to_spi_device(mux->chip->dev.parent);
39*4882a593Smuzhiyun u8 reg;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun if (state == MUX_IDLE_DISCONNECT)
42*4882a593Smuzhiyun reg = ADGS1408_DISABLE;
43*4882a593Smuzhiyun else
44*4882a593Smuzhiyun reg = ADGS1408_MUX(state);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun return adgs1408_spi_reg_write(spi, ADGS1408_SW_DATA, reg);
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun static const struct mux_control_ops adgs1408_ops = {
50*4882a593Smuzhiyun .set = adgs1408_set,
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun
adgs1408_probe(struct spi_device * spi)53*4882a593Smuzhiyun static int adgs1408_probe(struct spi_device *spi)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun struct device *dev = &spi->dev;
56*4882a593Smuzhiyun enum adgs1408_chip_id chip_id;
57*4882a593Smuzhiyun struct mux_chip *mux_chip;
58*4882a593Smuzhiyun struct mux_control *mux;
59*4882a593Smuzhiyun s32 idle_state;
60*4882a593Smuzhiyun int ret;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun chip_id = (enum adgs1408_chip_id)device_get_match_data(dev);
63*4882a593Smuzhiyun if (!chip_id)
64*4882a593Smuzhiyun chip_id = spi_get_device_id(spi)->driver_data;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun mux_chip = devm_mux_chip_alloc(dev, 1, 0);
67*4882a593Smuzhiyun if (IS_ERR(mux_chip))
68*4882a593Smuzhiyun return PTR_ERR(mux_chip);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun mux_chip->ops = &adgs1408_ops;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun ret = adgs1408_spi_reg_write(spi, ADGS1408_SW_DATA, ADGS1408_DISABLE);
73*4882a593Smuzhiyun if (ret < 0)
74*4882a593Smuzhiyun return ret;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun ret = device_property_read_u32(dev, "idle-state", (u32 *)&idle_state);
77*4882a593Smuzhiyun if (ret < 0)
78*4882a593Smuzhiyun idle_state = MUX_IDLE_AS_IS;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun mux = mux_chip->mux;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun if (chip_id == ADGS1408)
83*4882a593Smuzhiyun mux->states = 8;
84*4882a593Smuzhiyun else
85*4882a593Smuzhiyun mux->states = 4;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun switch (idle_state) {
88*4882a593Smuzhiyun case MUX_IDLE_DISCONNECT:
89*4882a593Smuzhiyun case MUX_IDLE_AS_IS:
90*4882a593Smuzhiyun case 0 ... 7:
91*4882a593Smuzhiyun /* adgs1409 supports only 4 states */
92*4882a593Smuzhiyun if (idle_state < mux->states) {
93*4882a593Smuzhiyun mux->idle_state = idle_state;
94*4882a593Smuzhiyun break;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun fallthrough;
97*4882a593Smuzhiyun default:
98*4882a593Smuzhiyun dev_err(dev, "invalid idle-state %d\n", idle_state);
99*4882a593Smuzhiyun return -EINVAL;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun return devm_mux_chip_register(dev, mux_chip);
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun static const struct spi_device_id adgs1408_spi_id[] = {
106*4882a593Smuzhiyun { "adgs1408", ADGS1408 },
107*4882a593Smuzhiyun { "adgs1409", ADGS1409 },
108*4882a593Smuzhiyun { }
109*4882a593Smuzhiyun };
110*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, adgs1408_spi_id);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun static const struct of_device_id adgs1408_of_match[] = {
113*4882a593Smuzhiyun { .compatible = "adi,adgs1408", .data = (void *)ADGS1408, },
114*4882a593Smuzhiyun { .compatible = "adi,adgs1409", .data = (void *)ADGS1409, },
115*4882a593Smuzhiyun { }
116*4882a593Smuzhiyun };
117*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, adgs1408_of_match);
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun static struct spi_driver adgs1408_driver = {
120*4882a593Smuzhiyun .driver = {
121*4882a593Smuzhiyun .name = "adgs1408",
122*4882a593Smuzhiyun .of_match_table = adgs1408_of_match,
123*4882a593Smuzhiyun },
124*4882a593Smuzhiyun .probe = adgs1408_probe,
125*4882a593Smuzhiyun .id_table = adgs1408_spi_id,
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun module_spi_driver(adgs1408_driver);
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun MODULE_AUTHOR("Mircea Caprioru <mircea.caprioru@analog.com>");
130*4882a593Smuzhiyun MODULE_DESCRIPTION("Analog Devices ADGS1408 MUX driver");
131*4882a593Smuzhiyun MODULE_LICENSE("GPL");
132