1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2005, Intec Automation Inc. 4*4882a593Smuzhiyun * Copyright (C) 2014, Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __LINUX_MTD_SFDP_H 8*4882a593Smuzhiyun #define __LINUX_MTD_SFDP_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* SFDP revisions */ 11*4882a593Smuzhiyun #define SFDP_JESD216_MAJOR 1 12*4882a593Smuzhiyun #define SFDP_JESD216_MINOR 0 13*4882a593Smuzhiyun #define SFDP_JESD216A_MINOR 5 14*4882a593Smuzhiyun #define SFDP_JESD216B_MINOR 6 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Basic Flash Parameter Table */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* 19*4882a593Smuzhiyun * JESD216 rev D defines a Basic Flash Parameter Table of 20 DWORDs. 20*4882a593Smuzhiyun * They are indexed from 1 but C arrays are indexed from 0. 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun #define BFPT_DWORD(i) ((i) - 1) 23*4882a593Smuzhiyun #define BFPT_DWORD_MAX 20 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun struct sfdp_bfpt { 26*4882a593Smuzhiyun u32 dwords[BFPT_DWORD_MAX]; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* The first version of JESD216 defined only 9 DWORDs. */ 30*4882a593Smuzhiyun #define BFPT_DWORD_MAX_JESD216 9 31*4882a593Smuzhiyun #define BFPT_DWORD_MAX_JESD216B 16 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* 1st DWORD. */ 34*4882a593Smuzhiyun #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16) 35*4882a593Smuzhiyun #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17) 36*4882a593Smuzhiyun #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17) 37*4882a593Smuzhiyun #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17) 38*4882a593Smuzhiyun #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17) 39*4882a593Smuzhiyun #define BFPT_DWORD1_DTR BIT(19) 40*4882a593Smuzhiyun #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20) 41*4882a593Smuzhiyun #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21) 42*4882a593Smuzhiyun #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* 5th DWORD. */ 45*4882a593Smuzhiyun #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0) 46*4882a593Smuzhiyun #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* 11th DWORD. */ 49*4882a593Smuzhiyun #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4 50*4882a593Smuzhiyun #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* 15th DWORD. */ 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* 55*4882a593Smuzhiyun * (from JESD216 rev B) 56*4882a593Smuzhiyun * Quad Enable Requirements (QER): 57*4882a593Smuzhiyun * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4 58*4882a593Smuzhiyun * reads based on instruction. DQ3/HOLD# functions are hold during 59*4882a593Smuzhiyun * instruction phase. 60*4882a593Smuzhiyun * - 001b: QE is bit 1 of status register 2. It is set via Write Status with 61*4882a593Smuzhiyun * two data bytes where bit 1 of the second byte is one. 62*4882a593Smuzhiyun * [...] 63*4882a593Smuzhiyun * Writing only one byte to the status register has the side-effect of 64*4882a593Smuzhiyun * clearing status register 2, including the QE bit. The 100b code is 65*4882a593Smuzhiyun * used if writing one byte to the status register does not modify 66*4882a593Smuzhiyun * status register 2. 67*4882a593Smuzhiyun * - 010b: QE is bit 6 of status register 1. It is set via Write Status with 68*4882a593Smuzhiyun * one data byte where bit 6 is one. 69*4882a593Smuzhiyun * [...] 70*4882a593Smuzhiyun * - 011b: QE is bit 7 of status register 2. It is set via Write status 71*4882a593Smuzhiyun * register 2 instruction 3Eh with one data byte where bit 7 is one. 72*4882a593Smuzhiyun * [...] 73*4882a593Smuzhiyun * The status register 2 is read using instruction 3Fh. 74*4882a593Smuzhiyun * - 100b: QE is bit 1 of status register 2. It is set via Write Status with 75*4882a593Smuzhiyun * two data bytes where bit 1 of the second byte is one. 76*4882a593Smuzhiyun * [...] 77*4882a593Smuzhiyun * In contrast to the 001b code, writing one byte to the status 78*4882a593Smuzhiyun * register does not modify status register 2. 79*4882a593Smuzhiyun * - 101b: QE is bit 1 of status register 2. Status register 1 is read using 80*4882a593Smuzhiyun * Read Status instruction 05h. Status register2 is read using 81*4882a593Smuzhiyun * instruction 35h. QE is set via Write Status instruction 01h with 82*4882a593Smuzhiyun * two data bytes where bit 1 of the second byte is one. 83*4882a593Smuzhiyun * [...] 84*4882a593Smuzhiyun */ 85*4882a593Smuzhiyun #define BFPT_DWORD15_QER_MASK GENMASK(22, 20) 86*4882a593Smuzhiyun #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */ 87*4882a593Smuzhiyun #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20) 88*4882a593Smuzhiyun #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */ 89*4882a593Smuzhiyun #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20) 90*4882a593Smuzhiyun #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20) 91*4882a593Smuzhiyun #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun struct sfdp_parameter_header { 94*4882a593Smuzhiyun u8 id_lsb; 95*4882a593Smuzhiyun u8 minor; 96*4882a593Smuzhiyun u8 major; 97*4882a593Smuzhiyun u8 length; /* in double words */ 98*4882a593Smuzhiyun u8 parameter_table_pointer[3]; /* byte address */ 99*4882a593Smuzhiyun u8 id_msb; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun int spi_nor_parse_sfdp(struct spi_nor *nor, 103*4882a593Smuzhiyun struct spi_nor_flash_parameter *params); 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #endif /* __LINUX_MTD_SFDP_H */ 106