1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2005, Intec Automation Inc.
4*4882a593Smuzhiyun * Copyright (C) 2014, Freescale Semiconductor, Inc.
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/mtd/spi-nor.h>
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include "core.h"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun static int
is25lp256_post_bfpt_fixups(struct spi_nor * nor,const struct sfdp_parameter_header * bfpt_header,const struct sfdp_bfpt * bfpt,struct spi_nor_flash_parameter * params)12*4882a593Smuzhiyun is25lp256_post_bfpt_fixups(struct spi_nor *nor,
13*4882a593Smuzhiyun const struct sfdp_parameter_header *bfpt_header,
14*4882a593Smuzhiyun const struct sfdp_bfpt *bfpt,
15*4882a593Smuzhiyun struct spi_nor_flash_parameter *params)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun /*
18*4882a593Smuzhiyun * IS25LP256 supports 4B opcodes, but the BFPT advertises a
19*4882a593Smuzhiyun * BFPT_DWORD1_ADDRESS_BYTES_3_ONLY address width.
20*4882a593Smuzhiyun * Overwrite the address width advertised by the BFPT.
21*4882a593Smuzhiyun */
22*4882a593Smuzhiyun if ((bfpt->dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) ==
23*4882a593Smuzhiyun BFPT_DWORD1_ADDRESS_BYTES_3_ONLY)
24*4882a593Smuzhiyun nor->addr_width = 4;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun return 0;
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun static struct spi_nor_fixups is25lp256_fixups = {
30*4882a593Smuzhiyun .post_bfpt = is25lp256_post_bfpt_fixups,
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun static const struct flash_info issi_parts[] = {
34*4882a593Smuzhiyun /* ISSI */
35*4882a593Smuzhiyun { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) },
36*4882a593Smuzhiyun { "is25lq040b", INFO(0x9d4013, 0, 64 * 1024, 8,
37*4882a593Smuzhiyun SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
38*4882a593Smuzhiyun { "is25lp016d", INFO(0x9d6015, 0, 64 * 1024, 32,
39*4882a593Smuzhiyun SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
40*4882a593Smuzhiyun { "is25lp080d", INFO(0x9d6014, 0, 64 * 1024, 16,
41*4882a593Smuzhiyun SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
42*4882a593Smuzhiyun { "is25lp032", INFO(0x9d6016, 0, 64 * 1024, 64,
43*4882a593Smuzhiyun SECT_4K | SPI_NOR_DUAL_READ) },
44*4882a593Smuzhiyun { "is25lp064", INFO(0x9d6017, 0, 64 * 1024, 128,
45*4882a593Smuzhiyun SECT_4K | SPI_NOR_DUAL_READ) },
46*4882a593Smuzhiyun { "is25lp128", INFO(0x9d6018, 0, 64 * 1024, 256,
47*4882a593Smuzhiyun SECT_4K | SPI_NOR_DUAL_READ) },
48*4882a593Smuzhiyun { "is25lp256", INFO(0x9d6019, 0, 64 * 1024, 512,
49*4882a593Smuzhiyun SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
50*4882a593Smuzhiyun SPI_NOR_4B_OPCODES)
51*4882a593Smuzhiyun .fixups = &is25lp256_fixups },
52*4882a593Smuzhiyun { "is25wp032", INFO(0x9d7016, 0, 64 * 1024, 64,
53*4882a593Smuzhiyun SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
54*4882a593Smuzhiyun { "is25wp064", INFO(0x9d7017, 0, 64 * 1024, 128,
55*4882a593Smuzhiyun SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
56*4882a593Smuzhiyun { "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256,
57*4882a593Smuzhiyun SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
58*4882a593Smuzhiyun { "is25wp256", INFO(0x9d7019, 0, 64 * 1024, 512,
59*4882a593Smuzhiyun SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
60*4882a593Smuzhiyun SPI_NOR_4B_OPCODES)
61*4882a593Smuzhiyun .fixups = &is25lp256_fixups },
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* PMC */
64*4882a593Smuzhiyun { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
65*4882a593Smuzhiyun { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
66*4882a593Smuzhiyun { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun
issi_default_init(struct spi_nor * nor)69*4882a593Smuzhiyun static void issi_default_init(struct spi_nor *nor)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun static const struct spi_nor_fixups issi_fixups = {
75*4882a593Smuzhiyun .default_init = issi_default_init,
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun const struct spi_nor_manufacturer spi_nor_issi = {
79*4882a593Smuzhiyun .name = "issi",
80*4882a593Smuzhiyun .parts = issi_parts,
81*4882a593Smuzhiyun .nparts = ARRAY_SIZE(issi_parts),
82*4882a593Smuzhiyun .fixups = &issi_fixups,
83*4882a593Smuzhiyun };
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