1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2005, Intec Automation Inc.
4*4882a593Smuzhiyun * Copyright (C) 2014, Freescale Semiconductor, Inc.
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/mtd/spi-nor.h>
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include "core.h"
10*4882a593Smuzhiyun
gd25q256_default_init(struct spi_nor * nor)11*4882a593Smuzhiyun static void gd25q256_default_init(struct spi_nor *nor)
12*4882a593Smuzhiyun {
13*4882a593Smuzhiyun /*
14*4882a593Smuzhiyun * Some manufacturer like GigaDevice may use different
15*4882a593Smuzhiyun * bit to set QE on different memories, so the MFR can't
16*4882a593Smuzhiyun * indicate the quad_enable method for this case, we need
17*4882a593Smuzhiyun * to set it in the default_init fixup hook.
18*4882a593Smuzhiyun */
19*4882a593Smuzhiyun nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
20*4882a593Smuzhiyun }
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun static struct spi_nor_fixups gd25q256_fixups = {
23*4882a593Smuzhiyun .default_init = gd25q256_default_init,
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun static const struct flash_info gigadevice_parts[] = {
27*4882a593Smuzhiyun { "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32,
28*4882a593Smuzhiyun SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
29*4882a593Smuzhiyun SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
30*4882a593Smuzhiyun { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64,
31*4882a593Smuzhiyun SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
32*4882a593Smuzhiyun SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
33*4882a593Smuzhiyun { "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64,
34*4882a593Smuzhiyun SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
35*4882a593Smuzhiyun SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
36*4882a593Smuzhiyun { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
37*4882a593Smuzhiyun SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
38*4882a593Smuzhiyun SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
39*4882a593Smuzhiyun { "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128,
40*4882a593Smuzhiyun SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
41*4882a593Smuzhiyun SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
42*4882a593Smuzhiyun { "gd25lq128d", INFO(0xc86018, 0, 64 * 1024, 256,
43*4882a593Smuzhiyun SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
44*4882a593Smuzhiyun SPI_NOR_HAS_TB) },
45*4882a593Smuzhiyun { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
46*4882a593Smuzhiyun SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
47*4882a593Smuzhiyun SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
48*4882a593Smuzhiyun { "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
49*4882a593Smuzhiyun SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
50*4882a593Smuzhiyun SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |
51*4882a593Smuzhiyun SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6)
52*4882a593Smuzhiyun .fixups = &gd25q256_fixups },
53*4882a593Smuzhiyun { "gd25q512", INFO(0xc84020, 0, 64 * 1024, 1024,
54*4882a593Smuzhiyun SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
55*4882a593Smuzhiyun SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |
56*4882a593Smuzhiyun SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6)
57*4882a593Smuzhiyun .fixups = &gd25q256_fixups },
58*4882a593Smuzhiyun { "gd25lq255", INFO(0xc86019, 0, 64 * 1024, 512,
59*4882a593Smuzhiyun SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
60*4882a593Smuzhiyun SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) },
61*4882a593Smuzhiyun { "gd25lb512m", INFO(0xc8671a, 0, 64 * 1024, 1024,
62*4882a593Smuzhiyun SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
63*4882a593Smuzhiyun SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) },
64*4882a593Smuzhiyun { "gd25b512m", INFO(0xc8471a, 0, 64 * 1024, 1024,
65*4882a593Smuzhiyun SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
66*4882a593Smuzhiyun SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) },
67*4882a593Smuzhiyun { "gd55b01ge", INFO(0xc8471b, 0, 64 * 1024, 2048,
68*4882a593Smuzhiyun SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
69*4882a593Smuzhiyun SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) },
70*4882a593Smuzhiyun { "gd55lb01ge", INFO(0xc8671b, 0, 64 * 1024, 2048,
71*4882a593Smuzhiyun SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
72*4882a593Smuzhiyun SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) },
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun const struct spi_nor_manufacturer spi_nor_gigadevice = {
76*4882a593Smuzhiyun .name = "gigadevice",
77*4882a593Smuzhiyun .parts = gigadevice_parts,
78*4882a593Smuzhiyun .nparts = ARRAY_SIZE(gigadevice_parts),
79*4882a593Smuzhiyun };
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