1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2017 exceet electronics GmbH
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Authors:
6*4882a593Smuzhiyun * Frieder Schrempf <frieder.schrempf@exceet.de>
7*4882a593Smuzhiyun * Boris Brezillon <boris.brezillon@bootlin.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/mtd/spinand.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define SPINAND_MFR_WINBOND 0xEF
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define WINBOND_CFG_BUF_READ BIT(3)
17*4882a593Smuzhiyun #define WINBOND_STATUS_ECC_HAS_BITFLIPS_T (3 << 4)
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun static SPINAND_OP_VARIANTS(read_cache_variants,
20*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
21*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
22*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
23*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
24*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
25*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun static SPINAND_OP_VARIANTS(write_cache_variants,
28*4882a593Smuzhiyun SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
29*4882a593Smuzhiyun SPINAND_PROG_LOAD(true, 0, NULL, 0));
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun static SPINAND_OP_VARIANTS(update_cache_variants,
32*4882a593Smuzhiyun SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
33*4882a593Smuzhiyun SPINAND_PROG_LOAD(false, 0, NULL, 0));
34*4882a593Smuzhiyun
w25m02gv_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * region)35*4882a593Smuzhiyun static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section,
36*4882a593Smuzhiyun struct mtd_oob_region *region)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun if (section > 3)
39*4882a593Smuzhiyun return -ERANGE;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun region->offset = (16 * section) + 8;
42*4882a593Smuzhiyun region->length = 8;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun return 0;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
w25m02gv_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * region)47*4882a593Smuzhiyun static int w25m02gv_ooblayout_free(struct mtd_info *mtd, int section,
48*4882a593Smuzhiyun struct mtd_oob_region *region)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun if (section > 3)
51*4882a593Smuzhiyun return -ERANGE;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun region->offset = (16 * section) + 2;
54*4882a593Smuzhiyun region->length = 6;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun return 0;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun static const struct mtd_ooblayout_ops w25m02gv_ooblayout = {
60*4882a593Smuzhiyun .ecc = w25m02gv_ooblayout_ecc,
61*4882a593Smuzhiyun .free = w25m02gv_ooblayout_free,
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
w25m02gv_select_target(struct spinand_device * spinand,unsigned int target)64*4882a593Smuzhiyun static int w25m02gv_select_target(struct spinand_device *spinand,
65*4882a593Smuzhiyun unsigned int target)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0xc2, 1),
68*4882a593Smuzhiyun SPI_MEM_OP_NO_ADDR,
69*4882a593Smuzhiyun SPI_MEM_OP_NO_DUMMY,
70*4882a593Smuzhiyun SPI_MEM_OP_DATA_OUT(1,
71*4882a593Smuzhiyun spinand->scratchbuf,
72*4882a593Smuzhiyun 1));
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun *spinand->scratchbuf = target;
75*4882a593Smuzhiyun return spi_mem_exec_op(spinand->spimem, &op);
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
w25n02kv_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * region)78*4882a593Smuzhiyun static int w25n02kv_ooblayout_ecc(struct mtd_info *mtd, int section,
79*4882a593Smuzhiyun struct mtd_oob_region *region)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun if (section)
82*4882a593Smuzhiyun return -ERANGE;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun region->offset = 64;
85*4882a593Smuzhiyun region->length = 64;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun return 0;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
w25n02kv_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * region)90*4882a593Smuzhiyun static int w25n02kv_ooblayout_free(struct mtd_info *mtd, int section,
91*4882a593Smuzhiyun struct mtd_oob_region *region)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun if (section)
94*4882a593Smuzhiyun return -ERANGE;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /* Reserve 2 bytes for the BBM. */
97*4882a593Smuzhiyun region->offset = 2;
98*4882a593Smuzhiyun region->length = 62;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun return 0;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun static const struct mtd_ooblayout_ops w25n02kv_ooblayout = {
104*4882a593Smuzhiyun .ecc = w25n02kv_ooblayout_ecc,
105*4882a593Smuzhiyun .free = w25n02kv_ooblayout_free,
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
w25n02kv_ecc_get_status(struct spinand_device * spinand,u8 status)108*4882a593Smuzhiyun static int w25n02kv_ecc_get_status(struct spinand_device *spinand,
109*4882a593Smuzhiyun u8 status)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun struct nand_device *nand = spinand_to_nand(spinand);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun switch (status & STATUS_ECC_MASK) {
114*4882a593Smuzhiyun case STATUS_ECC_NO_BITFLIPS:
115*4882a593Smuzhiyun return 0;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun case STATUS_ECC_UNCOR_ERROR:
118*4882a593Smuzhiyun return -EBADMSG;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun case STATUS_ECC_HAS_BITFLIPS:
121*4882a593Smuzhiyun return 1;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun default:
124*4882a593Smuzhiyun return nanddev_get_ecc_requirements(nand)->strength;
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun return -EINVAL;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun static const struct spinand_info winbond_spinand_table[] = {
132*4882a593Smuzhiyun SPINAND_INFO("W25M02GV",
133*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab),
134*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 2),
135*4882a593Smuzhiyun NAND_ECCREQ(1, 512),
136*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
137*4882a593Smuzhiyun &write_cache_variants,
138*4882a593Smuzhiyun &update_cache_variants),
139*4882a593Smuzhiyun 0,
140*4882a593Smuzhiyun SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
141*4882a593Smuzhiyun SPINAND_SELECT_TARGET(w25m02gv_select_target)),
142*4882a593Smuzhiyun SPINAND_INFO("W25N512GV",
143*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xAA, 0x20),
144*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 64, 64, 512, 10, 1, 1, 1),
145*4882a593Smuzhiyun NAND_ECCREQ(1, 512),
146*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
147*4882a593Smuzhiyun &write_cache_variants,
148*4882a593Smuzhiyun &update_cache_variants),
149*4882a593Smuzhiyun 0,
150*4882a593Smuzhiyun SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
151*4882a593Smuzhiyun SPINAND_SELECT_TARGET(w25m02gv_select_target)),
152*4882a593Smuzhiyun SPINAND_INFO("W25N01GV",
153*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xAA, 0x21),
154*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
155*4882a593Smuzhiyun NAND_ECCREQ(1, 512),
156*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
157*4882a593Smuzhiyun &write_cache_variants,
158*4882a593Smuzhiyun &update_cache_variants),
159*4882a593Smuzhiyun 0,
160*4882a593Smuzhiyun SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
161*4882a593Smuzhiyun SPINAND_SELECT_TARGET(w25m02gv_select_target)),
162*4882a593Smuzhiyun SPINAND_INFO("W25N02KV",
163*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xAA, 0x22),
164*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 128, 64, 2048, 20, 1, 1, 1),
165*4882a593Smuzhiyun NAND_ECCREQ(8, 512),
166*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
167*4882a593Smuzhiyun &write_cache_variants,
168*4882a593Smuzhiyun &update_cache_variants),
169*4882a593Smuzhiyun 0,
170*4882a593Smuzhiyun SPINAND_ECCINFO(&w25n02kv_ooblayout,
171*4882a593Smuzhiyun w25n02kv_ecc_get_status)),
172*4882a593Smuzhiyun SPINAND_INFO("W25N04KV",
173*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xAA, 0x23),
174*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 128, 64, 4096, 40, 1, 1, 1),
175*4882a593Smuzhiyun NAND_ECCREQ(8, 512),
176*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
177*4882a593Smuzhiyun &write_cache_variants,
178*4882a593Smuzhiyun &update_cache_variants),
179*4882a593Smuzhiyun 0,
180*4882a593Smuzhiyun SPINAND_ECCINFO(&w25n02kv_ooblayout,
181*4882a593Smuzhiyun w25n02kv_ecc_get_status)),
182*4882a593Smuzhiyun SPINAND_INFO("W25N01GW",
183*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBA, 0x21),
184*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
185*4882a593Smuzhiyun NAND_ECCREQ(1, 512),
186*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
187*4882a593Smuzhiyun &write_cache_variants,
188*4882a593Smuzhiyun &update_cache_variants),
189*4882a593Smuzhiyun 0,
190*4882a593Smuzhiyun SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
191*4882a593Smuzhiyun SPINAND_SELECT_TARGET(w25m02gv_select_target)),
192*4882a593Smuzhiyun SPINAND_INFO("W25N02KW",
193*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBA, 0x22),
194*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 128, 64, 2048, 20, 1, 1, 1),
195*4882a593Smuzhiyun NAND_ECCREQ(8, 512),
196*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
197*4882a593Smuzhiyun &write_cache_variants,
198*4882a593Smuzhiyun &update_cache_variants),
199*4882a593Smuzhiyun 0,
200*4882a593Smuzhiyun SPINAND_ECCINFO(&w25n02kv_ooblayout,
201*4882a593Smuzhiyun w25n02kv_ecc_get_status)),
202*4882a593Smuzhiyun SPINAND_INFO("W25N01KV",
203*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xAE, 0x21),
204*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
205*4882a593Smuzhiyun NAND_ECCREQ(4, 512),
206*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
207*4882a593Smuzhiyun &write_cache_variants,
208*4882a593Smuzhiyun &update_cache_variants),
209*4882a593Smuzhiyun 0,
210*4882a593Smuzhiyun SPINAND_ECCINFO(&w25n02kv_ooblayout,
211*4882a593Smuzhiyun w25n02kv_ecc_get_status)),
212*4882a593Smuzhiyun };
213*4882a593Smuzhiyun
winbond_spinand_init(struct spinand_device * spinand)214*4882a593Smuzhiyun static int winbond_spinand_init(struct spinand_device *spinand)
215*4882a593Smuzhiyun {
216*4882a593Smuzhiyun struct nand_device *nand = spinand_to_nand(spinand);
217*4882a593Smuzhiyun unsigned int i;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun /*
220*4882a593Smuzhiyun * Make sure all dies are in buffer read mode and not continuous read
221*4882a593Smuzhiyun * mode.
222*4882a593Smuzhiyun */
223*4882a593Smuzhiyun for (i = 0; i < nand->memorg.ntargets; i++) {
224*4882a593Smuzhiyun spinand_select_target(spinand, i);
225*4882a593Smuzhiyun spinand_upd_cfg(spinand, WINBOND_CFG_BUF_READ,
226*4882a593Smuzhiyun WINBOND_CFG_BUF_READ);
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun return 0;
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = {
233*4882a593Smuzhiyun .init = winbond_spinand_init,
234*4882a593Smuzhiyun };
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun const struct spinand_manufacturer winbond_spinand_manufacturer = {
237*4882a593Smuzhiyun .id = SPINAND_MFR_WINBOND,
238*4882a593Smuzhiyun .name = "Winbond",
239*4882a593Smuzhiyun .chips = winbond_spinand_table,
240*4882a593Smuzhiyun .nchips = ARRAY_SIZE(winbond_spinand_table),
241*4882a593Smuzhiyun .ops = &winbond_spinand_manuf_ops,
242*4882a593Smuzhiyun };
243