1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2018 Macronix
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author: Boris Brezillon <boris.brezillon@bootlin.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/device.h>
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/mtd/spinand.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #define SPINAND_MFR_MACRONIX 0xC2
13*4882a593Smuzhiyun #define MACRONIX_ECCSR_MASK 0x0F
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun static SPINAND_OP_VARIANTS(read_cache_variants,
16*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
17*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
18*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
19*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun static SPINAND_OP_VARIANTS(write_cache_variants,
22*4882a593Smuzhiyun SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
23*4882a593Smuzhiyun SPINAND_PROG_LOAD(true, 0, NULL, 0));
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun static SPINAND_OP_VARIANTS(update_cache_variants,
26*4882a593Smuzhiyun SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
27*4882a593Smuzhiyun SPINAND_PROG_LOAD(false, 0, NULL, 0));
28*4882a593Smuzhiyun
mx35lfxge4ab_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * region)29*4882a593Smuzhiyun static int mx35lfxge4ab_ooblayout_ecc(struct mtd_info *mtd, int section,
30*4882a593Smuzhiyun struct mtd_oob_region *region)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun return -ERANGE;
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun
mx35lfxge4ab_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * region)35*4882a593Smuzhiyun static int mx35lfxge4ab_ooblayout_free(struct mtd_info *mtd, int section,
36*4882a593Smuzhiyun struct mtd_oob_region *region)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun if (section)
39*4882a593Smuzhiyun return -ERANGE;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun region->offset = 2;
42*4882a593Smuzhiyun region->length = mtd->oobsize - 2;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun return 0;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun static const struct mtd_ooblayout_ops mx35lfxge4ab_ooblayout = {
48*4882a593Smuzhiyun .ecc = mx35lfxge4ab_ooblayout_ecc,
49*4882a593Smuzhiyun .free = mx35lfxge4ab_ooblayout_free,
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun
mx35ufxge4ad_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * region)52*4882a593Smuzhiyun static int mx35ufxge4ad_ooblayout_ecc(struct mtd_info *mtd, int section,
53*4882a593Smuzhiyun struct mtd_oob_region *region)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun if (section)
56*4882a593Smuzhiyun return -ERANGE;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun region->offset = mtd->oobsize / 2;
59*4882a593Smuzhiyun region->length = mtd->oobsize / 2;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun return 0;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
mx35ufxge4ad_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * region)64*4882a593Smuzhiyun static int mx35ufxge4ad_ooblayout_free(struct mtd_info *mtd, int section,
65*4882a593Smuzhiyun struct mtd_oob_region *region)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun if (section)
68*4882a593Smuzhiyun return -ERANGE;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun region->offset = 2;
71*4882a593Smuzhiyun region->length = mtd->oobsize / 2 - 2;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun return 0;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun static const struct mtd_ooblayout_ops mx35ufxge4ad_ooblayout = {
77*4882a593Smuzhiyun .ecc = mx35ufxge4ad_ooblayout_ecc,
78*4882a593Smuzhiyun .free = mx35ufxge4ad_ooblayout_free,
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun
mx35lf1ge4ab_get_eccsr(struct spinand_device * spinand,u8 * eccsr)81*4882a593Smuzhiyun static int mx35lf1ge4ab_get_eccsr(struct spinand_device *spinand, u8 *eccsr)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x7c, 1),
84*4882a593Smuzhiyun SPI_MEM_OP_NO_ADDR,
85*4882a593Smuzhiyun SPI_MEM_OP_DUMMY(1, 1),
86*4882a593Smuzhiyun SPI_MEM_OP_DATA_IN(1, eccsr, 1));
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun int ret = spi_mem_exec_op(spinand->spimem, &op);
89*4882a593Smuzhiyun if (ret)
90*4882a593Smuzhiyun return ret;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun *eccsr &= MACRONIX_ECCSR_MASK;
93*4882a593Smuzhiyun return 0;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
mx35lf1ge4ab_ecc_get_status(struct spinand_device * spinand,u8 status)96*4882a593Smuzhiyun static int mx35lf1ge4ab_ecc_get_status(struct spinand_device *spinand,
97*4882a593Smuzhiyun u8 status)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun struct nand_device *nand = spinand_to_nand(spinand);
100*4882a593Smuzhiyun u8 eccsr;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun switch (status & STATUS_ECC_MASK) {
103*4882a593Smuzhiyun case STATUS_ECC_NO_BITFLIPS:
104*4882a593Smuzhiyun return 0;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun case STATUS_ECC_UNCOR_ERROR:
107*4882a593Smuzhiyun return -EBADMSG;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun case STATUS_ECC_HAS_BITFLIPS:
110*4882a593Smuzhiyun /*
111*4882a593Smuzhiyun * Let's try to retrieve the real maximum number of bitflips
112*4882a593Smuzhiyun * in order to avoid forcing the wear-leveling layer to move
113*4882a593Smuzhiyun * data around if it's not necessary.
114*4882a593Smuzhiyun */
115*4882a593Smuzhiyun if (mx35lf1ge4ab_get_eccsr(spinand, &eccsr))
116*4882a593Smuzhiyun return nanddev_get_ecc_requirements(nand)->strength;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun if (WARN_ON(eccsr > nanddev_get_ecc_requirements(nand)->strength ||
119*4882a593Smuzhiyun !eccsr))
120*4882a593Smuzhiyun return nanddev_get_ecc_requirements(nand)->strength;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun return eccsr;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun default:
125*4882a593Smuzhiyun break;
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun return -EINVAL;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun static const struct spinand_info macronix_spinand_table[] = {
132*4882a593Smuzhiyun SPINAND_INFO("MX35LF1GE4AB",
133*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x12),
134*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
135*4882a593Smuzhiyun NAND_ECCREQ(4, 512),
136*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
137*4882a593Smuzhiyun &write_cache_variants,
138*4882a593Smuzhiyun &update_cache_variants),
139*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
140*4882a593Smuzhiyun SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
141*4882a593Smuzhiyun mx35lf1ge4ab_ecc_get_status)),
142*4882a593Smuzhiyun SPINAND_INFO("MX35LF2GE4AB",
143*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x22),
144*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1),
145*4882a593Smuzhiyun NAND_ECCREQ(4, 512),
146*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
147*4882a593Smuzhiyun &write_cache_variants,
148*4882a593Smuzhiyun &update_cache_variants),
149*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
150*4882a593Smuzhiyun SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
151*4882a593Smuzhiyun SPINAND_INFO("MX35LF2GE4AD",
152*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x26),
153*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
154*4882a593Smuzhiyun NAND_ECCREQ(8, 512),
155*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
156*4882a593Smuzhiyun &write_cache_variants,
157*4882a593Smuzhiyun &update_cache_variants),
158*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
159*4882a593Smuzhiyun SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
160*4882a593Smuzhiyun mx35lf1ge4ab_ecc_get_status)),
161*4882a593Smuzhiyun SPINAND_INFO("MX35LF4GE4AD",
162*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x37),
163*4882a593Smuzhiyun NAND_MEMORG(1, 4096, 128, 64, 2048, 40, 1, 1, 1),
164*4882a593Smuzhiyun NAND_ECCREQ(8, 512),
165*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
166*4882a593Smuzhiyun &write_cache_variants,
167*4882a593Smuzhiyun &update_cache_variants),
168*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
169*4882a593Smuzhiyun SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
170*4882a593Smuzhiyun mx35lf1ge4ab_ecc_get_status)),
171*4882a593Smuzhiyun SPINAND_INFO("MX35LF1G24AD",
172*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14),
173*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
174*4882a593Smuzhiyun NAND_ECCREQ(8, 512),
175*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
176*4882a593Smuzhiyun &write_cache_variants,
177*4882a593Smuzhiyun &update_cache_variants),
178*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
179*4882a593Smuzhiyun SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
180*4882a593Smuzhiyun SPINAND_INFO("MX35LF2G24AD",
181*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24),
182*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
183*4882a593Smuzhiyun NAND_ECCREQ(8, 512),
184*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
185*4882a593Smuzhiyun &write_cache_variants,
186*4882a593Smuzhiyun &update_cache_variants),
187*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
188*4882a593Smuzhiyun SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
189*4882a593Smuzhiyun SPINAND_INFO("MX35LF4G24AD",
190*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
191*4882a593Smuzhiyun NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 2, 1, 1),
192*4882a593Smuzhiyun NAND_ECCREQ(8, 512),
193*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
194*4882a593Smuzhiyun &write_cache_variants,
195*4882a593Smuzhiyun &update_cache_variants),
196*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
197*4882a593Smuzhiyun SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
198*4882a593Smuzhiyun SPINAND_INFO("MX31LF1GE4BC",
199*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x1e),
200*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
201*4882a593Smuzhiyun NAND_ECCREQ(8, 512),
202*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
203*4882a593Smuzhiyun &write_cache_variants,
204*4882a593Smuzhiyun &update_cache_variants),
205*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
206*4882a593Smuzhiyun SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
207*4882a593Smuzhiyun mx35lf1ge4ab_ecc_get_status)),
208*4882a593Smuzhiyun SPINAND_INFO("MX31UF1GE4BC",
209*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x9e),
210*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
211*4882a593Smuzhiyun NAND_ECCREQ(8, 512),
212*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
213*4882a593Smuzhiyun &write_cache_variants,
214*4882a593Smuzhiyun &update_cache_variants),
215*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
216*4882a593Smuzhiyun SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
217*4882a593Smuzhiyun mx35lf1ge4ab_ecc_get_status)),
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun SPINAND_INFO("MX35LF2G14AC",
220*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x20),
221*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1),
222*4882a593Smuzhiyun NAND_ECCREQ(4, 512),
223*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
224*4882a593Smuzhiyun &write_cache_variants,
225*4882a593Smuzhiyun &update_cache_variants),
226*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
227*4882a593Smuzhiyun SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
228*4882a593Smuzhiyun mx35lf1ge4ab_ecc_get_status)),
229*4882a593Smuzhiyun SPINAND_INFO("MX35UF4G24AD",
230*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb5),
231*4882a593Smuzhiyun NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 2, 1, 1),
232*4882a593Smuzhiyun NAND_ECCREQ(8, 512),
233*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
234*4882a593Smuzhiyun &write_cache_variants,
235*4882a593Smuzhiyun &update_cache_variants),
236*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
237*4882a593Smuzhiyun SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
238*4882a593Smuzhiyun mx35lf1ge4ab_ecc_get_status)),
239*4882a593Smuzhiyun SPINAND_INFO("MX35UF4GE4AD",
240*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb7),
241*4882a593Smuzhiyun NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
242*4882a593Smuzhiyun NAND_ECCREQ(8, 512),
243*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
244*4882a593Smuzhiyun &write_cache_variants,
245*4882a593Smuzhiyun &update_cache_variants),
246*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
247*4882a593Smuzhiyun SPINAND_ECCINFO(&mx35ufxge4ad_ooblayout,
248*4882a593Smuzhiyun mx35lf1ge4ab_ecc_get_status)),
249*4882a593Smuzhiyun SPINAND_INFO("MX35UF2G14AC",
250*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa0),
251*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1),
252*4882a593Smuzhiyun NAND_ECCREQ(4, 512),
253*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
254*4882a593Smuzhiyun &write_cache_variants,
255*4882a593Smuzhiyun &update_cache_variants),
256*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
257*4882a593Smuzhiyun SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
258*4882a593Smuzhiyun mx35lf1ge4ab_ecc_get_status)),
259*4882a593Smuzhiyun SPINAND_INFO("MX35UF2G24AD",
260*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa4),
261*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
262*4882a593Smuzhiyun NAND_ECCREQ(8, 512),
263*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
264*4882a593Smuzhiyun &write_cache_variants,
265*4882a593Smuzhiyun &update_cache_variants),
266*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
267*4882a593Smuzhiyun SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
268*4882a593Smuzhiyun mx35lf1ge4ab_ecc_get_status)),
269*4882a593Smuzhiyun SPINAND_INFO("MX35UF2GE4AD",
270*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa6),
271*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
272*4882a593Smuzhiyun NAND_ECCREQ(8, 512),
273*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
274*4882a593Smuzhiyun &write_cache_variants,
275*4882a593Smuzhiyun &update_cache_variants),
276*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
277*4882a593Smuzhiyun SPINAND_ECCINFO(&mx35ufxge4ad_ooblayout,
278*4882a593Smuzhiyun mx35lf1ge4ab_ecc_get_status)),
279*4882a593Smuzhiyun SPINAND_INFO("MX35UF2GE4AC",
280*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa2),
281*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
282*4882a593Smuzhiyun NAND_ECCREQ(4, 512),
283*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
284*4882a593Smuzhiyun &write_cache_variants,
285*4882a593Smuzhiyun &update_cache_variants),
286*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
287*4882a593Smuzhiyun SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
288*4882a593Smuzhiyun mx35lf1ge4ab_ecc_get_status)),
289*4882a593Smuzhiyun SPINAND_INFO("MX35UF1G14AC",
290*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x90),
291*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
292*4882a593Smuzhiyun NAND_ECCREQ(4, 512),
293*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
294*4882a593Smuzhiyun &write_cache_variants,
295*4882a593Smuzhiyun &update_cache_variants),
296*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
297*4882a593Smuzhiyun SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
298*4882a593Smuzhiyun mx35lf1ge4ab_ecc_get_status)),
299*4882a593Smuzhiyun SPINAND_INFO("MX35UF1G24AD",
300*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x94),
301*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
302*4882a593Smuzhiyun NAND_ECCREQ(8, 512),
303*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
304*4882a593Smuzhiyun &write_cache_variants,
305*4882a593Smuzhiyun &update_cache_variants),
306*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
307*4882a593Smuzhiyun SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
308*4882a593Smuzhiyun mx35lf1ge4ab_ecc_get_status)),
309*4882a593Smuzhiyun SPINAND_INFO("MX35UF1GE4AD",
310*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x96),
311*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
312*4882a593Smuzhiyun NAND_ECCREQ(8, 512),
313*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
314*4882a593Smuzhiyun &write_cache_variants,
315*4882a593Smuzhiyun &update_cache_variants),
316*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
317*4882a593Smuzhiyun SPINAND_ECCINFO(&mx35ufxge4ad_ooblayout,
318*4882a593Smuzhiyun mx35lf1ge4ab_ecc_get_status)),
319*4882a593Smuzhiyun SPINAND_INFO("MX35UF1GE4AC",
320*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92),
321*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
322*4882a593Smuzhiyun NAND_ECCREQ(4, 512),
323*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
324*4882a593Smuzhiyun &write_cache_variants,
325*4882a593Smuzhiyun &update_cache_variants),
326*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
327*4882a593Smuzhiyun SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
328*4882a593Smuzhiyun mx35lf1ge4ab_ecc_get_status)),
329*4882a593Smuzhiyun };
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun static const struct spinand_manufacturer_ops macronix_spinand_manuf_ops = {
332*4882a593Smuzhiyun };
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun const struct spinand_manufacturer macronix_spinand_manufacturer = {
335*4882a593Smuzhiyun .id = SPINAND_MFR_MACRONIX,
336*4882a593Smuzhiyun .name = "Macronix",
337*4882a593Smuzhiyun .chips = macronix_spinand_table,
338*4882a593Smuzhiyun .nchips = ARRAY_SIZE(macronix_spinand_table),
339*4882a593Smuzhiyun .ops = ¯onix_spinand_manuf_ops,
340*4882a593Smuzhiyun };
341