1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2020 Grandstream Networks, Inc
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Authors:
6*4882a593Smuzhiyun * Carl <xjxia@grandstream.cn>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/device.h>
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/mtd/spinand.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define SPINAND_MFR_FORESEE 0xCD
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun static SPINAND_OP_VARIANTS(read_cache_variants,
16*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
17*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
18*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
19*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
20*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
21*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun static SPINAND_OP_VARIANTS(write_cache_variants,
24*4882a593Smuzhiyun SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
25*4882a593Smuzhiyun SPINAND_PROG_LOAD(true, 0, NULL, 0));
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun static SPINAND_OP_VARIANTS(update_cache_variants,
28*4882a593Smuzhiyun SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
29*4882a593Smuzhiyun SPINAND_PROG_LOAD(true, 0, NULL, 0));
30*4882a593Smuzhiyun
fsxxndxxg_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * region)31*4882a593Smuzhiyun static int fsxxndxxg_ooblayout_ecc(struct mtd_info *mtd, int section,
32*4882a593Smuzhiyun struct mtd_oob_region *region)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun return -ERANGE;
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
fsxxndxxg_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * region)37*4882a593Smuzhiyun static int fsxxndxxg_ooblayout_free(struct mtd_info *mtd, int section,
38*4882a593Smuzhiyun struct mtd_oob_region *region)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun if (section)
41*4882a593Smuzhiyun return -ERANGE;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun region->offset = 2;
44*4882a593Smuzhiyun region->length = mtd->oobsize - 2;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun return 0;
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun static const struct mtd_ooblayout_ops fsxxndxxg_ooblayout = {
50*4882a593Smuzhiyun .ecc = fsxxndxxg_ooblayout_ecc,
51*4882a593Smuzhiyun .free = fsxxndxxg_ooblayout_free,
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun static const struct spinand_info foresee_spinand_table[] = {
55*4882a593Smuzhiyun SPINAND_INFO("FS35ND01G-S1Y2",
56*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xEA),
57*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
58*4882a593Smuzhiyun NAND_ECCREQ(4, 512),
59*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
60*4882a593Smuzhiyun &write_cache_variants,
61*4882a593Smuzhiyun &update_cache_variants),
62*4882a593Smuzhiyun 0,
63*4882a593Smuzhiyun SPINAND_ECCINFO(&fsxxndxxg_ooblayout, NULL)),
64*4882a593Smuzhiyun SPINAND_INFO("FS35ND02G-S3Y2",
65*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xEB),
66*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
67*4882a593Smuzhiyun NAND_ECCREQ(4, 512),
68*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
69*4882a593Smuzhiyun &write_cache_variants,
70*4882a593Smuzhiyun &update_cache_variants),
71*4882a593Smuzhiyun 0,
72*4882a593Smuzhiyun SPINAND_ECCINFO(&fsxxndxxg_ooblayout, NULL)),
73*4882a593Smuzhiyun SPINAND_INFO("FS35ND04G-S2Y2",
74*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xEC),
75*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 64, 64, 4096, 80, 1, 1, 1),
76*4882a593Smuzhiyun NAND_ECCREQ(4, 512),
77*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
78*4882a593Smuzhiyun &write_cache_variants,
79*4882a593Smuzhiyun &update_cache_variants),
80*4882a593Smuzhiyun 0,
81*4882a593Smuzhiyun SPINAND_ECCINFO(&fsxxndxxg_ooblayout, NULL)),
82*4882a593Smuzhiyun SPINAND_INFO("F35SQA001G",
83*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71),
84*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
85*4882a593Smuzhiyun NAND_ECCREQ(1, 512),
86*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
87*4882a593Smuzhiyun &write_cache_variants,
88*4882a593Smuzhiyun &update_cache_variants),
89*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
90*4882a593Smuzhiyun SPINAND_ECCINFO(&fsxxndxxg_ooblayout, NULL)),
91*4882a593Smuzhiyun SPINAND_INFO("F35SQA002G",
92*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x72),
93*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
94*4882a593Smuzhiyun NAND_ECCREQ(1, 512),
95*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
96*4882a593Smuzhiyun &write_cache_variants,
97*4882a593Smuzhiyun &update_cache_variants),
98*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
99*4882a593Smuzhiyun SPINAND_ECCINFO(&fsxxndxxg_ooblayout, NULL)),
100*4882a593Smuzhiyun SPINAND_INFO("F35SQA512M",
101*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x70),
102*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 64, 64, 512, 20, 1, 1, 1),
103*4882a593Smuzhiyun NAND_ECCREQ(1, 512),
104*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
105*4882a593Smuzhiyun &write_cache_variants,
106*4882a593Smuzhiyun &update_cache_variants),
107*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
108*4882a593Smuzhiyun SPINAND_ECCINFO(&fsxxndxxg_ooblayout, NULL)),
109*4882a593Smuzhiyun SPINAND_INFO("F35UQA512M",
110*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x60),
111*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 64, 64, 512, 20, 1, 1, 1),
112*4882a593Smuzhiyun NAND_ECCREQ(1, 512),
113*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
114*4882a593Smuzhiyun &write_cache_variants,
115*4882a593Smuzhiyun &update_cache_variants),
116*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
117*4882a593Smuzhiyun SPINAND_ECCINFO(&fsxxndxxg_ooblayout, NULL)),
118*4882a593Smuzhiyun SPINAND_INFO("F35UQA002G-WWT",
119*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x62),
120*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
121*4882a593Smuzhiyun NAND_ECCREQ(1, 512),
122*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
123*4882a593Smuzhiyun &write_cache_variants,
124*4882a593Smuzhiyun &update_cache_variants),
125*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
126*4882a593Smuzhiyun SPINAND_ECCINFO(&fsxxndxxg_ooblayout, NULL)),
127*4882a593Smuzhiyun SPINAND_INFO("F35UQA001G-WWT",
128*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x61),
129*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
130*4882a593Smuzhiyun NAND_ECCREQ(1, 512),
131*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
132*4882a593Smuzhiyun &write_cache_variants,
133*4882a593Smuzhiyun &update_cache_variants),
134*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
135*4882a593Smuzhiyun SPINAND_ECCINFO(&fsxxndxxg_ooblayout, NULL)),
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun static const struct spinand_manufacturer_ops foresee_spinand_manuf_ops = {
139*4882a593Smuzhiyun };
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun const struct spinand_manufacturer foresee_spinand_manufacturer = {
142*4882a593Smuzhiyun .id = SPINAND_MFR_FORESEE,
143*4882a593Smuzhiyun .name = "foresee",
144*4882a593Smuzhiyun .chips = foresee_spinand_table,
145*4882a593Smuzhiyun .nchips = ARRAY_SIZE(foresee_spinand_table),
146*4882a593Smuzhiyun .ops = &foresee_spinand_manuf_ops,
147*4882a593Smuzhiyun };
148