1*4882a593Smuzhiyun // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/device.h>
7*4882a593Smuzhiyun #include <linux/kernel.h>
8*4882a593Smuzhiyun #include <linux/mtd/spinand.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #define SPINAND_MFR_BIWIN 0xBC
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #define BIWIN_CFG_BUF_READ BIT(3)
13*4882a593Smuzhiyun #define BIWIN_STATUS_ECC_HAS_BITFLIPS_T (3 << 4)
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun static SPINAND_OP_VARIANTS(read_cache_variants,
16*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
17*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
18*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
19*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
20*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
21*4882a593Smuzhiyun SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun static SPINAND_OP_VARIANTS(write_cache_variants,
24*4882a593Smuzhiyun SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
25*4882a593Smuzhiyun SPINAND_PROG_LOAD(true, 0, NULL, 0));
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun static SPINAND_OP_VARIANTS(update_cache_variants,
28*4882a593Smuzhiyun SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
29*4882a593Smuzhiyun SPINAND_PROG_LOAD(false, 0, NULL, 0));
30*4882a593Smuzhiyun
bwjx08k_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * region)31*4882a593Smuzhiyun static int bwjx08k_ooblayout_ecc(struct mtd_info *mtd, int section,
32*4882a593Smuzhiyun struct mtd_oob_region *region)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun if (section > 3)
35*4882a593Smuzhiyun return -ERANGE;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun region->offset = (16 * section) + 12;
38*4882a593Smuzhiyun region->length = 4;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun return 0;
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
bwjx08k_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * region)43*4882a593Smuzhiyun static int bwjx08k_ooblayout_free(struct mtd_info *mtd, int section,
44*4882a593Smuzhiyun struct mtd_oob_region *region)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun if (section > 3)
47*4882a593Smuzhiyun return -ERANGE;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun region->offset = (16 * section) + 2;
50*4882a593Smuzhiyun region->length = 10;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun return 0;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun static const struct mtd_ooblayout_ops bwjx08k_ooblayout = {
56*4882a593Smuzhiyun .ecc = bwjx08k_ooblayout_ecc,
57*4882a593Smuzhiyun .free = bwjx08k_ooblayout_free,
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun
bwjx08k_ecc_get_status(struct spinand_device * spinand,u8 status)60*4882a593Smuzhiyun static int bwjx08k_ecc_get_status(struct spinand_device *spinand,
61*4882a593Smuzhiyun u8 status)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun struct nand_device *nand = spinand_to_nand(spinand);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun switch (status & STATUS_ECC_MASK) {
66*4882a593Smuzhiyun case STATUS_ECC_NO_BITFLIPS:
67*4882a593Smuzhiyun return 0;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun case STATUS_ECC_UNCOR_ERROR:
70*4882a593Smuzhiyun return -EBADMSG;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun case STATUS_ECC_HAS_BITFLIPS:
73*4882a593Smuzhiyun return 1;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun default:
76*4882a593Smuzhiyun return nanddev_get_ecc_requirements(nand)->strength;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun return -EINVAL;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* Another set for the same id[2] devices in one series */
83*4882a593Smuzhiyun static const struct spinand_info biwin_spinand_table[] = {
84*4882a593Smuzhiyun SPINAND_INFO("BWJX08K",
85*4882a593Smuzhiyun SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB3),
86*4882a593Smuzhiyun NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
87*4882a593Smuzhiyun NAND_ECCREQ(8, 512),
88*4882a593Smuzhiyun SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
89*4882a593Smuzhiyun &write_cache_variants,
90*4882a593Smuzhiyun &update_cache_variants),
91*4882a593Smuzhiyun SPINAND_HAS_QE_BIT,
92*4882a593Smuzhiyun SPINAND_ECCINFO(&bwjx08k_ooblayout,
93*4882a593Smuzhiyun bwjx08k_ecc_get_status)),
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun static const struct spinand_manufacturer_ops biwin_spinand_manuf_ops = {
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun const struct spinand_manufacturer biwin_spinand_manufacturer = {
100*4882a593Smuzhiyun .id = SPINAND_MFR_BIWIN,
101*4882a593Smuzhiyun .name = "BIWIN",
102*4882a593Smuzhiyun .chips = biwin_spinand_table,
103*4882a593Smuzhiyun .nchips = ARRAY_SIZE(biwin_spinand_table),
104*4882a593Smuzhiyun .ops = &biwin_spinand_manuf_ops,
105*4882a593Smuzhiyun };
106