1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Freescale GPMI NAND Flash Driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2008-2011 Freescale Semiconductor, Inc. 6*4882a593Smuzhiyun * Copyright 2008 Embedded Alley Solutions, Inc. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef __GPMI_NAND_GPMI_REGS_H 9*4882a593Smuzhiyun #define __GPMI_NAND_GPMI_REGS_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define HW_GPMI_CTRL0 0x00000000 12*4882a593Smuzhiyun #define HW_GPMI_CTRL0_SET 0x00000004 13*4882a593Smuzhiyun #define HW_GPMI_CTRL0_CLR 0x00000008 14*4882a593Smuzhiyun #define HW_GPMI_CTRL0_TOG 0x0000000c 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define BP_GPMI_CTRL0_COMMAND_MODE 24 17*4882a593Smuzhiyun #define BM_GPMI_CTRL0_COMMAND_MODE (3 << BP_GPMI_CTRL0_COMMAND_MODE) 18*4882a593Smuzhiyun #define BF_GPMI_CTRL0_COMMAND_MODE(v) \ 19*4882a593Smuzhiyun (((v) << BP_GPMI_CTRL0_COMMAND_MODE) & BM_GPMI_CTRL0_COMMAND_MODE) 20*4882a593Smuzhiyun #define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0 21*4882a593Smuzhiyun #define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1 22*4882a593Smuzhiyun #define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2 23*4882a593Smuzhiyun #define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define BM_GPMI_CTRL0_WORD_LENGTH (1 << 23) 26*4882a593Smuzhiyun #define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0 27*4882a593Smuzhiyun #define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* 30*4882a593Smuzhiyun * Difference in LOCK_CS between imx23 and imx28 : 31*4882a593Smuzhiyun * This bit may impact the _POWER_ consumption. So some chips 32*4882a593Smuzhiyun * do not set it. 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun #define MX23_BP_GPMI_CTRL0_LOCK_CS 22 35*4882a593Smuzhiyun #define MX28_BP_GPMI_CTRL0_LOCK_CS 27 36*4882a593Smuzhiyun #define LOCK_CS_ENABLE 0x1 37*4882a593Smuzhiyun #define BF_GPMI_CTRL0_LOCK_CS(v, x) 0x0 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Difference in CS between imx23 and imx28 */ 40*4882a593Smuzhiyun #define BP_GPMI_CTRL0_CS 20 41*4882a593Smuzhiyun #define MX23_BM_GPMI_CTRL0_CS (3 << BP_GPMI_CTRL0_CS) 42*4882a593Smuzhiyun #define MX28_BM_GPMI_CTRL0_CS (7 << BP_GPMI_CTRL0_CS) 43*4882a593Smuzhiyun #define BF_GPMI_CTRL0_CS(v, x) (((v) << BP_GPMI_CTRL0_CS) & \ 44*4882a593Smuzhiyun (GPMI_IS_MX23((x)) \ 45*4882a593Smuzhiyun ? MX23_BM_GPMI_CTRL0_CS \ 46*4882a593Smuzhiyun : MX28_BM_GPMI_CTRL0_CS)) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define BP_GPMI_CTRL0_ADDRESS 17 49*4882a593Smuzhiyun #define BM_GPMI_CTRL0_ADDRESS (3 << BP_GPMI_CTRL0_ADDRESS) 50*4882a593Smuzhiyun #define BF_GPMI_CTRL0_ADDRESS(v) \ 51*4882a593Smuzhiyun (((v) << BP_GPMI_CTRL0_ADDRESS) & BM_GPMI_CTRL0_ADDRESS) 52*4882a593Smuzhiyun #define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0 53*4882a593Smuzhiyun #define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1 54*4882a593Smuzhiyun #define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define BM_GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16) 57*4882a593Smuzhiyun #define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0 58*4882a593Smuzhiyun #define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define BP_GPMI_CTRL0_XFER_COUNT 0 61*4882a593Smuzhiyun #define BM_GPMI_CTRL0_XFER_COUNT (0xffff << BP_GPMI_CTRL0_XFER_COUNT) 62*4882a593Smuzhiyun #define BF_GPMI_CTRL0_XFER_COUNT(v) \ 63*4882a593Smuzhiyun (((v) << BP_GPMI_CTRL0_XFER_COUNT) & BM_GPMI_CTRL0_XFER_COUNT) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define HW_GPMI_COMPARE 0x00000010 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define HW_GPMI_ECCCTRL 0x00000020 68*4882a593Smuzhiyun #define HW_GPMI_ECCCTRL_SET 0x00000024 69*4882a593Smuzhiyun #define HW_GPMI_ECCCTRL_CLR 0x00000028 70*4882a593Smuzhiyun #define HW_GPMI_ECCCTRL_TOG 0x0000002c 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define BP_GPMI_ECCCTRL_ECC_CMD 13 73*4882a593Smuzhiyun #define BM_GPMI_ECCCTRL_ECC_CMD (3 << BP_GPMI_ECCCTRL_ECC_CMD) 74*4882a593Smuzhiyun #define BF_GPMI_ECCCTRL_ECC_CMD(v) \ 75*4882a593Smuzhiyun (((v) << BP_GPMI_ECCCTRL_ECC_CMD) & BM_GPMI_ECCCTRL_ECC_CMD) 76*4882a593Smuzhiyun #define BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE 0x0 77*4882a593Smuzhiyun #define BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE 0x1 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define BM_GPMI_ECCCTRL_ENABLE_ECC (1 << 12) 80*4882a593Smuzhiyun #define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE 0x1 81*4882a593Smuzhiyun #define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define BP_GPMI_ECCCTRL_BUFFER_MASK 0 84*4882a593Smuzhiyun #define BM_GPMI_ECCCTRL_BUFFER_MASK (0x1ff << BP_GPMI_ECCCTRL_BUFFER_MASK) 85*4882a593Smuzhiyun #define BF_GPMI_ECCCTRL_BUFFER_MASK(v) \ 86*4882a593Smuzhiyun (((v) << BP_GPMI_ECCCTRL_BUFFER_MASK) & BM_GPMI_ECCCTRL_BUFFER_MASK) 87*4882a593Smuzhiyun #define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100 88*4882a593Smuzhiyun #define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE 0x1FF 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define HW_GPMI_ECCCOUNT 0x00000030 91*4882a593Smuzhiyun #define HW_GPMI_PAYLOAD 0x00000040 92*4882a593Smuzhiyun #define HW_GPMI_AUXILIARY 0x00000050 93*4882a593Smuzhiyun #define HW_GPMI_CTRL1 0x00000060 94*4882a593Smuzhiyun #define HW_GPMI_CTRL1_SET 0x00000064 95*4882a593Smuzhiyun #define HW_GPMI_CTRL1_CLR 0x00000068 96*4882a593Smuzhiyun #define HW_GPMI_CTRL1_TOG 0x0000006c 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define BP_GPMI_CTRL1_DECOUPLE_CS 24 99*4882a593Smuzhiyun #define BM_GPMI_CTRL1_DECOUPLE_CS (1 << BP_GPMI_CTRL1_DECOUPLE_CS) 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define BP_GPMI_CTRL1_WRN_DLY_SEL 22 102*4882a593Smuzhiyun #define BM_GPMI_CTRL1_WRN_DLY_SEL (0x3 << BP_GPMI_CTRL1_WRN_DLY_SEL) 103*4882a593Smuzhiyun #define BF_GPMI_CTRL1_WRN_DLY_SEL(v) \ 104*4882a593Smuzhiyun (((v) << BP_GPMI_CTRL1_WRN_DLY_SEL) & BM_GPMI_CTRL1_WRN_DLY_SEL) 105*4882a593Smuzhiyun #define BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS 0x0 106*4882a593Smuzhiyun #define BV_GPMI_CTRL1_WRN_DLY_SEL_6_TO_10NS 0x1 107*4882a593Smuzhiyun #define BV_GPMI_CTRL1_WRN_DLY_SEL_7_TO_12NS 0x2 108*4882a593Smuzhiyun #define BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY 0x3 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #define BM_GPMI_CTRL1_BCH_MODE (1 << 18) 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define BP_GPMI_CTRL1_DLL_ENABLE 17 113*4882a593Smuzhiyun #define BM_GPMI_CTRL1_DLL_ENABLE (1 << BP_GPMI_CTRL1_DLL_ENABLE) 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define BP_GPMI_CTRL1_HALF_PERIOD 16 116*4882a593Smuzhiyun #define BM_GPMI_CTRL1_HALF_PERIOD (1 << BP_GPMI_CTRL1_HALF_PERIOD) 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #define BP_GPMI_CTRL1_RDN_DELAY 12 119*4882a593Smuzhiyun #define BM_GPMI_CTRL1_RDN_DELAY (0xf << BP_GPMI_CTRL1_RDN_DELAY) 120*4882a593Smuzhiyun #define BF_GPMI_CTRL1_RDN_DELAY(v) \ 121*4882a593Smuzhiyun (((v) << BP_GPMI_CTRL1_RDN_DELAY) & BM_GPMI_CTRL1_RDN_DELAY) 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #define BM_GPMI_CTRL1_DEV_RESET (1 << 3) 124*4882a593Smuzhiyun #define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0 125*4882a593Smuzhiyun #define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2) 128*4882a593Smuzhiyun #define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0 129*4882a593Smuzhiyun #define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #define BM_GPMI_CTRL1_CAMERA_MODE (1 << 1) 132*4882a593Smuzhiyun #define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0 133*4882a593Smuzhiyun #define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #define BM_GPMI_CTRL1_GPMI_MODE (1 << 0) 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun #define BM_GPMI_CTRL1_CLEAR_MASK (BM_GPMI_CTRL1_WRN_DLY_SEL | \ 138*4882a593Smuzhiyun BM_GPMI_CTRL1_DLL_ENABLE | \ 139*4882a593Smuzhiyun BM_GPMI_CTRL1_RDN_DELAY | \ 140*4882a593Smuzhiyun BM_GPMI_CTRL1_HALF_PERIOD) 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun #define HW_GPMI_TIMING0 0x00000070 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun #define BP_GPMI_TIMING0_ADDRESS_SETUP 16 145*4882a593Smuzhiyun #define BM_GPMI_TIMING0_ADDRESS_SETUP (0xff << BP_GPMI_TIMING0_ADDRESS_SETUP) 146*4882a593Smuzhiyun #define BF_GPMI_TIMING0_ADDRESS_SETUP(v) \ 147*4882a593Smuzhiyun (((v) << BP_GPMI_TIMING0_ADDRESS_SETUP) & BM_GPMI_TIMING0_ADDRESS_SETUP) 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun #define BP_GPMI_TIMING0_DATA_HOLD 8 150*4882a593Smuzhiyun #define BM_GPMI_TIMING0_DATA_HOLD (0xff << BP_GPMI_TIMING0_DATA_HOLD) 151*4882a593Smuzhiyun #define BF_GPMI_TIMING0_DATA_HOLD(v) \ 152*4882a593Smuzhiyun (((v) << BP_GPMI_TIMING0_DATA_HOLD) & BM_GPMI_TIMING0_DATA_HOLD) 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun #define BP_GPMI_TIMING0_DATA_SETUP 0 155*4882a593Smuzhiyun #define BM_GPMI_TIMING0_DATA_SETUP (0xff << BP_GPMI_TIMING0_DATA_SETUP) 156*4882a593Smuzhiyun #define BF_GPMI_TIMING0_DATA_SETUP(v) \ 157*4882a593Smuzhiyun (((v) << BP_GPMI_TIMING0_DATA_SETUP) & BM_GPMI_TIMING0_DATA_SETUP) 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun #define HW_GPMI_TIMING1 0x00000080 160*4882a593Smuzhiyun #define BP_GPMI_TIMING1_BUSY_TIMEOUT 16 161*4882a593Smuzhiyun #define BM_GPMI_TIMING1_BUSY_TIMEOUT (0xffff << BP_GPMI_TIMING1_BUSY_TIMEOUT) 162*4882a593Smuzhiyun #define BF_GPMI_TIMING1_BUSY_TIMEOUT(v) \ 163*4882a593Smuzhiyun (((v) << BP_GPMI_TIMING1_BUSY_TIMEOUT) & BM_GPMI_TIMING1_BUSY_TIMEOUT) 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun #define HW_GPMI_TIMING2 0x00000090 166*4882a593Smuzhiyun #define HW_GPMI_DATA 0x000000a0 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun /* MX28 uses this to detect READY. */ 169*4882a593Smuzhiyun #define HW_GPMI_STAT 0x000000b0 170*4882a593Smuzhiyun #define MX28_BP_GPMI_STAT_READY_BUSY 24 171*4882a593Smuzhiyun #define MX28_BM_GPMI_STAT_READY_BUSY (0xff << MX28_BP_GPMI_STAT_READY_BUSY) 172*4882a593Smuzhiyun #define MX28_BF_GPMI_STAT_READY_BUSY(v) \ 173*4882a593Smuzhiyun (((v) << MX28_BP_GPMI_STAT_READY_BUSY) & MX28_BM_GPMI_STAT_READY_BUSY) 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun /* MX23 uses this to detect READY. */ 176*4882a593Smuzhiyun #define HW_GPMI_DEBUG 0x000000c0 177*4882a593Smuzhiyun #define MX23_BP_GPMI_DEBUG_READY0 28 178*4882a593Smuzhiyun #define MX23_BM_GPMI_DEBUG_READY0 (1 << MX23_BP_GPMI_DEBUG_READY0) 179*4882a593Smuzhiyun #endif 180