1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2015 Simon Arlott
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Derived from bcm63138_nand.c:
6*4882a593Smuzhiyun * Copyright © 2015 Broadcom Corporation
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Derived from bcm963xx_4.12L.06B_consumer/shared/opensource/include/bcm963xx/63268_map_part.h:
9*4882a593Smuzhiyun * Copyright 2000-2010 Broadcom Corporation
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * Derived from bcm963xx_4.12L.06B_consumer/shared/opensource/flash/nandflash.c:
12*4882a593Smuzhiyun * Copyright 2000-2010 Broadcom Corporation
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <linux/device.h>
16*4882a593Smuzhiyun #include <linux/io.h>
17*4882a593Smuzhiyun #include <linux/ioport.h>
18*4882a593Smuzhiyun #include <linux/module.h>
19*4882a593Smuzhiyun #include <linux/of.h>
20*4882a593Smuzhiyun #include <linux/of_address.h>
21*4882a593Smuzhiyun #include <linux/platform_device.h>
22*4882a593Smuzhiyun #include <linux/slab.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #include "brcmnand.h"
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun struct bcm6368_nand_soc {
27*4882a593Smuzhiyun struct brcmnand_soc soc;
28*4882a593Smuzhiyun void __iomem *base;
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define BCM6368_NAND_INT 0x00
32*4882a593Smuzhiyun #define BCM6368_NAND_STATUS_SHIFT 0
33*4882a593Smuzhiyun #define BCM6368_NAND_STATUS_MASK (0xfff << BCM6368_NAND_STATUS_SHIFT)
34*4882a593Smuzhiyun #define BCM6368_NAND_ENABLE_SHIFT 16
35*4882a593Smuzhiyun #define BCM6368_NAND_ENABLE_MASK (0xffff << BCM6368_NAND_ENABLE_SHIFT)
36*4882a593Smuzhiyun #define BCM6368_NAND_BASE_ADDR0 0x04
37*4882a593Smuzhiyun #define BCM6368_NAND_BASE_ADDR1 0x0c
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun enum {
40*4882a593Smuzhiyun BCM6368_NP_READ = BIT(0),
41*4882a593Smuzhiyun BCM6368_BLOCK_ERASE = BIT(1),
42*4882a593Smuzhiyun BCM6368_COPY_BACK = BIT(2),
43*4882a593Smuzhiyun BCM6368_PAGE_PGM = BIT(3),
44*4882a593Smuzhiyun BCM6368_CTRL_READY = BIT(4),
45*4882a593Smuzhiyun BCM6368_DEV_RBPIN = BIT(5),
46*4882a593Smuzhiyun BCM6368_ECC_ERR_UNC = BIT(6),
47*4882a593Smuzhiyun BCM6368_ECC_ERR_CORR = BIT(7),
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
bcm6368_nand_intc_ack(struct brcmnand_soc * soc)50*4882a593Smuzhiyun static bool bcm6368_nand_intc_ack(struct brcmnand_soc *soc)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun struct bcm6368_nand_soc *priv =
53*4882a593Smuzhiyun container_of(soc, struct bcm6368_nand_soc, soc);
54*4882a593Smuzhiyun void __iomem *mmio = priv->base + BCM6368_NAND_INT;
55*4882a593Smuzhiyun u32 val = brcmnand_readl(mmio);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun if (val & (BCM6368_CTRL_READY << BCM6368_NAND_STATUS_SHIFT)) {
58*4882a593Smuzhiyun /* Ack interrupt */
59*4882a593Smuzhiyun val &= ~BCM6368_NAND_STATUS_MASK;
60*4882a593Smuzhiyun val |= BCM6368_CTRL_READY << BCM6368_NAND_STATUS_SHIFT;
61*4882a593Smuzhiyun brcmnand_writel(val, mmio);
62*4882a593Smuzhiyun return true;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun return false;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
bcm6368_nand_intc_set(struct brcmnand_soc * soc,bool en)68*4882a593Smuzhiyun static void bcm6368_nand_intc_set(struct brcmnand_soc *soc, bool en)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun struct bcm6368_nand_soc *priv =
71*4882a593Smuzhiyun container_of(soc, struct bcm6368_nand_soc, soc);
72*4882a593Smuzhiyun void __iomem *mmio = priv->base + BCM6368_NAND_INT;
73*4882a593Smuzhiyun u32 val = brcmnand_readl(mmio);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* Don't ack any interrupts */
76*4882a593Smuzhiyun val &= ~BCM6368_NAND_STATUS_MASK;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun if (en)
79*4882a593Smuzhiyun val |= BCM6368_CTRL_READY << BCM6368_NAND_ENABLE_SHIFT;
80*4882a593Smuzhiyun else
81*4882a593Smuzhiyun val &= ~(BCM6368_CTRL_READY << BCM6368_NAND_ENABLE_SHIFT);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun brcmnand_writel(val, mmio);
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
bcm6368_nand_probe(struct platform_device * pdev)86*4882a593Smuzhiyun static int bcm6368_nand_probe(struct platform_device *pdev)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun struct device *dev = &pdev->dev;
89*4882a593Smuzhiyun struct bcm6368_nand_soc *priv;
90*4882a593Smuzhiyun struct brcmnand_soc *soc;
91*4882a593Smuzhiyun struct resource *res;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
94*4882a593Smuzhiyun if (!priv)
95*4882a593Smuzhiyun return -ENOMEM;
96*4882a593Smuzhiyun soc = &priv->soc;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun res = platform_get_resource_byname(pdev,
99*4882a593Smuzhiyun IORESOURCE_MEM, "nand-int-base");
100*4882a593Smuzhiyun priv->base = devm_ioremap_resource(dev, res);
101*4882a593Smuzhiyun if (IS_ERR(priv->base))
102*4882a593Smuzhiyun return PTR_ERR(priv->base);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun soc->ctlrdy_ack = bcm6368_nand_intc_ack;
105*4882a593Smuzhiyun soc->ctlrdy_set_enabled = bcm6368_nand_intc_set;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* Disable and ack all interrupts */
108*4882a593Smuzhiyun brcmnand_writel(0, priv->base + BCM6368_NAND_INT);
109*4882a593Smuzhiyun brcmnand_writel(BCM6368_NAND_STATUS_MASK,
110*4882a593Smuzhiyun priv->base + BCM6368_NAND_INT);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun return brcmnand_probe(pdev, soc);
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun static const struct of_device_id bcm6368_nand_of_match[] = {
116*4882a593Smuzhiyun { .compatible = "brcm,nand-bcm6368" },
117*4882a593Smuzhiyun {},
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, bcm6368_nand_of_match);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun static struct platform_driver bcm6368_nand_driver = {
122*4882a593Smuzhiyun .probe = bcm6368_nand_probe,
123*4882a593Smuzhiyun .remove = brcmnand_remove,
124*4882a593Smuzhiyun .driver = {
125*4882a593Smuzhiyun .name = "bcm6368_nand",
126*4882a593Smuzhiyun .pm = &brcmnand_pm_ops,
127*4882a593Smuzhiyun .of_match_table = bcm6368_nand_of_match,
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun };
130*4882a593Smuzhiyun module_platform_driver(bcm6368_nand_driver);
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun MODULE_LICENSE("GPL");
133*4882a593Smuzhiyun MODULE_AUTHOR("Simon Arlott");
134*4882a593Smuzhiyun MODULE_DESCRIPTION("NAND driver for BCM6368");
135