1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2008-2010 Samsung Electronics 4*4882a593Smuzhiyun * Kyungmin Park <kyungmin.park@samsung.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef __SAMSUNG_ONENAND_H__ 7*4882a593Smuzhiyun #define __SAMSUNG_ONENAND_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* 10*4882a593Smuzhiyun * OneNAND Controller 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun #define MEM_CFG_OFFSET 0x0000 13*4882a593Smuzhiyun #define BURST_LEN_OFFSET 0x0010 14*4882a593Smuzhiyun #define MEM_RESET_OFFSET 0x0020 15*4882a593Smuzhiyun #define INT_ERR_STAT_OFFSET 0x0030 16*4882a593Smuzhiyun #define INT_ERR_MASK_OFFSET 0x0040 17*4882a593Smuzhiyun #define INT_ERR_ACK_OFFSET 0x0050 18*4882a593Smuzhiyun #define ECC_ERR_STAT_OFFSET 0x0060 19*4882a593Smuzhiyun #define MANUFACT_ID_OFFSET 0x0070 20*4882a593Smuzhiyun #define DEVICE_ID_OFFSET 0x0080 21*4882a593Smuzhiyun #define DATA_BUF_SIZE_OFFSET 0x0090 22*4882a593Smuzhiyun #define BOOT_BUF_SIZE_OFFSET 0x00A0 23*4882a593Smuzhiyun #define BUF_AMOUNT_OFFSET 0x00B0 24*4882a593Smuzhiyun #define TECH_OFFSET 0x00C0 25*4882a593Smuzhiyun #define FBA_WIDTH_OFFSET 0x00D0 26*4882a593Smuzhiyun #define FPA_WIDTH_OFFSET 0x00E0 27*4882a593Smuzhiyun #define FSA_WIDTH_OFFSET 0x00F0 28*4882a593Smuzhiyun #define TRANS_SPARE_OFFSET 0x0140 29*4882a593Smuzhiyun #define DBS_DFS_WIDTH_OFFSET 0x0160 30*4882a593Smuzhiyun #define INT_PIN_ENABLE_OFFSET 0x01A0 31*4882a593Smuzhiyun #define ACC_CLOCK_OFFSET 0x01C0 32*4882a593Smuzhiyun #define FLASH_VER_ID_OFFSET 0x01F0 33*4882a593Smuzhiyun #define FLASH_AUX_CNTRL_OFFSET 0x0300 /* s3c64xx only */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define ONENAND_MEM_RESET_HOT 0x3 36*4882a593Smuzhiyun #define ONENAND_MEM_RESET_COLD 0x2 37*4882a593Smuzhiyun #define ONENAND_MEM_RESET_WARM 0x1 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define CACHE_OP_ERR (1 << 13) 40*4882a593Smuzhiyun #define RST_CMP (1 << 12) 41*4882a593Smuzhiyun #define RDY_ACT (1 << 11) 42*4882a593Smuzhiyun #define INT_ACT (1 << 10) 43*4882a593Smuzhiyun #define UNSUP_CMD (1 << 9) 44*4882a593Smuzhiyun #define LOCKED_BLK (1 << 8) 45*4882a593Smuzhiyun #define BLK_RW_CMP (1 << 7) 46*4882a593Smuzhiyun #define ERS_CMP (1 << 6) 47*4882a593Smuzhiyun #define PGM_CMP (1 << 5) 48*4882a593Smuzhiyun #define LOAD_CMP (1 << 4) 49*4882a593Smuzhiyun #define ERS_FAIL (1 << 3) 50*4882a593Smuzhiyun #define PGM_FAIL (1 << 2) 51*4882a593Smuzhiyun #define INT_TO (1 << 1) 52*4882a593Smuzhiyun #define LD_FAIL_ECC_ERR (1 << 0) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define TSRF (1 << 0) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #endif 57