1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyunmenuconfig MTD_ONENAND 3*4882a593Smuzhiyun tristate "OneNAND Device Support" 4*4882a593Smuzhiyun depends on HAS_IOMEM 5*4882a593Smuzhiyun help 6*4882a593Smuzhiyun This enables support for accessing all type of OneNAND flash 7*4882a593Smuzhiyun devices. 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunif MTD_ONENAND 10*4882a593Smuzhiyun 11*4882a593Smuzhiyunconfig MTD_ONENAND_VERIFY_WRITE 12*4882a593Smuzhiyun bool "Verify OneNAND page writes" 13*4882a593Smuzhiyun help 14*4882a593Smuzhiyun This adds an extra check when data is written to the flash. The 15*4882a593Smuzhiyun OneNAND flash device internally checks only bits transitioning 16*4882a593Smuzhiyun from 1 to 0. There is a rare possibility that even though the 17*4882a593Smuzhiyun device thinks the write was successful, a bit could have been 18*4882a593Smuzhiyun flipped accidentally due to device wear or something else. 19*4882a593Smuzhiyun 20*4882a593Smuzhiyunconfig MTD_ONENAND_GENERIC 21*4882a593Smuzhiyun tristate "OneNAND Flash device via platform device driver" 22*4882a593Smuzhiyun help 23*4882a593Smuzhiyun Support for OneNAND flash via platform device driver. 24*4882a593Smuzhiyun 25*4882a593Smuzhiyunconfig MTD_ONENAND_OMAP2 26*4882a593Smuzhiyun tristate "OneNAND on OMAP2/OMAP3 support" 27*4882a593Smuzhiyun depends on ARCH_OMAP2 || ARCH_OMAP3 || (COMPILE_TEST && ARM) 28*4882a593Smuzhiyun depends on OF || COMPILE_TEST 29*4882a593Smuzhiyun help 30*4882a593Smuzhiyun Support for a OneNAND flash device connected to an OMAP2/OMAP3 SoC 31*4882a593Smuzhiyun via the GPMC memory controller. 32*4882a593Smuzhiyun Enable dmaengine and gpiolib for better performance. 33*4882a593Smuzhiyun 34*4882a593Smuzhiyunconfig MTD_ONENAND_SAMSUNG 35*4882a593Smuzhiyun tristate "OneNAND on Samsung SOC controller support" 36*4882a593Smuzhiyun depends on ARCH_S3C64XX || ARCH_S5PV210 || ARCH_EXYNOS4 || COMPILE_TEST 37*4882a593Smuzhiyun help 38*4882a593Smuzhiyun Support for a OneNAND flash device connected to an Samsung SOC. 39*4882a593Smuzhiyun S3C64XX uses command mapping method. 40*4882a593Smuzhiyun S5PC110/S5PC210 use generic OneNAND method. 41*4882a593Smuzhiyun 42*4882a593Smuzhiyunconfig MTD_ONENAND_OTP 43*4882a593Smuzhiyun bool "OneNAND OTP Support" 44*4882a593Smuzhiyun help 45*4882a593Smuzhiyun One Block of the NAND Flash Array memory is reserved as 46*4882a593Smuzhiyun a One-Time Programmable Block memory area. 47*4882a593Smuzhiyun Also, 1st Block of NAND Flash Array can be used as OTP. 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun The OTP block can be read, programmed and locked using the same 50*4882a593Smuzhiyun operations as any other NAND Flash Array memory block. 51*4882a593Smuzhiyun OTP block cannot be erased. 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun OTP block is fully-guaranteed to be a valid block. 54*4882a593Smuzhiyun 55*4882a593Smuzhiyunconfig MTD_ONENAND_2X_PROGRAM 56*4882a593Smuzhiyun bool "OneNAND 2X program support" 57*4882a593Smuzhiyun help 58*4882a593Smuzhiyun The 2X Program is an extension of Program Operation. 59*4882a593Smuzhiyun Since the device is equipped with two DataRAMs, and two-plane NAND 60*4882a593Smuzhiyun Flash memory array, these two component enables simultaneous program 61*4882a593Smuzhiyun of 4KiB. Plane1 has only even blocks such as block0, block2, block4 62*4882a593Smuzhiyun while Plane2 has only odd blocks such as block1, block3, block5. 63*4882a593Smuzhiyun So MTD regards it as 4KiB page size and 256KiB block size 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun Now the following chips support it. (KFXXX16Q2M) 66*4882a593Smuzhiyun Demux: KFG2G16Q2M, KFH4G16Q2M, KFW8G16Q2M, 67*4882a593Smuzhiyun Mux: KFM2G16Q2M, KFN4G16Q2M, 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun And more recent chips 70*4882a593Smuzhiyun 71*4882a593Smuzhiyunendif # MTD_ONENAND 72