1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * BIOS Flash chip on Intel 440GX board.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Bugs this currently does not work under linuxBIOS.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/pci.h>
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun #include <linux/mtd/mtd.h>
14*4882a593Smuzhiyun #include <linux/mtd/map.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define PIIXE_IOBASE_RESOURCE 11
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define WINDOW_ADDR 0xfff00000
19*4882a593Smuzhiyun #define WINDOW_SIZE 0x00100000
20*4882a593Smuzhiyun #define BUSWIDTH 1
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun static u32 iobase;
23*4882a593Smuzhiyun #define IOBASE iobase
24*4882a593Smuzhiyun #define TRIBUF_PORT (IOBASE+0x37)
25*4882a593Smuzhiyun #define VPP_PORT (IOBASE+0x28)
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun static struct mtd_info *mymtd;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* Is this really the vpp port? */
31*4882a593Smuzhiyun static DEFINE_SPINLOCK(l440gx_vpp_lock);
32*4882a593Smuzhiyun static int l440gx_vpp_refcnt;
l440gx_set_vpp(struct map_info * map,int vpp)33*4882a593Smuzhiyun static void l440gx_set_vpp(struct map_info *map, int vpp)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun unsigned long flags;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun spin_lock_irqsave(&l440gx_vpp_lock, flags);
38*4882a593Smuzhiyun if (vpp) {
39*4882a593Smuzhiyun if (++l440gx_vpp_refcnt == 1) /* first nested 'on' */
40*4882a593Smuzhiyun outl(inl(VPP_PORT) | 1, VPP_PORT);
41*4882a593Smuzhiyun } else {
42*4882a593Smuzhiyun if (--l440gx_vpp_refcnt == 0) /* last nested 'off' */
43*4882a593Smuzhiyun outl(inl(VPP_PORT) & ~1, VPP_PORT);
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun spin_unlock_irqrestore(&l440gx_vpp_lock, flags);
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun static struct map_info l440gx_map = {
49*4882a593Smuzhiyun .name = "L440GX BIOS",
50*4882a593Smuzhiyun .size = WINDOW_SIZE,
51*4882a593Smuzhiyun .bankwidth = BUSWIDTH,
52*4882a593Smuzhiyun .phys = WINDOW_ADDR,
53*4882a593Smuzhiyun #if 0
54*4882a593Smuzhiyun /* FIXME verify that this is the
55*4882a593Smuzhiyun * appripriate code for vpp enable/disable
56*4882a593Smuzhiyun */
57*4882a593Smuzhiyun .set_vpp = l440gx_set_vpp
58*4882a593Smuzhiyun #endif
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun
init_l440gx(void)61*4882a593Smuzhiyun static int __init init_l440gx(void)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun struct pci_dev *dev, *pm_dev;
64*4882a593Smuzhiyun struct resource *pm_iobase;
65*4882a593Smuzhiyun __u16 word;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun dev = pci_get_device(PCI_VENDOR_ID_INTEL,
68*4882a593Smuzhiyun PCI_DEVICE_ID_INTEL_82371AB_0, NULL);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun pm_dev = pci_get_device(PCI_VENDOR_ID_INTEL,
71*4882a593Smuzhiyun PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun pci_dev_put(dev);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun if (!dev || !pm_dev) {
76*4882a593Smuzhiyun printk(KERN_NOTICE "L440GX flash mapping: failed to find PIIX4 ISA bridge, cannot continue\n");
77*4882a593Smuzhiyun pci_dev_put(pm_dev);
78*4882a593Smuzhiyun return -ENODEV;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun l440gx_map.virt = ioremap(WINDOW_ADDR, WINDOW_SIZE);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun if (!l440gx_map.virt) {
84*4882a593Smuzhiyun printk(KERN_WARNING "Failed to ioremap L440GX flash region\n");
85*4882a593Smuzhiyun pci_dev_put(pm_dev);
86*4882a593Smuzhiyun return -ENOMEM;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun simple_map_init(&l440gx_map);
89*4882a593Smuzhiyun pr_debug("window_addr = %p\n", l440gx_map.virt);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun /* Setup the pm iobase resource
92*4882a593Smuzhiyun * This code should move into some kind of generic bridge
93*4882a593Smuzhiyun * driver but for the moment I'm content with getting the
94*4882a593Smuzhiyun * allocation correct.
95*4882a593Smuzhiyun */
96*4882a593Smuzhiyun pm_iobase = &pm_dev->resource[PIIXE_IOBASE_RESOURCE];
97*4882a593Smuzhiyun if (!(pm_iobase->flags & IORESOURCE_IO)) {
98*4882a593Smuzhiyun pm_iobase->name = "pm iobase";
99*4882a593Smuzhiyun pm_iobase->start = 0;
100*4882a593Smuzhiyun pm_iobase->end = 63;
101*4882a593Smuzhiyun pm_iobase->flags = IORESOURCE_IO;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /* Put the current value in the resource */
104*4882a593Smuzhiyun pci_read_config_dword(pm_dev, 0x40, &iobase);
105*4882a593Smuzhiyun iobase &= ~1;
106*4882a593Smuzhiyun pm_iobase->start += iobase & ~1;
107*4882a593Smuzhiyun pm_iobase->end += iobase & ~1;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun pci_dev_put(pm_dev);
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* Allocate the resource region */
112*4882a593Smuzhiyun if (pci_assign_resource(pm_dev, PIIXE_IOBASE_RESOURCE) != 0) {
113*4882a593Smuzhiyun pci_dev_put(dev);
114*4882a593Smuzhiyun pci_dev_put(pm_dev);
115*4882a593Smuzhiyun printk(KERN_WARNING "Could not allocate pm iobase resource\n");
116*4882a593Smuzhiyun iounmap(l440gx_map.virt);
117*4882a593Smuzhiyun return -ENXIO;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun /* Set the iobase */
121*4882a593Smuzhiyun iobase = pm_iobase->start;
122*4882a593Smuzhiyun pci_write_config_dword(pm_dev, 0x40, iobase | 1);
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun /* Set XBCS# */
126*4882a593Smuzhiyun pci_read_config_word(dev, 0x4e, &word);
127*4882a593Smuzhiyun word |= 0x4;
128*4882a593Smuzhiyun pci_write_config_word(dev, 0x4e, word);
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun /* Supply write voltage to the chip */
131*4882a593Smuzhiyun l440gx_set_vpp(&l440gx_map, 1);
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun /* Enable the gate on the WE line */
134*4882a593Smuzhiyun outb(inb(TRIBUF_PORT) & ~1, TRIBUF_PORT);
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun printk(KERN_NOTICE "Enabled WE line to L440GX BIOS flash chip.\n");
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun mymtd = do_map_probe("jedec_probe", &l440gx_map);
139*4882a593Smuzhiyun if (!mymtd) {
140*4882a593Smuzhiyun printk(KERN_NOTICE "JEDEC probe on BIOS chip failed. Using ROM\n");
141*4882a593Smuzhiyun mymtd = do_map_probe("map_rom", &l440gx_map);
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun if (mymtd) {
144*4882a593Smuzhiyun mymtd->owner = THIS_MODULE;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun mtd_device_register(mymtd, NULL, 0);
147*4882a593Smuzhiyun return 0;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun iounmap(l440gx_map.virt);
151*4882a593Smuzhiyun return -ENXIO;
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun
cleanup_l440gx(void)154*4882a593Smuzhiyun static void __exit cleanup_l440gx(void)
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun mtd_device_unregister(mymtd);
157*4882a593Smuzhiyun map_destroy(mymtd);
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun iounmap(l440gx_map.virt);
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun module_init(init_l440gx);
163*4882a593Smuzhiyun module_exit(cleanup_l440gx);
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun MODULE_LICENSE("GPL");
166*4882a593Smuzhiyun MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
167*4882a593Smuzhiyun MODULE_DESCRIPTION("MTD map driver for BIOS chips on Intel L440GX motherboards");
168