1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2001, 2003 Maciej W. Rozycki 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * DEC MS02-NV (54-20948-01) battery backed-up NVRAM module for 6*4882a593Smuzhiyun * DECstation/DECsystem 5000/2x0 and DECsystem 5900 and 5900/260 7*4882a593Smuzhiyun * systems. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/ioport.h> 11*4882a593Smuzhiyun #include <linux/mtd/mtd.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * Addresses are decoded as follows: 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * 0x000000 - 0x3fffff SRAM 17*4882a593Smuzhiyun * 0x400000 - 0x7fffff CSR 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * Within the SRAM area the following ranges are forced by the system 20*4882a593Smuzhiyun * firmware: 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * 0x000000 - 0x0003ff diagnostic area, destroyed upon a reboot 23*4882a593Smuzhiyun * 0x000400 - ENDofRAM storage area, available to operating systems 24*4882a593Smuzhiyun * 25*4882a593Smuzhiyun * but we can't really use the available area right from 0x000400 as 26*4882a593Smuzhiyun * the first word is used by the firmware as a status flag passed 27*4882a593Smuzhiyun * from an operating system. If anything but the valid data magic 28*4882a593Smuzhiyun * ID value is found, the firmware considers the SRAM clean, i.e. 29*4882a593Smuzhiyun * containing no valid data, and disables the battery resulting in 30*4882a593Smuzhiyun * data being erased as soon as power is switched off. So the choice 31*4882a593Smuzhiyun * for the start address of the user-available is 0x001000 which is 32*4882a593Smuzhiyun * nicely page aligned. The area between 0x000404 and 0x000fff may 33*4882a593Smuzhiyun * be used by the driver for own needs. 34*4882a593Smuzhiyun * 35*4882a593Smuzhiyun * The diagnostic area defines two status words to be read by an 36*4882a593Smuzhiyun * operating system, a magic ID to distinguish a MS02-NV board from 37*4882a593Smuzhiyun * anything else and a status information providing results of tests 38*4882a593Smuzhiyun * as well as the size of SRAM available, which can be 1MiB or 2MiB 39*4882a593Smuzhiyun * (that's what the firmware handles; no idea if 2MiB modules ever 40*4882a593Smuzhiyun * existed). 41*4882a593Smuzhiyun * 42*4882a593Smuzhiyun * The firmware only handles the MS02-NV board if installed in the 43*4882a593Smuzhiyun * last (15th) slot, so for any other location the status information 44*4882a593Smuzhiyun * stored in the SRAM cannot be relied upon. But from the hardware 45*4882a593Smuzhiyun * point of view there is no problem using up to 14 such boards in a 46*4882a593Smuzhiyun * system -- only the 1st slot needs to be filled with a DRAM module. 47*4882a593Smuzhiyun * The MS02-NV board is ECC-protected, like other MS02 memory boards. 48*4882a593Smuzhiyun * 49*4882a593Smuzhiyun * The state of the battery as provided by the CSR is reflected on 50*4882a593Smuzhiyun * the two onboard LEDs. When facing the battery side of the board, 51*4882a593Smuzhiyun * with the LEDs at the top left and the battery at the bottom right 52*4882a593Smuzhiyun * (i.e. looking from the back side of the system box), their meaning 53*4882a593Smuzhiyun * is as follows (the system has to be powered on): 54*4882a593Smuzhiyun * 55*4882a593Smuzhiyun * left LED battery disable status: lit = enabled 56*4882a593Smuzhiyun * right LED battery condition status: lit = OK 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* MS02-NV iomem register offsets. */ 60*4882a593Smuzhiyun #define MS02NV_CSR 0x400000 /* control & status register */ 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* MS02-NV CSR status bits. */ 63*4882a593Smuzhiyun #define MS02NV_CSR_BATT_OK 0x01 /* battery OK */ 64*4882a593Smuzhiyun #define MS02NV_CSR_BATT_OFF 0x02 /* battery disabled */ 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* MS02-NV memory offsets. */ 68*4882a593Smuzhiyun #define MS02NV_DIAG 0x0003f8 /* diagnostic status */ 69*4882a593Smuzhiyun #define MS02NV_MAGIC 0x0003fc /* MS02-NV magic ID */ 70*4882a593Smuzhiyun #define MS02NV_VALID 0x000400 /* valid data magic ID */ 71*4882a593Smuzhiyun #define MS02NV_RAM 0x001000 /* user-exposed RAM start */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* MS02-NV diagnostic status bits. */ 74*4882a593Smuzhiyun #define MS02NV_DIAG_TEST 0x01 /* SRAM test done (?) */ 75*4882a593Smuzhiyun #define MS02NV_DIAG_RO 0x02 /* SRAM r/o test done */ 76*4882a593Smuzhiyun #define MS02NV_DIAG_RW 0x04 /* SRAM r/w test done */ 77*4882a593Smuzhiyun #define MS02NV_DIAG_FAIL 0x08 /* SRAM test failed */ 78*4882a593Smuzhiyun #define MS02NV_DIAG_SIZE_MASK 0xf0 /* SRAM size mask */ 79*4882a593Smuzhiyun #define MS02NV_DIAG_SIZE_SHIFT 0x10 /* SRAM size shift (left) */ 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* MS02-NV general constants. */ 82*4882a593Smuzhiyun #define MS02NV_ID 0x03021966 /* MS02-NV magic ID value */ 83*4882a593Smuzhiyun #define MS02NV_VALID_ID 0xbd100248 /* valid data magic ID value */ 84*4882a593Smuzhiyun #define MS02NV_SLOT_SIZE 0x800000 /* size of the address space 85*4882a593Smuzhiyun decoded by the module */ 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun typedef volatile u32 ms02nv_uint; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun struct ms02nv_private { 91*4882a593Smuzhiyun struct mtd_info *next; 92*4882a593Smuzhiyun struct { 93*4882a593Smuzhiyun struct resource *module; 94*4882a593Smuzhiyun struct resource *diag_ram; 95*4882a593Smuzhiyun struct resource *user_ram; 96*4882a593Smuzhiyun struct resource *csr; 97*4882a593Smuzhiyun } resource; 98*4882a593Smuzhiyun u_char *addr; 99*4882a593Smuzhiyun size_t size; 100*4882a593Smuzhiyun u_char *uaddr; 101*4882a593Smuzhiyun }; 102