xref: /OK3568_Linux_fs/kernel/drivers/mtd/devices/mchp23k256.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * mchp23k256.c
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Driver for Microchip 23k256 SPI RAM chips
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Copyright © 2016 Andrew Lunn <andrew@lunn.ch>
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun #include <linux/device.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/mtd/mtd.h>
12*4882a593Smuzhiyun #include <linux/mtd/partitions.h>
13*4882a593Smuzhiyun #include <linux/mutex.h>
14*4882a593Smuzhiyun #include <linux/sched.h>
15*4882a593Smuzhiyun #include <linux/sizes.h>
16*4882a593Smuzhiyun #include <linux/spi/flash.h>
17*4882a593Smuzhiyun #include <linux/spi/spi.h>
18*4882a593Smuzhiyun #include <linux/of_device.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #define MAX_CMD_SIZE		4
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun struct mchp23_caps {
23*4882a593Smuzhiyun 	u8 addr_width;
24*4882a593Smuzhiyun 	unsigned int size;
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun struct mchp23k256_flash {
28*4882a593Smuzhiyun 	struct spi_device	*spi;
29*4882a593Smuzhiyun 	struct mutex		lock;
30*4882a593Smuzhiyun 	struct mtd_info		mtd;
31*4882a593Smuzhiyun 	const struct mchp23_caps	*caps;
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #define MCHP23K256_CMD_WRITE_STATUS	0x01
35*4882a593Smuzhiyun #define MCHP23K256_CMD_WRITE		0x02
36*4882a593Smuzhiyun #define MCHP23K256_CMD_READ		0x03
37*4882a593Smuzhiyun #define MCHP23K256_MODE_SEQ		BIT(6)
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #define to_mchp23k256_flash(x) container_of(x, struct mchp23k256_flash, mtd)
40*4882a593Smuzhiyun 
mchp23k256_addr2cmd(struct mchp23k256_flash * flash,unsigned int addr,u8 * cmd)41*4882a593Smuzhiyun static void mchp23k256_addr2cmd(struct mchp23k256_flash *flash,
42*4882a593Smuzhiyun 				unsigned int addr, u8 *cmd)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun 	int i;
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 	/*
47*4882a593Smuzhiyun 	 * Address is sent in big endian (MSB first) and we skip
48*4882a593Smuzhiyun 	 * the first entry of the cmd array which contains the cmd
49*4882a593Smuzhiyun 	 * opcode.
50*4882a593Smuzhiyun 	 */
51*4882a593Smuzhiyun 	for (i = flash->caps->addr_width; i > 0; i--, addr >>= 8)
52*4882a593Smuzhiyun 		cmd[i] = addr;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun 
mchp23k256_cmdsz(struct mchp23k256_flash * flash)55*4882a593Smuzhiyun static int mchp23k256_cmdsz(struct mchp23k256_flash *flash)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun 	return 1 + flash->caps->addr_width;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun 
mchp23k256_write(struct mtd_info * mtd,loff_t to,size_t len,size_t * retlen,const unsigned char * buf)60*4882a593Smuzhiyun static int mchp23k256_write(struct mtd_info *mtd, loff_t to, size_t len,
61*4882a593Smuzhiyun 			    size_t *retlen, const unsigned char *buf)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun 	struct mchp23k256_flash *flash = to_mchp23k256_flash(mtd);
64*4882a593Smuzhiyun 	struct spi_transfer transfer[2] = {};
65*4882a593Smuzhiyun 	struct spi_message message;
66*4882a593Smuzhiyun 	unsigned char command[MAX_CMD_SIZE];
67*4882a593Smuzhiyun 	int ret, cmd_len;
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	spi_message_init(&message);
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 	cmd_len = mchp23k256_cmdsz(flash);
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	command[0] = MCHP23K256_CMD_WRITE;
74*4882a593Smuzhiyun 	mchp23k256_addr2cmd(flash, to, command);
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	transfer[0].tx_buf = command;
77*4882a593Smuzhiyun 	transfer[0].len = cmd_len;
78*4882a593Smuzhiyun 	spi_message_add_tail(&transfer[0], &message);
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	transfer[1].tx_buf = buf;
81*4882a593Smuzhiyun 	transfer[1].len = len;
82*4882a593Smuzhiyun 	spi_message_add_tail(&transfer[1], &message);
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun 	mutex_lock(&flash->lock);
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	ret = spi_sync(flash->spi, &message);
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	mutex_unlock(&flash->lock);
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	if (ret)
91*4882a593Smuzhiyun 		return ret;
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	if (retlen && message.actual_length > cmd_len)
94*4882a593Smuzhiyun 		*retlen += message.actual_length - cmd_len;
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	return 0;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun 
mchp23k256_read(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,unsigned char * buf)99*4882a593Smuzhiyun static int mchp23k256_read(struct mtd_info *mtd, loff_t from, size_t len,
100*4882a593Smuzhiyun 			   size_t *retlen, unsigned char *buf)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun 	struct mchp23k256_flash *flash = to_mchp23k256_flash(mtd);
103*4882a593Smuzhiyun 	struct spi_transfer transfer[2] = {};
104*4882a593Smuzhiyun 	struct spi_message message;
105*4882a593Smuzhiyun 	unsigned char command[MAX_CMD_SIZE];
106*4882a593Smuzhiyun 	int ret, cmd_len;
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	spi_message_init(&message);
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	cmd_len = mchp23k256_cmdsz(flash);
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	memset(&transfer, 0, sizeof(transfer));
113*4882a593Smuzhiyun 	command[0] = MCHP23K256_CMD_READ;
114*4882a593Smuzhiyun 	mchp23k256_addr2cmd(flash, from, command);
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 	transfer[0].tx_buf = command;
117*4882a593Smuzhiyun 	transfer[0].len = cmd_len;
118*4882a593Smuzhiyun 	spi_message_add_tail(&transfer[0], &message);
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	transfer[1].rx_buf = buf;
121*4882a593Smuzhiyun 	transfer[1].len = len;
122*4882a593Smuzhiyun 	spi_message_add_tail(&transfer[1], &message);
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	mutex_lock(&flash->lock);
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	ret = spi_sync(flash->spi, &message);
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	mutex_unlock(&flash->lock);
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	if (ret)
131*4882a593Smuzhiyun 		return ret;
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	if (retlen && message.actual_length > cmd_len)
134*4882a593Smuzhiyun 		*retlen += message.actual_length - cmd_len;
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	return 0;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun /*
140*4882a593Smuzhiyun  * Set the device into sequential mode. This allows read/writes to the
141*4882a593Smuzhiyun  * entire SRAM in a single operation
142*4882a593Smuzhiyun  */
mchp23k256_set_mode(struct spi_device * spi)143*4882a593Smuzhiyun static int mchp23k256_set_mode(struct spi_device *spi)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun 	struct spi_transfer transfer = {};
146*4882a593Smuzhiyun 	struct spi_message message;
147*4882a593Smuzhiyun 	unsigned char command[2];
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	spi_message_init(&message);
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	command[0] = MCHP23K256_CMD_WRITE_STATUS;
152*4882a593Smuzhiyun 	command[1] = MCHP23K256_MODE_SEQ;
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	transfer.tx_buf = command;
155*4882a593Smuzhiyun 	transfer.len = sizeof(command);
156*4882a593Smuzhiyun 	spi_message_add_tail(&transfer, &message);
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	return spi_sync(spi, &message);
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun static const struct mchp23_caps mchp23k256_caps = {
162*4882a593Smuzhiyun 	.size = SZ_32K,
163*4882a593Smuzhiyun 	.addr_width = 2,
164*4882a593Smuzhiyun };
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun static const struct mchp23_caps mchp23lcv1024_caps = {
167*4882a593Smuzhiyun 	.size = SZ_128K,
168*4882a593Smuzhiyun 	.addr_width = 3,
169*4882a593Smuzhiyun };
170*4882a593Smuzhiyun 
mchp23k256_probe(struct spi_device * spi)171*4882a593Smuzhiyun static int mchp23k256_probe(struct spi_device *spi)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun 	struct mchp23k256_flash *flash;
174*4882a593Smuzhiyun 	struct flash_platform_data *data;
175*4882a593Smuzhiyun 	int err;
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	flash = devm_kzalloc(&spi->dev, sizeof(*flash), GFP_KERNEL);
178*4882a593Smuzhiyun 	if (!flash)
179*4882a593Smuzhiyun 		return -ENOMEM;
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	flash->spi = spi;
182*4882a593Smuzhiyun 	mutex_init(&flash->lock);
183*4882a593Smuzhiyun 	spi_set_drvdata(spi, flash);
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	err = mchp23k256_set_mode(spi);
186*4882a593Smuzhiyun 	if (err)
187*4882a593Smuzhiyun 		return err;
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	data = dev_get_platdata(&spi->dev);
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	flash->caps = of_device_get_match_data(&spi->dev);
192*4882a593Smuzhiyun 	if (!flash->caps)
193*4882a593Smuzhiyun 		flash->caps = &mchp23k256_caps;
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	mtd_set_of_node(&flash->mtd, spi->dev.of_node);
196*4882a593Smuzhiyun 	flash->mtd.dev.parent	= &spi->dev;
197*4882a593Smuzhiyun 	flash->mtd.type		= MTD_RAM;
198*4882a593Smuzhiyun 	flash->mtd.flags	= MTD_CAP_RAM;
199*4882a593Smuzhiyun 	flash->mtd.writesize	= 1;
200*4882a593Smuzhiyun 	flash->mtd.size		= flash->caps->size;
201*4882a593Smuzhiyun 	flash->mtd._read	= mchp23k256_read;
202*4882a593Smuzhiyun 	flash->mtd._write	= mchp23k256_write;
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	err = mtd_device_register(&flash->mtd, data ? data->parts : NULL,
205*4882a593Smuzhiyun 				  data ? data->nr_parts : 0);
206*4882a593Smuzhiyun 	if (err)
207*4882a593Smuzhiyun 		return err;
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	return 0;
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun 
mchp23k256_remove(struct spi_device * spi)212*4882a593Smuzhiyun static int mchp23k256_remove(struct spi_device *spi)
213*4882a593Smuzhiyun {
214*4882a593Smuzhiyun 	struct mchp23k256_flash *flash = spi_get_drvdata(spi);
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	return mtd_device_unregister(&flash->mtd);
217*4882a593Smuzhiyun }
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun static const struct of_device_id mchp23k256_of_table[] = {
220*4882a593Smuzhiyun 	{
221*4882a593Smuzhiyun 		.compatible = "microchip,mchp23k256",
222*4882a593Smuzhiyun 		.data = &mchp23k256_caps,
223*4882a593Smuzhiyun 	},
224*4882a593Smuzhiyun 	{
225*4882a593Smuzhiyun 		.compatible = "microchip,mchp23lcv1024",
226*4882a593Smuzhiyun 		.data = &mchp23lcv1024_caps,
227*4882a593Smuzhiyun 	},
228*4882a593Smuzhiyun 	{}
229*4882a593Smuzhiyun };
230*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, mchp23k256_of_table);
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun static struct spi_driver mchp23k256_driver = {
233*4882a593Smuzhiyun 	.driver = {
234*4882a593Smuzhiyun 		.name	= "mchp23k256",
235*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(mchp23k256_of_table),
236*4882a593Smuzhiyun 	},
237*4882a593Smuzhiyun 	.probe		= mchp23k256_probe,
238*4882a593Smuzhiyun 	.remove		= mchp23k256_remove,
239*4882a593Smuzhiyun };
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun module_spi_driver(mchp23k256_driver);
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun MODULE_DESCRIPTION("MTD SPI driver for MCHP23K256 RAM chips");
244*4882a593Smuzhiyun MODULE_AUTHOR("Andrew Lunn <andre@lunn.ch>");
245*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
246*4882a593Smuzhiyun MODULE_ALIAS("spi:mchp23k256");
247