1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef FWH_LOCK_H
3*4882a593Smuzhiyun #define FWH_LOCK_H
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun enum fwh_lock_state {
7*4882a593Smuzhiyun FWH_UNLOCKED = 0,
8*4882a593Smuzhiyun FWH_DENY_WRITE = 1,
9*4882a593Smuzhiyun FWH_IMMUTABLE = 2,
10*4882a593Smuzhiyun FWH_DENY_READ = 4,
11*4882a593Smuzhiyun };
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun struct fwh_xxlock_thunk {
14*4882a593Smuzhiyun enum fwh_lock_state val;
15*4882a593Smuzhiyun flstate_t state;
16*4882a593Smuzhiyun };
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define FWH_XXLOCK_ONEBLOCK_LOCK ((struct fwh_xxlock_thunk){ FWH_DENY_WRITE, FL_LOCKING})
20*4882a593Smuzhiyun #define FWH_XXLOCK_ONEBLOCK_UNLOCK ((struct fwh_xxlock_thunk){ FWH_UNLOCKED, FL_UNLOCKING})
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /*
23*4882a593Smuzhiyun * This locking/unlock is specific to firmware hub parts. Only one
24*4882a593Smuzhiyun * is known that supports the Intel command set. Firmware
25*4882a593Smuzhiyun * hub parts cannot be interleaved as they are on the LPC bus
26*4882a593Smuzhiyun * so this code has not been tested with interleaved chips,
27*4882a593Smuzhiyun * and will likely fail in that context.
28*4882a593Smuzhiyun */
fwh_xxlock_oneblock(struct map_info * map,struct flchip * chip,unsigned long adr,int len,void * thunk)29*4882a593Smuzhiyun static int fwh_xxlock_oneblock(struct map_info *map, struct flchip *chip,
30*4882a593Smuzhiyun unsigned long adr, int len, void *thunk)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun struct cfi_private *cfi = map->fldrv_priv;
33*4882a593Smuzhiyun struct fwh_xxlock_thunk *xxlt = (struct fwh_xxlock_thunk *)thunk;
34*4882a593Smuzhiyun int ret;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* Refuse the operation if the we cannot look behind the chip */
37*4882a593Smuzhiyun if (chip->start < 0x400000) {
38*4882a593Smuzhiyun pr_debug( "MTD %s(): chip->start: %lx wanted >= 0x400000\n",
39*4882a593Smuzhiyun __func__, chip->start );
40*4882a593Smuzhiyun return -EIO;
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun /*
43*4882a593Smuzhiyun * lock block registers:
44*4882a593Smuzhiyun * - on 64k boundariesand
45*4882a593Smuzhiyun * - bit 1 set high
46*4882a593Smuzhiyun * - block lock registers are 4MiB lower - overflow subtract (danger)
47*4882a593Smuzhiyun *
48*4882a593Smuzhiyun * The address manipulation is first done on the logical address
49*4882a593Smuzhiyun * which is 0 at the start of the chip, and then the offset of
50*4882a593Smuzhiyun * the individual chip is addted to it. Any other order a weird
51*4882a593Smuzhiyun * map offset could cause problems.
52*4882a593Smuzhiyun */
53*4882a593Smuzhiyun adr = (adr & ~0xffffUL) | 0x2;
54*4882a593Smuzhiyun adr += chip->start - 0x400000;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /*
57*4882a593Smuzhiyun * This is easy because these are writes to registers and not writes
58*4882a593Smuzhiyun * to flash memory - that means that we don't have to check status
59*4882a593Smuzhiyun * and timeout.
60*4882a593Smuzhiyun */
61*4882a593Smuzhiyun mutex_lock(&chip->mutex);
62*4882a593Smuzhiyun ret = get_chip(map, chip, adr, FL_LOCKING);
63*4882a593Smuzhiyun if (ret) {
64*4882a593Smuzhiyun mutex_unlock(&chip->mutex);
65*4882a593Smuzhiyun return ret;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun chip->oldstate = chip->state;
69*4882a593Smuzhiyun chip->state = xxlt->state;
70*4882a593Smuzhiyun map_write(map, CMD(xxlt->val), adr);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* Done and happy. */
73*4882a593Smuzhiyun chip->state = chip->oldstate;
74*4882a593Smuzhiyun put_chip(map, chip, adr);
75*4882a593Smuzhiyun mutex_unlock(&chip->mutex);
76*4882a593Smuzhiyun return 0;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun
fwh_lock_varsize(struct mtd_info * mtd,loff_t ofs,uint64_t len)80*4882a593Smuzhiyun static int fwh_lock_varsize(struct mtd_info *mtd, loff_t ofs, uint64_t len)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun int ret;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun ret = cfi_varsize_frob(mtd, fwh_xxlock_oneblock, ofs, len,
85*4882a593Smuzhiyun (void *)&FWH_XXLOCK_ONEBLOCK_LOCK);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun return ret;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun
fwh_unlock_varsize(struct mtd_info * mtd,loff_t ofs,uint64_t len)91*4882a593Smuzhiyun static int fwh_unlock_varsize(struct mtd_info *mtd, loff_t ofs, uint64_t len)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun int ret;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun ret = cfi_varsize_frob(mtd, fwh_xxlock_oneblock, ofs, len,
96*4882a593Smuzhiyun (void *)&FWH_XXLOCK_ONEBLOCK_UNLOCK);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun return ret;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
fixup_use_fwh_lock(struct mtd_info * mtd)101*4882a593Smuzhiyun static void fixup_use_fwh_lock(struct mtd_info *mtd)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun printk(KERN_NOTICE "using fwh lock/unlock method\n");
104*4882a593Smuzhiyun /* Setup for the chips with the fwh lock method */
105*4882a593Smuzhiyun mtd->_lock = fwh_lock_varsize;
106*4882a593Smuzhiyun mtd->_unlock = fwh_unlock_varsize;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun #endif /* FWH_LOCK_H */
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