xref: /OK3568_Linux_fs/kernel/drivers/mtd/chips/cfi_probe.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun    Common Flash Interface probe code.
3*4882a593Smuzhiyun    (C) 2000 Red Hat. GPL'd.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #include <linux/module.h>
7*4882a593Smuzhiyun #include <linux/types.h>
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include <asm/byteorder.h>
12*4882a593Smuzhiyun #include <linux/errno.h>
13*4882a593Smuzhiyun #include <linux/slab.h>
14*4882a593Smuzhiyun #include <linux/interrupt.h>
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #include <linux/mtd/xip.h>
17*4882a593Smuzhiyun #include <linux/mtd/map.h>
18*4882a593Smuzhiyun #include <linux/mtd/cfi.h>
19*4882a593Smuzhiyun #include <linux/mtd/gen_probe.h>
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun //#define DEBUG_CFI
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #ifdef DEBUG_CFI
24*4882a593Smuzhiyun static void print_cfi_ident(struct cfi_ident *);
25*4882a593Smuzhiyun #endif
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun static int cfi_probe_chip(struct map_info *map, __u32 base,
28*4882a593Smuzhiyun 			  unsigned long *chip_map, struct cfi_private *cfi);
29*4882a593Smuzhiyun static int cfi_chip_setup(struct map_info *map, struct cfi_private *cfi);
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun struct mtd_info *cfi_probe(struct map_info *map);
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #ifdef CONFIG_MTD_XIP
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun /* only needed for short periods, so this is rather simple */
36*4882a593Smuzhiyun #define xip_disable()	local_irq_disable()
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #define xip_allowed(base, map) \
39*4882a593Smuzhiyun do { \
40*4882a593Smuzhiyun 	(void) map_read(map, base); \
41*4882a593Smuzhiyun 	xip_iprefetch(); \
42*4882a593Smuzhiyun 	local_irq_enable(); \
43*4882a593Smuzhiyun } while (0)
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun #define xip_enable(base, map, cfi) \
46*4882a593Smuzhiyun do { \
47*4882a593Smuzhiyun 	cfi_qry_mode_off(base, map, cfi);		\
48*4882a593Smuzhiyun 	xip_allowed(base, map); \
49*4882a593Smuzhiyun } while (0)
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun #define xip_disable_qry(base, map, cfi) \
52*4882a593Smuzhiyun do { \
53*4882a593Smuzhiyun 	xip_disable(); \
54*4882a593Smuzhiyun 	cfi_qry_mode_on(base, map, cfi); \
55*4882a593Smuzhiyun } while (0)
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun #else
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun #define xip_disable()			do { } while (0)
60*4882a593Smuzhiyun #define xip_allowed(base, map)		do { } while (0)
61*4882a593Smuzhiyun #define xip_enable(base, map, cfi)	do { } while (0)
62*4882a593Smuzhiyun #define xip_disable_qry(base, map, cfi) do { } while (0)
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun #endif
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun /*
67*4882a593Smuzhiyun  * This fixup occurs immediately after reading the CFI structure and can affect
68*4882a593Smuzhiyun  * the number of chips detected, unlike cfi_fixup, which occurs after an
69*4882a593Smuzhiyun  * mtd_info structure has been created for the chip.
70*4882a593Smuzhiyun  */
71*4882a593Smuzhiyun struct cfi_early_fixup {
72*4882a593Smuzhiyun 	uint16_t mfr;
73*4882a593Smuzhiyun 	uint16_t id;
74*4882a593Smuzhiyun 	void (*fixup)(struct cfi_private *cfi);
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun 
cfi_early_fixup(struct cfi_private * cfi,const struct cfi_early_fixup * fixups)77*4882a593Smuzhiyun static void cfi_early_fixup(struct cfi_private *cfi,
78*4882a593Smuzhiyun 			    const struct cfi_early_fixup *fixups)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun 	const struct cfi_early_fixup *f;
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 	for (f = fixups; f->fixup; f++) {
83*4882a593Smuzhiyun 		if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi->mfr)) &&
84*4882a593Smuzhiyun 		    ((f->id == CFI_ID_ANY) || (f->id == cfi->id))) {
85*4882a593Smuzhiyun 			f->fixup(cfi);
86*4882a593Smuzhiyun 		}
87*4882a593Smuzhiyun 	}
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun /* check for QRY.
91*4882a593Smuzhiyun    in: interleave,type,mode
92*4882a593Smuzhiyun    ret: table index, <0 for error
93*4882a593Smuzhiyun  */
94*4882a593Smuzhiyun 
cfi_probe_chip(struct map_info * map,__u32 base,unsigned long * chip_map,struct cfi_private * cfi)95*4882a593Smuzhiyun static int __xipram cfi_probe_chip(struct map_info *map, __u32 base,
96*4882a593Smuzhiyun 				   unsigned long *chip_map, struct cfi_private *cfi)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun 	int i;
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	if ((base + 0) >= map->size) {
101*4882a593Smuzhiyun 		printk(KERN_NOTICE
102*4882a593Smuzhiyun 			"Probe at base[0x00](0x%08lx) past the end of the map(0x%08lx)\n",
103*4882a593Smuzhiyun 			(unsigned long)base, map->size -1);
104*4882a593Smuzhiyun 		return 0;
105*4882a593Smuzhiyun 	}
106*4882a593Smuzhiyun 	if ((base + 0xff) >= map->size) {
107*4882a593Smuzhiyun 		printk(KERN_NOTICE
108*4882a593Smuzhiyun 			"Probe at base[0x55](0x%08lx) past the end of the map(0x%08lx)\n",
109*4882a593Smuzhiyun 			(unsigned long)base + 0x55, map->size -1);
110*4882a593Smuzhiyun 		return 0;
111*4882a593Smuzhiyun 	}
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	xip_disable();
114*4882a593Smuzhiyun 	if (!cfi_qry_mode_on(base, map, cfi)) {
115*4882a593Smuzhiyun 		xip_enable(base, map, cfi);
116*4882a593Smuzhiyun 		return 0;
117*4882a593Smuzhiyun 	}
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	if (!cfi->numchips) {
120*4882a593Smuzhiyun 		/* This is the first time we're called. Set up the CFI
121*4882a593Smuzhiyun 		   stuff accordingly and return */
122*4882a593Smuzhiyun 		return cfi_chip_setup(map, cfi);
123*4882a593Smuzhiyun 	}
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	/* Check each previous chip to see if it's an alias */
126*4882a593Smuzhiyun  	for (i=0; i < (base >> cfi->chipshift); i++) {
127*4882a593Smuzhiyun  		unsigned long start;
128*4882a593Smuzhiyun  		if(!test_bit(i, chip_map)) {
129*4882a593Smuzhiyun 			/* Skip location; no valid chip at this address */
130*4882a593Smuzhiyun  			continue;
131*4882a593Smuzhiyun  		}
132*4882a593Smuzhiyun  		start = i << cfi->chipshift;
133*4882a593Smuzhiyun 		/* This chip should be in read mode if it's one
134*4882a593Smuzhiyun 		   we've already touched. */
135*4882a593Smuzhiyun 		if (cfi_qry_present(map, start, cfi)) {
136*4882a593Smuzhiyun 			/* Eep. This chip also had the QRY marker.
137*4882a593Smuzhiyun 			 * Is it an alias for the new one? */
138*4882a593Smuzhiyun 			cfi_qry_mode_off(start, map, cfi);
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 			/* If the QRY marker goes away, it's an alias */
141*4882a593Smuzhiyun 			if (!cfi_qry_present(map, start, cfi)) {
142*4882a593Smuzhiyun 				xip_allowed(base, map);
143*4882a593Smuzhiyun 				printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n",
144*4882a593Smuzhiyun 				       map->name, base, start);
145*4882a593Smuzhiyun 				return 0;
146*4882a593Smuzhiyun 			}
147*4882a593Smuzhiyun 			/* Yes, it's actually got QRY for data. Most
148*4882a593Smuzhiyun 			 * unfortunate. Stick the new chip in read mode
149*4882a593Smuzhiyun 			 * too and if it's the same, assume it's an alias. */
150*4882a593Smuzhiyun 			/* FIXME: Use other modes to do a proper check */
151*4882a593Smuzhiyun 			cfi_qry_mode_off(base, map, cfi);
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 			if (cfi_qry_present(map, base, cfi)) {
154*4882a593Smuzhiyun 				xip_allowed(base, map);
155*4882a593Smuzhiyun 				printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n",
156*4882a593Smuzhiyun 				       map->name, base, start);
157*4882a593Smuzhiyun 				return 0;
158*4882a593Smuzhiyun 			}
159*4882a593Smuzhiyun 		}
160*4882a593Smuzhiyun 	}
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	/* OK, if we got to here, then none of the previous chips appear to
163*4882a593Smuzhiyun 	   be aliases for the current one. */
164*4882a593Smuzhiyun 	set_bit((base >> cfi->chipshift), chip_map); /* Update chip map */
165*4882a593Smuzhiyun 	cfi->numchips++;
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	/* Put it back into Read Mode */
168*4882a593Smuzhiyun 	cfi_qry_mode_off(base, map, cfi);
169*4882a593Smuzhiyun 	xip_allowed(base, map);
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	printk(KERN_INFO "%s: Found %d x%d devices at 0x%x in %d-bit bank\n",
172*4882a593Smuzhiyun 	       map->name, cfi->interleave, cfi->device_type*8, base,
173*4882a593Smuzhiyun 	       map->bankwidth*8);
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	return 1;
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun 
fixup_s70gl02gs_chips(struct cfi_private * cfi)178*4882a593Smuzhiyun static void fixup_s70gl02gs_chips(struct cfi_private *cfi)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun 	/*
181*4882a593Smuzhiyun 	 * S70GL02GS flash reports a single 256 MiB chip, but is really made up
182*4882a593Smuzhiyun 	 * of two 128 MiB chips with 1024 sectors each.
183*4882a593Smuzhiyun 	 */
184*4882a593Smuzhiyun 	cfi->cfiq->DevSize = 27;
185*4882a593Smuzhiyun 	cfi->cfiq->EraseRegionInfo[0] = 0x20003ff;
186*4882a593Smuzhiyun 	pr_warn("Bad S70GL02GS CFI data; adjust to detect 2 chips\n");
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun static const struct cfi_early_fixup cfi_early_fixup_table[] = {
190*4882a593Smuzhiyun 	{ CFI_MFR_AMD, 0x4801, fixup_s70gl02gs_chips },
191*4882a593Smuzhiyun 	{ },
192*4882a593Smuzhiyun };
193*4882a593Smuzhiyun 
cfi_chip_setup(struct map_info * map,struct cfi_private * cfi)194*4882a593Smuzhiyun static int __xipram cfi_chip_setup(struct map_info *map,
195*4882a593Smuzhiyun 				   struct cfi_private *cfi)
196*4882a593Smuzhiyun {
197*4882a593Smuzhiyun 	int ofs_factor = cfi->interleave*cfi->device_type;
198*4882a593Smuzhiyun 	__u32 base = 0;
199*4882a593Smuzhiyun 	int num_erase_regions = cfi_read_query(map, base + (0x10 + 28)*ofs_factor);
200*4882a593Smuzhiyun 	int i;
201*4882a593Smuzhiyun 	int addr_unlock1 = 0x555, addr_unlock2 = 0x2AA;
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	xip_enable(base, map, cfi);
204*4882a593Smuzhiyun #ifdef DEBUG_CFI
205*4882a593Smuzhiyun 	printk("Number of erase regions: %d\n", num_erase_regions);
206*4882a593Smuzhiyun #endif
207*4882a593Smuzhiyun 	if (!num_erase_regions)
208*4882a593Smuzhiyun 		return 0;
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 	cfi->cfiq = kmalloc(sizeof(struct cfi_ident) + num_erase_regions * 4, GFP_KERNEL);
211*4882a593Smuzhiyun 	if (!cfi->cfiq)
212*4882a593Smuzhiyun 		return 0;
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	memset(cfi->cfiq,0,sizeof(struct cfi_ident));
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	cfi->cfi_mode = CFI_MODE_CFI;
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 	cfi->sector_erase_cmd = CMD(0x30);
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 	/* Read the CFI info structure */
221*4882a593Smuzhiyun 	xip_disable_qry(base, map, cfi);
222*4882a593Smuzhiyun 	for (i=0; i<(sizeof(struct cfi_ident) + num_erase_regions * 4); i++)
223*4882a593Smuzhiyun 		((unsigned char *)cfi->cfiq)[i] = cfi_read_query(map,base + (0x10 + i)*ofs_factor);
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 	/* Do any necessary byteswapping */
226*4882a593Smuzhiyun 	cfi->cfiq->P_ID = le16_to_cpu(cfi->cfiq->P_ID);
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 	cfi->cfiq->P_ADR = le16_to_cpu(cfi->cfiq->P_ADR);
229*4882a593Smuzhiyun 	cfi->cfiq->A_ID = le16_to_cpu(cfi->cfiq->A_ID);
230*4882a593Smuzhiyun 	cfi->cfiq->A_ADR = le16_to_cpu(cfi->cfiq->A_ADR);
231*4882a593Smuzhiyun 	cfi->cfiq->InterfaceDesc = le16_to_cpu(cfi->cfiq->InterfaceDesc);
232*4882a593Smuzhiyun 	cfi->cfiq->MaxBufWriteSize = le16_to_cpu(cfi->cfiq->MaxBufWriteSize);
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun #ifdef DEBUG_CFI
235*4882a593Smuzhiyun 	/* Dump the information therein */
236*4882a593Smuzhiyun 	print_cfi_ident(cfi->cfiq);
237*4882a593Smuzhiyun #endif
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 	for (i=0; i<cfi->cfiq->NumEraseRegions; i++) {
240*4882a593Smuzhiyun 		cfi->cfiq->EraseRegionInfo[i] = le32_to_cpu(cfi->cfiq->EraseRegionInfo[i]);
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun #ifdef DEBUG_CFI
243*4882a593Smuzhiyun 		printk("  Erase Region #%d: BlockSize 0x%4.4X bytes, %d blocks\n",
244*4882a593Smuzhiyun 		       i, (cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff,
245*4882a593Smuzhiyun 		       (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1);
246*4882a593Smuzhiyun #endif
247*4882a593Smuzhiyun 	}
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun 	if (cfi->cfiq->P_ID == P_ID_SST_OLD) {
250*4882a593Smuzhiyun 		addr_unlock1 = 0x5555;
251*4882a593Smuzhiyun 		addr_unlock2 = 0x2AAA;
252*4882a593Smuzhiyun 	}
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	/*
255*4882a593Smuzhiyun 	 * Note we put the device back into Read Mode BEFORE going into Auto
256*4882a593Smuzhiyun 	 * Select Mode, as some devices support nesting of modes, others
257*4882a593Smuzhiyun 	 * don't. This way should always work.
258*4882a593Smuzhiyun 	 * On cmdset 0001 the writes of 0xaa and 0x55 are not needed, and
259*4882a593Smuzhiyun 	 * so should be treated as nops or illegal (and so put the device
260*4882a593Smuzhiyun 	 * back into Read Mode, which is a nop in this case).
261*4882a593Smuzhiyun 	 */
262*4882a593Smuzhiyun 	cfi_send_gen_cmd(0xf0,     0, base, map, cfi, cfi->device_type, NULL);
263*4882a593Smuzhiyun 	cfi_send_gen_cmd(0xaa, addr_unlock1, base, map, cfi, cfi->device_type, NULL);
264*4882a593Smuzhiyun 	cfi_send_gen_cmd(0x55, addr_unlock2, base, map, cfi, cfi->device_type, NULL);
265*4882a593Smuzhiyun 	cfi_send_gen_cmd(0x90, addr_unlock1, base, map, cfi, cfi->device_type, NULL);
266*4882a593Smuzhiyun 	cfi->mfr = cfi_read_query16(map, base);
267*4882a593Smuzhiyun 	cfi->id = cfi_read_query16(map, base + ofs_factor);
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	/* Get AMD/Spansion extended JEDEC ID */
270*4882a593Smuzhiyun 	if (cfi->mfr == CFI_MFR_AMD && (cfi->id & 0xff) == 0x7e)
271*4882a593Smuzhiyun 		cfi->id = cfi_read_query(map, base + 0xe * ofs_factor) << 8 |
272*4882a593Smuzhiyun 			  cfi_read_query(map, base + 0xf * ofs_factor);
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun 	/* Put it back into Read Mode */
275*4882a593Smuzhiyun 	cfi_qry_mode_off(base, map, cfi);
276*4882a593Smuzhiyun 	xip_allowed(base, map);
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 	cfi_early_fixup(cfi, cfi_early_fixup_table);
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun 	printk(KERN_INFO "%s: Found %d x%d devices at 0x%x in %d-bit bank. Manufacturer ID %#08x Chip ID %#08x\n",
281*4882a593Smuzhiyun 	       map->name, cfi->interleave, cfi->device_type*8, base,
282*4882a593Smuzhiyun 	       map->bankwidth*8, cfi->mfr, cfi->id);
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun 	return 1;
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun #ifdef DEBUG_CFI
vendorname(__u16 vendor)288*4882a593Smuzhiyun static char *vendorname(__u16 vendor)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun 	switch (vendor) {
291*4882a593Smuzhiyun 	case P_ID_NONE:
292*4882a593Smuzhiyun 		return "None";
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun 	case P_ID_INTEL_EXT:
295*4882a593Smuzhiyun 		return "Intel/Sharp Extended";
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun 	case P_ID_AMD_STD:
298*4882a593Smuzhiyun 		return "AMD/Fujitsu Standard";
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 	case P_ID_INTEL_STD:
301*4882a593Smuzhiyun 		return "Intel/Sharp Standard";
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun 	case P_ID_AMD_EXT:
304*4882a593Smuzhiyun 		return "AMD/Fujitsu Extended";
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun 	case P_ID_WINBOND:
307*4882a593Smuzhiyun 		return "Winbond Standard";
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 	case P_ID_ST_ADV:
310*4882a593Smuzhiyun 		return "ST Advanced";
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	case P_ID_MITSUBISHI_STD:
313*4882a593Smuzhiyun 		return "Mitsubishi Standard";
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 	case P_ID_MITSUBISHI_EXT:
316*4882a593Smuzhiyun 		return "Mitsubishi Extended";
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun 	case P_ID_SST_PAGE:
319*4882a593Smuzhiyun 		return "SST Page Write";
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun 	case P_ID_SST_OLD:
322*4882a593Smuzhiyun 		return "SST 39VF160x/39VF320x";
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun 	case P_ID_INTEL_PERFORMANCE:
325*4882a593Smuzhiyun 		return "Intel Performance Code";
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun 	case P_ID_INTEL_DATA:
328*4882a593Smuzhiyun 		return "Intel Data";
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun 	case P_ID_RESERVED:
331*4882a593Smuzhiyun 		return "Not Allowed / Reserved for Future Use";
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun 	default:
334*4882a593Smuzhiyun 		return "Unknown";
335*4882a593Smuzhiyun 	}
336*4882a593Smuzhiyun }
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun 
print_cfi_ident(struct cfi_ident * cfip)339*4882a593Smuzhiyun static void print_cfi_ident(struct cfi_ident *cfip)
340*4882a593Smuzhiyun {
341*4882a593Smuzhiyun #if 0
342*4882a593Smuzhiyun 	if (cfip->qry[0] != 'Q' || cfip->qry[1] != 'R' || cfip->qry[2] != 'Y') {
343*4882a593Smuzhiyun 		printk("Invalid CFI ident structure.\n");
344*4882a593Smuzhiyun 		return;
345*4882a593Smuzhiyun 	}
346*4882a593Smuzhiyun #endif
347*4882a593Smuzhiyun 	printk("Primary Vendor Command Set: %4.4X (%s)\n", cfip->P_ID, vendorname(cfip->P_ID));
348*4882a593Smuzhiyun 	if (cfip->P_ADR)
349*4882a593Smuzhiyun 		printk("Primary Algorithm Table at %4.4X\n", cfip->P_ADR);
350*4882a593Smuzhiyun 	else
351*4882a593Smuzhiyun 		printk("No Primary Algorithm Table\n");
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun 	printk("Alternative Vendor Command Set: %4.4X (%s)\n", cfip->A_ID, vendorname(cfip->A_ID));
354*4882a593Smuzhiyun 	if (cfip->A_ADR)
355*4882a593Smuzhiyun 		printk("Alternate Algorithm Table at %4.4X\n", cfip->A_ADR);
356*4882a593Smuzhiyun 	else
357*4882a593Smuzhiyun 		printk("No Alternate Algorithm Table\n");
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun 	printk("Vcc Minimum: %2d.%d V\n", cfip->VccMin >> 4, cfip->VccMin & 0xf);
361*4882a593Smuzhiyun 	printk("Vcc Maximum: %2d.%d V\n", cfip->VccMax >> 4, cfip->VccMax & 0xf);
362*4882a593Smuzhiyun 	if (cfip->VppMin) {
363*4882a593Smuzhiyun 		printk("Vpp Minimum: %2d.%d V\n", cfip->VppMin >> 4, cfip->VppMin & 0xf);
364*4882a593Smuzhiyun 		printk("Vpp Maximum: %2d.%d V\n", cfip->VppMax >> 4, cfip->VppMax & 0xf);
365*4882a593Smuzhiyun 	}
366*4882a593Smuzhiyun 	else
367*4882a593Smuzhiyun 		printk("No Vpp line\n");
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun 	printk("Typical byte/word write timeout: %d µs\n", 1<<cfip->WordWriteTimeoutTyp);
370*4882a593Smuzhiyun 	printk("Maximum byte/word write timeout: %d µs\n", (1<<cfip->WordWriteTimeoutMax) * (1<<cfip->WordWriteTimeoutTyp));
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun 	if (cfip->BufWriteTimeoutTyp || cfip->BufWriteTimeoutMax) {
373*4882a593Smuzhiyun 		printk("Typical full buffer write timeout: %d µs\n", 1<<cfip->BufWriteTimeoutTyp);
374*4882a593Smuzhiyun 		printk("Maximum full buffer write timeout: %d µs\n", (1<<cfip->BufWriteTimeoutMax) * (1<<cfip->BufWriteTimeoutTyp));
375*4882a593Smuzhiyun 	}
376*4882a593Smuzhiyun 	else
377*4882a593Smuzhiyun 		printk("Full buffer write not supported\n");
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun 	printk("Typical block erase timeout: %d ms\n", 1<<cfip->BlockEraseTimeoutTyp);
380*4882a593Smuzhiyun 	printk("Maximum block erase timeout: %d ms\n", (1<<cfip->BlockEraseTimeoutMax) * (1<<cfip->BlockEraseTimeoutTyp));
381*4882a593Smuzhiyun 	if (cfip->ChipEraseTimeoutTyp || cfip->ChipEraseTimeoutMax) {
382*4882a593Smuzhiyun 		printk("Typical chip erase timeout: %d ms\n", 1<<cfip->ChipEraseTimeoutTyp);
383*4882a593Smuzhiyun 		printk("Maximum chip erase timeout: %d ms\n", (1<<cfip->ChipEraseTimeoutMax) * (1<<cfip->ChipEraseTimeoutTyp));
384*4882a593Smuzhiyun 	}
385*4882a593Smuzhiyun 	else
386*4882a593Smuzhiyun 		printk("Chip erase not supported\n");
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun 	printk("Device size: 0x%X bytes (%d MiB)\n", 1 << cfip->DevSize, 1<< (cfip->DevSize - 20));
389*4882a593Smuzhiyun 	printk("Flash Device Interface description: 0x%4.4X\n", cfip->InterfaceDesc);
390*4882a593Smuzhiyun 	switch(cfip->InterfaceDesc) {
391*4882a593Smuzhiyun 	case CFI_INTERFACE_X8_ASYNC:
392*4882a593Smuzhiyun 		printk("  - x8-only asynchronous interface\n");
393*4882a593Smuzhiyun 		break;
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun 	case CFI_INTERFACE_X16_ASYNC:
396*4882a593Smuzhiyun 		printk("  - x16-only asynchronous interface\n");
397*4882a593Smuzhiyun 		break;
398*4882a593Smuzhiyun 
399*4882a593Smuzhiyun 	case CFI_INTERFACE_X8_BY_X16_ASYNC:
400*4882a593Smuzhiyun 		printk("  - supports x8 and x16 via BYTE# with asynchronous interface\n");
401*4882a593Smuzhiyun 		break;
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun 	case CFI_INTERFACE_X32_ASYNC:
404*4882a593Smuzhiyun 		printk("  - x32-only asynchronous interface\n");
405*4882a593Smuzhiyun 		break;
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun 	case CFI_INTERFACE_X16_BY_X32_ASYNC:
408*4882a593Smuzhiyun 		printk("  - supports x16 and x32 via Word# with asynchronous interface\n");
409*4882a593Smuzhiyun 		break;
410*4882a593Smuzhiyun 
411*4882a593Smuzhiyun 	case CFI_INTERFACE_NOT_ALLOWED:
412*4882a593Smuzhiyun 		printk("  - Not Allowed / Reserved\n");
413*4882a593Smuzhiyun 		break;
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun 	default:
416*4882a593Smuzhiyun 		printk("  - Unknown\n");
417*4882a593Smuzhiyun 		break;
418*4882a593Smuzhiyun 	}
419*4882a593Smuzhiyun 
420*4882a593Smuzhiyun 	printk("Max. bytes in buffer write: 0x%x\n", 1<< cfip->MaxBufWriteSize);
421*4882a593Smuzhiyun 	printk("Number of Erase Block Regions: %d\n", cfip->NumEraseRegions);
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun }
424*4882a593Smuzhiyun #endif /* DEBUG_CFI */
425*4882a593Smuzhiyun 
426*4882a593Smuzhiyun static struct chip_probe cfi_chip_probe = {
427*4882a593Smuzhiyun 	.name		= "CFI",
428*4882a593Smuzhiyun 	.probe_chip	= cfi_probe_chip
429*4882a593Smuzhiyun };
430*4882a593Smuzhiyun 
cfi_probe(struct map_info * map)431*4882a593Smuzhiyun struct mtd_info *cfi_probe(struct map_info *map)
432*4882a593Smuzhiyun {
433*4882a593Smuzhiyun 	/*
434*4882a593Smuzhiyun 	 * Just use the generic probe stuff to call our CFI-specific
435*4882a593Smuzhiyun 	 * chip_probe routine in all the possible permutations, etc.
436*4882a593Smuzhiyun 	 */
437*4882a593Smuzhiyun 	return mtd_do_chip_probe(map, &cfi_chip_probe);
438*4882a593Smuzhiyun }
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun static struct mtd_chip_driver cfi_chipdrv = {
441*4882a593Smuzhiyun 	.probe		= cfi_probe,
442*4882a593Smuzhiyun 	.name		= "cfi_probe",
443*4882a593Smuzhiyun 	.module		= THIS_MODULE
444*4882a593Smuzhiyun };
445*4882a593Smuzhiyun 
cfi_probe_init(void)446*4882a593Smuzhiyun static int __init cfi_probe_init(void)
447*4882a593Smuzhiyun {
448*4882a593Smuzhiyun 	register_mtd_chip_driver(&cfi_chipdrv);
449*4882a593Smuzhiyun 	return 0;
450*4882a593Smuzhiyun }
451*4882a593Smuzhiyun 
cfi_probe_exit(void)452*4882a593Smuzhiyun static void __exit cfi_probe_exit(void)
453*4882a593Smuzhiyun {
454*4882a593Smuzhiyun 	unregister_mtd_chip_driver(&cfi_chipdrv);
455*4882a593Smuzhiyun }
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun module_init(cfi_probe_init);
458*4882a593Smuzhiyun module_exit(cfi_probe_exit);
459*4882a593Smuzhiyun 
460*4882a593Smuzhiyun MODULE_LICENSE("GPL");
461*4882a593Smuzhiyun MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org> et al.");
462*4882a593Smuzhiyun MODULE_DESCRIPTION("Probe code for CFI-compliant flash chips");
463