1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * linux/drivers/mmc/host/wbsd.h - Winbond W83L51xD SD/MMC driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2004-2007 Pierre Ossman, All Rights Reserved. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define LOCK_CODE 0xAA 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define WBSD_CONF_SWRST 0x02 11*4882a593Smuzhiyun #define WBSD_CONF_DEVICE 0x07 12*4882a593Smuzhiyun #define WBSD_CONF_ID_HI 0x20 13*4882a593Smuzhiyun #define WBSD_CONF_ID_LO 0x21 14*4882a593Smuzhiyun #define WBSD_CONF_POWER 0x22 15*4882a593Smuzhiyun #define WBSD_CONF_PME 0x23 16*4882a593Smuzhiyun #define WBSD_CONF_PMES 0x24 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define WBSD_CONF_ENABLE 0x30 19*4882a593Smuzhiyun #define WBSD_CONF_PORT_HI 0x60 20*4882a593Smuzhiyun #define WBSD_CONF_PORT_LO 0x61 21*4882a593Smuzhiyun #define WBSD_CONF_IRQ 0x70 22*4882a593Smuzhiyun #define WBSD_CONF_DRQ 0x74 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define WBSD_CONF_PINS 0xF0 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define DEVICE_SD 0x03 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define WBSD_PINS_DAT3_HI 0x20 29*4882a593Smuzhiyun #define WBSD_PINS_DAT3_OUT 0x10 30*4882a593Smuzhiyun #define WBSD_PINS_GP11_HI 0x04 31*4882a593Smuzhiyun #define WBSD_PINS_DETECT_GP11 0x02 32*4882a593Smuzhiyun #define WBSD_PINS_DETECT_DAT3 0x01 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define WBSD_CMDR 0x00 35*4882a593Smuzhiyun #define WBSD_DFR 0x01 36*4882a593Smuzhiyun #define WBSD_EIR 0x02 37*4882a593Smuzhiyun #define WBSD_ISR 0x03 38*4882a593Smuzhiyun #define WBSD_FSR 0x04 39*4882a593Smuzhiyun #define WBSD_IDXR 0x05 40*4882a593Smuzhiyun #define WBSD_DATAR 0x06 41*4882a593Smuzhiyun #define WBSD_CSR 0x07 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define WBSD_EINT_CARD 0x40 44*4882a593Smuzhiyun #define WBSD_EINT_FIFO_THRE 0x20 45*4882a593Smuzhiyun #define WBSD_EINT_CRC 0x10 46*4882a593Smuzhiyun #define WBSD_EINT_TIMEOUT 0x08 47*4882a593Smuzhiyun #define WBSD_EINT_PROGEND 0x04 48*4882a593Smuzhiyun #define WBSD_EINT_BUSYEND 0x02 49*4882a593Smuzhiyun #define WBSD_EINT_TC 0x01 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define WBSD_INT_PENDING 0x80 52*4882a593Smuzhiyun #define WBSD_INT_CARD 0x40 53*4882a593Smuzhiyun #define WBSD_INT_FIFO_THRE 0x20 54*4882a593Smuzhiyun #define WBSD_INT_CRC 0x10 55*4882a593Smuzhiyun #define WBSD_INT_TIMEOUT 0x08 56*4882a593Smuzhiyun #define WBSD_INT_PROGEND 0x04 57*4882a593Smuzhiyun #define WBSD_INT_BUSYEND 0x02 58*4882a593Smuzhiyun #define WBSD_INT_TC 0x01 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define WBSD_FIFO_EMPTY 0x80 61*4882a593Smuzhiyun #define WBSD_FIFO_FULL 0x40 62*4882a593Smuzhiyun #define WBSD_FIFO_EMTHRE 0x20 63*4882a593Smuzhiyun #define WBSD_FIFO_FUTHRE 0x10 64*4882a593Smuzhiyun #define WBSD_FIFO_SZMASK 0x0F 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define WBSD_MSLED 0x20 67*4882a593Smuzhiyun #define WBSD_POWER_N 0x10 68*4882a593Smuzhiyun #define WBSD_WRPT 0x04 69*4882a593Smuzhiyun #define WBSD_CARDPRESENT 0x01 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define WBSD_IDX_CLK 0x01 72*4882a593Smuzhiyun #define WBSD_IDX_PBSMSB 0x02 73*4882a593Smuzhiyun #define WBSD_IDX_TAAC 0x03 74*4882a593Smuzhiyun #define WBSD_IDX_NSAC 0x04 75*4882a593Smuzhiyun #define WBSD_IDX_PBSLSB 0x05 76*4882a593Smuzhiyun #define WBSD_IDX_SETUP 0x06 77*4882a593Smuzhiyun #define WBSD_IDX_DMA 0x07 78*4882a593Smuzhiyun #define WBSD_IDX_FIFOEN 0x08 79*4882a593Smuzhiyun #define WBSD_IDX_STATUS 0x10 80*4882a593Smuzhiyun #define WBSD_IDX_RSPLEN 0x1E 81*4882a593Smuzhiyun #define WBSD_IDX_RESP0 0x1F 82*4882a593Smuzhiyun #define WBSD_IDX_RESP1 0x20 83*4882a593Smuzhiyun #define WBSD_IDX_RESP2 0x21 84*4882a593Smuzhiyun #define WBSD_IDX_RESP3 0x22 85*4882a593Smuzhiyun #define WBSD_IDX_RESP4 0x23 86*4882a593Smuzhiyun #define WBSD_IDX_RESP5 0x24 87*4882a593Smuzhiyun #define WBSD_IDX_RESP6 0x25 88*4882a593Smuzhiyun #define WBSD_IDX_RESP7 0x26 89*4882a593Smuzhiyun #define WBSD_IDX_RESP8 0x27 90*4882a593Smuzhiyun #define WBSD_IDX_RESP9 0x28 91*4882a593Smuzhiyun #define WBSD_IDX_RESP10 0x29 92*4882a593Smuzhiyun #define WBSD_IDX_RESP11 0x2A 93*4882a593Smuzhiyun #define WBSD_IDX_RESP12 0x2B 94*4882a593Smuzhiyun #define WBSD_IDX_RESP13 0x2C 95*4882a593Smuzhiyun #define WBSD_IDX_RESP14 0x2D 96*4882a593Smuzhiyun #define WBSD_IDX_RESP15 0x2E 97*4882a593Smuzhiyun #define WBSD_IDX_RESP16 0x2F 98*4882a593Smuzhiyun #define WBSD_IDX_CRCSTATUS 0x30 99*4882a593Smuzhiyun #define WBSD_IDX_ISR 0x3F 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define WBSD_CLK_375K 0x00 102*4882a593Smuzhiyun #define WBSD_CLK_12M 0x01 103*4882a593Smuzhiyun #define WBSD_CLK_16M 0x02 104*4882a593Smuzhiyun #define WBSD_CLK_24M 0x03 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #define WBSD_DATA_WIDTH 0x01 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define WBSD_DAT3_H 0x08 109*4882a593Smuzhiyun #define WBSD_FIFO_RESET 0x04 110*4882a593Smuzhiyun #define WBSD_SOFT_RESET 0x02 111*4882a593Smuzhiyun #define WBSD_INC_INDEX 0x01 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define WBSD_DMA_SINGLE 0x02 114*4882a593Smuzhiyun #define WBSD_DMA_ENABLE 0x01 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #define WBSD_FIFOEN_EMPTY 0x20 117*4882a593Smuzhiyun #define WBSD_FIFOEN_FULL 0x10 118*4882a593Smuzhiyun #define WBSD_FIFO_THREMASK 0x0F 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #define WBSD_BLOCK_READ 0x80 121*4882a593Smuzhiyun #define WBSD_BLOCK_WRITE 0x40 122*4882a593Smuzhiyun #define WBSD_BUSY 0x20 123*4882a593Smuzhiyun #define WBSD_CARDTRAFFIC 0x04 124*4882a593Smuzhiyun #define WBSD_SENDCMD 0x02 125*4882a593Smuzhiyun #define WBSD_RECVRES 0x01 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define WBSD_RSP_SHORT 0x00 128*4882a593Smuzhiyun #define WBSD_RSP_LONG 0x01 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #define WBSD_CRC_MASK 0x1F 131*4882a593Smuzhiyun #define WBSD_CRC_OK 0x05 /* S010E (00101) */ 132*4882a593Smuzhiyun #define WBSD_CRC_FAIL 0x0B /* S101E (01011) */ 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #define WBSD_DMA_SIZE 65536 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun struct wbsd_host 137*4882a593Smuzhiyun { 138*4882a593Smuzhiyun struct mmc_host* mmc; /* MMC structure */ 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun spinlock_t lock; /* Mutex */ 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun int flags; /* Driver states */ 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun #define WBSD_FCARD_PRESENT (1<<0) /* Card is present */ 145*4882a593Smuzhiyun #define WBSD_FIGNORE_DETECT (1<<1) /* Ignore card detection */ 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun struct mmc_request* mrq; /* Current request */ 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun u8 isr; /* Accumulated ISR */ 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun struct scatterlist* cur_sg; /* Current SG entry */ 152*4882a593Smuzhiyun unsigned int num_sg; /* Number of entries left */ 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun unsigned int offset; /* Offset into current entry */ 155*4882a593Smuzhiyun unsigned int remain; /* Data left in curren entry */ 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun char* dma_buffer; /* ISA DMA buffer */ 158*4882a593Smuzhiyun dma_addr_t dma_addr; /* Physical address for same */ 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun int firsterr; /* See fifo functions */ 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun u8 clk; /* Current clock speed */ 163*4882a593Smuzhiyun unsigned char bus_width; /* Current bus width */ 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun int config; /* Config port */ 166*4882a593Smuzhiyun u8 unlock_code; /* Code to unlock config */ 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun int chip_id; /* ID of controller */ 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun int base; /* I/O port base */ 171*4882a593Smuzhiyun int irq; /* Interrupt */ 172*4882a593Smuzhiyun int dma; /* DMA channel */ 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun struct tasklet_struct card_tasklet; /* Tasklet structures */ 175*4882a593Smuzhiyun struct tasklet_struct fifo_tasklet; 176*4882a593Smuzhiyun struct tasklet_struct crc_tasklet; 177*4882a593Smuzhiyun struct tasklet_struct timeout_tasklet; 178*4882a593Smuzhiyun struct tasklet_struct finish_tasklet; 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun struct timer_list ignore_timer; /* Ignore detection timer */ 181*4882a593Smuzhiyun }; 182