1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * tifm_sd.c - TI FlashMedia driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2006 Alex Dubov <oakad@yahoo.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Special thanks to Brad Campbell for extensive testing of this driver.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/tifm.h>
12*4882a593Smuzhiyun #include <linux/mmc/host.h>
13*4882a593Smuzhiyun #include <linux/highmem.h>
14*4882a593Smuzhiyun #include <linux/scatterlist.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <asm/io.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define DRIVER_NAME "tifm_sd"
19*4882a593Smuzhiyun #define DRIVER_VERSION "0.8"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun static bool no_dma = 0;
22*4882a593Smuzhiyun static bool fixed_timeout = 0;
23*4882a593Smuzhiyun module_param(no_dma, bool, 0644);
24*4882a593Smuzhiyun module_param(fixed_timeout, bool, 0644);
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* Constants here are mostly from OMAP5912 datasheet */
27*4882a593Smuzhiyun #define TIFM_MMCSD_RESET 0x0002
28*4882a593Smuzhiyun #define TIFM_MMCSD_CLKMASK 0x03ff
29*4882a593Smuzhiyun #define TIFM_MMCSD_POWER 0x0800
30*4882a593Smuzhiyun #define TIFM_MMCSD_4BBUS 0x8000
31*4882a593Smuzhiyun #define TIFM_MMCSD_RXDE 0x8000 /* rx dma enable */
32*4882a593Smuzhiyun #define TIFM_MMCSD_TXDE 0x0080 /* tx dma enable */
33*4882a593Smuzhiyun #define TIFM_MMCSD_BUFINT 0x0c00 /* set bits: AE, AF */
34*4882a593Smuzhiyun #define TIFM_MMCSD_DPE 0x0020 /* data timeout counted in kilocycles */
35*4882a593Smuzhiyun #define TIFM_MMCSD_INAB 0x0080 /* abort / initialize command */
36*4882a593Smuzhiyun #define TIFM_MMCSD_READ 0x8000
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #define TIFM_MMCSD_ERRMASK 0x01e0 /* set bits: CCRC, CTO, DCRC, DTO */
39*4882a593Smuzhiyun #define TIFM_MMCSD_EOC 0x0001 /* end of command phase */
40*4882a593Smuzhiyun #define TIFM_MMCSD_CD 0x0002 /* card detect */
41*4882a593Smuzhiyun #define TIFM_MMCSD_CB 0x0004 /* card enter busy state */
42*4882a593Smuzhiyun #define TIFM_MMCSD_BRS 0x0008 /* block received/sent */
43*4882a593Smuzhiyun #define TIFM_MMCSD_EOFB 0x0010 /* card exit busy state */
44*4882a593Smuzhiyun #define TIFM_MMCSD_DTO 0x0020 /* data time-out */
45*4882a593Smuzhiyun #define TIFM_MMCSD_DCRC 0x0040 /* data crc error */
46*4882a593Smuzhiyun #define TIFM_MMCSD_CTO 0x0080 /* command time-out */
47*4882a593Smuzhiyun #define TIFM_MMCSD_CCRC 0x0100 /* command crc error */
48*4882a593Smuzhiyun #define TIFM_MMCSD_AF 0x0400 /* fifo almost full */
49*4882a593Smuzhiyun #define TIFM_MMCSD_AE 0x0800 /* fifo almost empty */
50*4882a593Smuzhiyun #define TIFM_MMCSD_OCRB 0x1000 /* OCR busy */
51*4882a593Smuzhiyun #define TIFM_MMCSD_CIRQ 0x2000 /* card irq (cmd40/sdio) */
52*4882a593Smuzhiyun #define TIFM_MMCSD_CERR 0x4000 /* card status error */
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #define TIFM_MMCSD_ODTO 0x0040 /* open drain / extended timeout */
55*4882a593Smuzhiyun #define TIFM_MMCSD_CARD_RO 0x0200 /* card is read-only */
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun #define TIFM_MMCSD_FIFO_SIZE 0x0020
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun #define TIFM_MMCSD_RSP_R0 0x0000
60*4882a593Smuzhiyun #define TIFM_MMCSD_RSP_R1 0x0100
61*4882a593Smuzhiyun #define TIFM_MMCSD_RSP_R2 0x0200
62*4882a593Smuzhiyun #define TIFM_MMCSD_RSP_R3 0x0300
63*4882a593Smuzhiyun #define TIFM_MMCSD_RSP_R4 0x0400
64*4882a593Smuzhiyun #define TIFM_MMCSD_RSP_R5 0x0500
65*4882a593Smuzhiyun #define TIFM_MMCSD_RSP_R6 0x0600
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun #define TIFM_MMCSD_RSP_BUSY 0x0800
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun #define TIFM_MMCSD_CMD_BC 0x0000
70*4882a593Smuzhiyun #define TIFM_MMCSD_CMD_BCR 0x1000
71*4882a593Smuzhiyun #define TIFM_MMCSD_CMD_AC 0x2000
72*4882a593Smuzhiyun #define TIFM_MMCSD_CMD_ADTC 0x3000
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun #define TIFM_MMCSD_MAX_BLOCK_SIZE 0x0800UL
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun #define TIFM_MMCSD_REQ_TIMEOUT_MS 1000
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun enum {
79*4882a593Smuzhiyun CMD_READY = 0x0001,
80*4882a593Smuzhiyun FIFO_READY = 0x0002,
81*4882a593Smuzhiyun BRS_READY = 0x0004,
82*4882a593Smuzhiyun SCMD_ACTIVE = 0x0008,
83*4882a593Smuzhiyun SCMD_READY = 0x0010,
84*4882a593Smuzhiyun CARD_BUSY = 0x0020,
85*4882a593Smuzhiyun DATA_CARRY = 0x0040
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun struct tifm_sd {
89*4882a593Smuzhiyun struct tifm_dev *dev;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun unsigned short eject:1,
92*4882a593Smuzhiyun open_drain:1,
93*4882a593Smuzhiyun no_dma:1;
94*4882a593Smuzhiyun unsigned short cmd_flags;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun unsigned int clk_freq;
97*4882a593Smuzhiyun unsigned int clk_div;
98*4882a593Smuzhiyun unsigned long timeout_jiffies;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun struct tasklet_struct finish_tasklet;
101*4882a593Smuzhiyun struct timer_list timer;
102*4882a593Smuzhiyun struct mmc_request *req;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun int sg_len;
105*4882a593Smuzhiyun int sg_pos;
106*4882a593Smuzhiyun unsigned int block_pos;
107*4882a593Smuzhiyun struct scatterlist bounce_buf;
108*4882a593Smuzhiyun unsigned char bounce_buf_data[TIFM_MMCSD_MAX_BLOCK_SIZE];
109*4882a593Smuzhiyun };
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* for some reason, host won't respond correctly to readw/writew */
tifm_sd_read_fifo(struct tifm_sd * host,struct page * pg,unsigned int off,unsigned int cnt)112*4882a593Smuzhiyun static void tifm_sd_read_fifo(struct tifm_sd *host, struct page *pg,
113*4882a593Smuzhiyun unsigned int off, unsigned int cnt)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun struct tifm_dev *sock = host->dev;
116*4882a593Smuzhiyun unsigned char *buf;
117*4882a593Smuzhiyun unsigned int pos = 0, val;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun buf = kmap_atomic(pg) + off;
120*4882a593Smuzhiyun if (host->cmd_flags & DATA_CARRY) {
121*4882a593Smuzhiyun buf[pos++] = host->bounce_buf_data[0];
122*4882a593Smuzhiyun host->cmd_flags &= ~DATA_CARRY;
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun while (pos < cnt) {
126*4882a593Smuzhiyun val = readl(sock->addr + SOCK_MMCSD_DATA);
127*4882a593Smuzhiyun buf[pos++] = val & 0xff;
128*4882a593Smuzhiyun if (pos == cnt) {
129*4882a593Smuzhiyun host->bounce_buf_data[0] = (val >> 8) & 0xff;
130*4882a593Smuzhiyun host->cmd_flags |= DATA_CARRY;
131*4882a593Smuzhiyun break;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun buf[pos++] = (val >> 8) & 0xff;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun kunmap_atomic(buf - off);
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
tifm_sd_write_fifo(struct tifm_sd * host,struct page * pg,unsigned int off,unsigned int cnt)138*4882a593Smuzhiyun static void tifm_sd_write_fifo(struct tifm_sd *host, struct page *pg,
139*4882a593Smuzhiyun unsigned int off, unsigned int cnt)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun struct tifm_dev *sock = host->dev;
142*4882a593Smuzhiyun unsigned char *buf;
143*4882a593Smuzhiyun unsigned int pos = 0, val;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun buf = kmap_atomic(pg) + off;
146*4882a593Smuzhiyun if (host->cmd_flags & DATA_CARRY) {
147*4882a593Smuzhiyun val = host->bounce_buf_data[0] | ((buf[pos++] << 8) & 0xff00);
148*4882a593Smuzhiyun writel(val, sock->addr + SOCK_MMCSD_DATA);
149*4882a593Smuzhiyun host->cmd_flags &= ~DATA_CARRY;
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun while (pos < cnt) {
153*4882a593Smuzhiyun val = buf[pos++];
154*4882a593Smuzhiyun if (pos == cnt) {
155*4882a593Smuzhiyun host->bounce_buf_data[0] = val & 0xff;
156*4882a593Smuzhiyun host->cmd_flags |= DATA_CARRY;
157*4882a593Smuzhiyun break;
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun val |= (buf[pos++] << 8) & 0xff00;
160*4882a593Smuzhiyun writel(val, sock->addr + SOCK_MMCSD_DATA);
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun kunmap_atomic(buf - off);
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun
tifm_sd_transfer_data(struct tifm_sd * host)165*4882a593Smuzhiyun static void tifm_sd_transfer_data(struct tifm_sd *host)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun struct mmc_data *r_data = host->req->cmd->data;
168*4882a593Smuzhiyun struct scatterlist *sg = r_data->sg;
169*4882a593Smuzhiyun unsigned int off, cnt, t_size = TIFM_MMCSD_FIFO_SIZE * 2;
170*4882a593Smuzhiyun unsigned int p_off, p_cnt;
171*4882a593Smuzhiyun struct page *pg;
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun if (host->sg_pos == host->sg_len)
174*4882a593Smuzhiyun return;
175*4882a593Smuzhiyun while (t_size) {
176*4882a593Smuzhiyun cnt = sg[host->sg_pos].length - host->block_pos;
177*4882a593Smuzhiyun if (!cnt) {
178*4882a593Smuzhiyun host->block_pos = 0;
179*4882a593Smuzhiyun host->sg_pos++;
180*4882a593Smuzhiyun if (host->sg_pos == host->sg_len) {
181*4882a593Smuzhiyun if ((r_data->flags & MMC_DATA_WRITE)
182*4882a593Smuzhiyun && (host->cmd_flags & DATA_CARRY))
183*4882a593Smuzhiyun writel(host->bounce_buf_data[0],
184*4882a593Smuzhiyun host->dev->addr
185*4882a593Smuzhiyun + SOCK_MMCSD_DATA);
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun return;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun cnt = sg[host->sg_pos].length;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun off = sg[host->sg_pos].offset + host->block_pos;
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun pg = nth_page(sg_page(&sg[host->sg_pos]), off >> PAGE_SHIFT);
194*4882a593Smuzhiyun p_off = offset_in_page(off);
195*4882a593Smuzhiyun p_cnt = PAGE_SIZE - p_off;
196*4882a593Smuzhiyun p_cnt = min(p_cnt, cnt);
197*4882a593Smuzhiyun p_cnt = min(p_cnt, t_size);
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun if (r_data->flags & MMC_DATA_READ)
200*4882a593Smuzhiyun tifm_sd_read_fifo(host, pg, p_off, p_cnt);
201*4882a593Smuzhiyun else if (r_data->flags & MMC_DATA_WRITE)
202*4882a593Smuzhiyun tifm_sd_write_fifo(host, pg, p_off, p_cnt);
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun t_size -= p_cnt;
205*4882a593Smuzhiyun host->block_pos += p_cnt;
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun
tifm_sd_copy_page(struct page * dst,unsigned int dst_off,struct page * src,unsigned int src_off,unsigned int count)209*4882a593Smuzhiyun static void tifm_sd_copy_page(struct page *dst, unsigned int dst_off,
210*4882a593Smuzhiyun struct page *src, unsigned int src_off,
211*4882a593Smuzhiyun unsigned int count)
212*4882a593Smuzhiyun {
213*4882a593Smuzhiyun unsigned char *src_buf = kmap_atomic(src) + src_off;
214*4882a593Smuzhiyun unsigned char *dst_buf = kmap_atomic(dst) + dst_off;
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun memcpy(dst_buf, src_buf, count);
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun kunmap_atomic(dst_buf - dst_off);
219*4882a593Smuzhiyun kunmap_atomic(src_buf - src_off);
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun
tifm_sd_bounce_block(struct tifm_sd * host,struct mmc_data * r_data)222*4882a593Smuzhiyun static void tifm_sd_bounce_block(struct tifm_sd *host, struct mmc_data *r_data)
223*4882a593Smuzhiyun {
224*4882a593Smuzhiyun struct scatterlist *sg = r_data->sg;
225*4882a593Smuzhiyun unsigned int t_size = r_data->blksz;
226*4882a593Smuzhiyun unsigned int off, cnt;
227*4882a593Smuzhiyun unsigned int p_off, p_cnt;
228*4882a593Smuzhiyun struct page *pg;
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun dev_dbg(&host->dev->dev, "bouncing block\n");
231*4882a593Smuzhiyun while (t_size) {
232*4882a593Smuzhiyun cnt = sg[host->sg_pos].length - host->block_pos;
233*4882a593Smuzhiyun if (!cnt) {
234*4882a593Smuzhiyun host->block_pos = 0;
235*4882a593Smuzhiyun host->sg_pos++;
236*4882a593Smuzhiyun if (host->sg_pos == host->sg_len)
237*4882a593Smuzhiyun return;
238*4882a593Smuzhiyun cnt = sg[host->sg_pos].length;
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun off = sg[host->sg_pos].offset + host->block_pos;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun pg = nth_page(sg_page(&sg[host->sg_pos]), off >> PAGE_SHIFT);
243*4882a593Smuzhiyun p_off = offset_in_page(off);
244*4882a593Smuzhiyun p_cnt = PAGE_SIZE - p_off;
245*4882a593Smuzhiyun p_cnt = min(p_cnt, cnt);
246*4882a593Smuzhiyun p_cnt = min(p_cnt, t_size);
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun if (r_data->flags & MMC_DATA_WRITE)
249*4882a593Smuzhiyun tifm_sd_copy_page(sg_page(&host->bounce_buf),
250*4882a593Smuzhiyun r_data->blksz - t_size,
251*4882a593Smuzhiyun pg, p_off, p_cnt);
252*4882a593Smuzhiyun else if (r_data->flags & MMC_DATA_READ)
253*4882a593Smuzhiyun tifm_sd_copy_page(pg, p_off, sg_page(&host->bounce_buf),
254*4882a593Smuzhiyun r_data->blksz - t_size, p_cnt);
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun t_size -= p_cnt;
257*4882a593Smuzhiyun host->block_pos += p_cnt;
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun
tifm_sd_set_dma_data(struct tifm_sd * host,struct mmc_data * r_data)261*4882a593Smuzhiyun static int tifm_sd_set_dma_data(struct tifm_sd *host, struct mmc_data *r_data)
262*4882a593Smuzhiyun {
263*4882a593Smuzhiyun struct tifm_dev *sock = host->dev;
264*4882a593Smuzhiyun unsigned int t_size = TIFM_DMA_TSIZE * r_data->blksz;
265*4882a593Smuzhiyun unsigned int dma_len, dma_blk_cnt, dma_off;
266*4882a593Smuzhiyun struct scatterlist *sg = NULL;
267*4882a593Smuzhiyun unsigned long flags;
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun if (host->sg_pos == host->sg_len)
270*4882a593Smuzhiyun return 1;
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun if (host->cmd_flags & DATA_CARRY) {
273*4882a593Smuzhiyun host->cmd_flags &= ~DATA_CARRY;
274*4882a593Smuzhiyun local_irq_save(flags);
275*4882a593Smuzhiyun tifm_sd_bounce_block(host, r_data);
276*4882a593Smuzhiyun local_irq_restore(flags);
277*4882a593Smuzhiyun if (host->sg_pos == host->sg_len)
278*4882a593Smuzhiyun return 1;
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun dma_len = sg_dma_len(&r_data->sg[host->sg_pos]) - host->block_pos;
282*4882a593Smuzhiyun if (!dma_len) {
283*4882a593Smuzhiyun host->block_pos = 0;
284*4882a593Smuzhiyun host->sg_pos++;
285*4882a593Smuzhiyun if (host->sg_pos == host->sg_len)
286*4882a593Smuzhiyun return 1;
287*4882a593Smuzhiyun dma_len = sg_dma_len(&r_data->sg[host->sg_pos]);
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun if (dma_len < t_size) {
291*4882a593Smuzhiyun dma_blk_cnt = dma_len / r_data->blksz;
292*4882a593Smuzhiyun dma_off = host->block_pos;
293*4882a593Smuzhiyun host->block_pos += dma_blk_cnt * r_data->blksz;
294*4882a593Smuzhiyun } else {
295*4882a593Smuzhiyun dma_blk_cnt = TIFM_DMA_TSIZE;
296*4882a593Smuzhiyun dma_off = host->block_pos;
297*4882a593Smuzhiyun host->block_pos += t_size;
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun if (dma_blk_cnt)
301*4882a593Smuzhiyun sg = &r_data->sg[host->sg_pos];
302*4882a593Smuzhiyun else if (dma_len) {
303*4882a593Smuzhiyun if (r_data->flags & MMC_DATA_WRITE) {
304*4882a593Smuzhiyun local_irq_save(flags);
305*4882a593Smuzhiyun tifm_sd_bounce_block(host, r_data);
306*4882a593Smuzhiyun local_irq_restore(flags);
307*4882a593Smuzhiyun } else
308*4882a593Smuzhiyun host->cmd_flags |= DATA_CARRY;
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun sg = &host->bounce_buf;
311*4882a593Smuzhiyun dma_off = 0;
312*4882a593Smuzhiyun dma_blk_cnt = 1;
313*4882a593Smuzhiyun } else
314*4882a593Smuzhiyun return 1;
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun dev_dbg(&sock->dev, "setting dma for %d blocks\n", dma_blk_cnt);
317*4882a593Smuzhiyun writel(sg_dma_address(sg) + dma_off, sock->addr + SOCK_DMA_ADDRESS);
318*4882a593Smuzhiyun if (r_data->flags & MMC_DATA_WRITE)
319*4882a593Smuzhiyun writel((dma_blk_cnt << 8) | TIFM_DMA_TX | TIFM_DMA_EN,
320*4882a593Smuzhiyun sock->addr + SOCK_DMA_CONTROL);
321*4882a593Smuzhiyun else
322*4882a593Smuzhiyun writel((dma_blk_cnt << 8) | TIFM_DMA_EN,
323*4882a593Smuzhiyun sock->addr + SOCK_DMA_CONTROL);
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun return 0;
326*4882a593Smuzhiyun }
327*4882a593Smuzhiyun
tifm_sd_op_flags(struct mmc_command * cmd)328*4882a593Smuzhiyun static unsigned int tifm_sd_op_flags(struct mmc_command *cmd)
329*4882a593Smuzhiyun {
330*4882a593Smuzhiyun unsigned int rc = 0;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun switch (mmc_resp_type(cmd)) {
333*4882a593Smuzhiyun case MMC_RSP_NONE:
334*4882a593Smuzhiyun rc |= TIFM_MMCSD_RSP_R0;
335*4882a593Smuzhiyun break;
336*4882a593Smuzhiyun case MMC_RSP_R1B:
337*4882a593Smuzhiyun rc |= TIFM_MMCSD_RSP_BUSY;
338*4882a593Smuzhiyun fallthrough;
339*4882a593Smuzhiyun case MMC_RSP_R1:
340*4882a593Smuzhiyun rc |= TIFM_MMCSD_RSP_R1;
341*4882a593Smuzhiyun break;
342*4882a593Smuzhiyun case MMC_RSP_R2:
343*4882a593Smuzhiyun rc |= TIFM_MMCSD_RSP_R2;
344*4882a593Smuzhiyun break;
345*4882a593Smuzhiyun case MMC_RSP_R3:
346*4882a593Smuzhiyun rc |= TIFM_MMCSD_RSP_R3;
347*4882a593Smuzhiyun break;
348*4882a593Smuzhiyun default:
349*4882a593Smuzhiyun BUG();
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun switch (mmc_cmd_type(cmd)) {
353*4882a593Smuzhiyun case MMC_CMD_BC:
354*4882a593Smuzhiyun rc |= TIFM_MMCSD_CMD_BC;
355*4882a593Smuzhiyun break;
356*4882a593Smuzhiyun case MMC_CMD_BCR:
357*4882a593Smuzhiyun rc |= TIFM_MMCSD_CMD_BCR;
358*4882a593Smuzhiyun break;
359*4882a593Smuzhiyun case MMC_CMD_AC:
360*4882a593Smuzhiyun rc |= TIFM_MMCSD_CMD_AC;
361*4882a593Smuzhiyun break;
362*4882a593Smuzhiyun case MMC_CMD_ADTC:
363*4882a593Smuzhiyun rc |= TIFM_MMCSD_CMD_ADTC;
364*4882a593Smuzhiyun break;
365*4882a593Smuzhiyun default:
366*4882a593Smuzhiyun BUG();
367*4882a593Smuzhiyun }
368*4882a593Smuzhiyun return rc;
369*4882a593Smuzhiyun }
370*4882a593Smuzhiyun
tifm_sd_exec(struct tifm_sd * host,struct mmc_command * cmd)371*4882a593Smuzhiyun static void tifm_sd_exec(struct tifm_sd *host, struct mmc_command *cmd)
372*4882a593Smuzhiyun {
373*4882a593Smuzhiyun struct tifm_dev *sock = host->dev;
374*4882a593Smuzhiyun unsigned int cmd_mask = tifm_sd_op_flags(cmd);
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun if (host->open_drain)
377*4882a593Smuzhiyun cmd_mask |= TIFM_MMCSD_ODTO;
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
380*4882a593Smuzhiyun cmd_mask |= TIFM_MMCSD_READ;
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun dev_dbg(&sock->dev, "executing opcode 0x%x, arg: 0x%x, mask: 0x%x\n",
383*4882a593Smuzhiyun cmd->opcode, cmd->arg, cmd_mask);
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH);
386*4882a593Smuzhiyun writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW);
387*4882a593Smuzhiyun writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND);
388*4882a593Smuzhiyun }
389*4882a593Smuzhiyun
tifm_sd_fetch_resp(struct mmc_command * cmd,struct tifm_dev * sock)390*4882a593Smuzhiyun static void tifm_sd_fetch_resp(struct mmc_command *cmd, struct tifm_dev *sock)
391*4882a593Smuzhiyun {
392*4882a593Smuzhiyun cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16)
393*4882a593Smuzhiyun | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18);
394*4882a593Smuzhiyun cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16)
395*4882a593Smuzhiyun | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10);
396*4882a593Smuzhiyun cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16)
397*4882a593Smuzhiyun | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08);
398*4882a593Smuzhiyun cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16)
399*4882a593Smuzhiyun | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00);
400*4882a593Smuzhiyun }
401*4882a593Smuzhiyun
tifm_sd_check_status(struct tifm_sd * host)402*4882a593Smuzhiyun static void tifm_sd_check_status(struct tifm_sd *host)
403*4882a593Smuzhiyun {
404*4882a593Smuzhiyun struct tifm_dev *sock = host->dev;
405*4882a593Smuzhiyun struct mmc_command *cmd = host->req->cmd;
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun if (cmd->error)
408*4882a593Smuzhiyun goto finish_request;
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun if (!(host->cmd_flags & CMD_READY))
411*4882a593Smuzhiyun return;
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun if (cmd->data) {
414*4882a593Smuzhiyun if (cmd->data->error) {
415*4882a593Smuzhiyun if ((host->cmd_flags & SCMD_ACTIVE)
416*4882a593Smuzhiyun && !(host->cmd_flags & SCMD_READY))
417*4882a593Smuzhiyun return;
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun goto finish_request;
420*4882a593Smuzhiyun }
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun if (!(host->cmd_flags & BRS_READY))
423*4882a593Smuzhiyun return;
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun if (!(host->no_dma || (host->cmd_flags & FIFO_READY)))
426*4882a593Smuzhiyun return;
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun if (cmd->data->flags & MMC_DATA_WRITE) {
429*4882a593Smuzhiyun if (host->req->stop) {
430*4882a593Smuzhiyun if (!(host->cmd_flags & SCMD_ACTIVE)) {
431*4882a593Smuzhiyun host->cmd_flags |= SCMD_ACTIVE;
432*4882a593Smuzhiyun writel(TIFM_MMCSD_EOFB
433*4882a593Smuzhiyun | readl(sock->addr
434*4882a593Smuzhiyun + SOCK_MMCSD_INT_ENABLE),
435*4882a593Smuzhiyun sock->addr
436*4882a593Smuzhiyun + SOCK_MMCSD_INT_ENABLE);
437*4882a593Smuzhiyun tifm_sd_exec(host, host->req->stop);
438*4882a593Smuzhiyun return;
439*4882a593Smuzhiyun } else {
440*4882a593Smuzhiyun if (!(host->cmd_flags & SCMD_READY)
441*4882a593Smuzhiyun || (host->cmd_flags & CARD_BUSY))
442*4882a593Smuzhiyun return;
443*4882a593Smuzhiyun writel((~TIFM_MMCSD_EOFB)
444*4882a593Smuzhiyun & readl(sock->addr
445*4882a593Smuzhiyun + SOCK_MMCSD_INT_ENABLE),
446*4882a593Smuzhiyun sock->addr
447*4882a593Smuzhiyun + SOCK_MMCSD_INT_ENABLE);
448*4882a593Smuzhiyun }
449*4882a593Smuzhiyun } else {
450*4882a593Smuzhiyun if (host->cmd_flags & CARD_BUSY)
451*4882a593Smuzhiyun return;
452*4882a593Smuzhiyun writel((~TIFM_MMCSD_EOFB)
453*4882a593Smuzhiyun & readl(sock->addr
454*4882a593Smuzhiyun + SOCK_MMCSD_INT_ENABLE),
455*4882a593Smuzhiyun sock->addr + SOCK_MMCSD_INT_ENABLE);
456*4882a593Smuzhiyun }
457*4882a593Smuzhiyun } else {
458*4882a593Smuzhiyun if (host->req->stop) {
459*4882a593Smuzhiyun if (!(host->cmd_flags & SCMD_ACTIVE)) {
460*4882a593Smuzhiyun host->cmd_flags |= SCMD_ACTIVE;
461*4882a593Smuzhiyun tifm_sd_exec(host, host->req->stop);
462*4882a593Smuzhiyun return;
463*4882a593Smuzhiyun } else {
464*4882a593Smuzhiyun if (!(host->cmd_flags & SCMD_READY))
465*4882a593Smuzhiyun return;
466*4882a593Smuzhiyun }
467*4882a593Smuzhiyun }
468*4882a593Smuzhiyun }
469*4882a593Smuzhiyun }
470*4882a593Smuzhiyun finish_request:
471*4882a593Smuzhiyun tasklet_schedule(&host->finish_tasklet);
472*4882a593Smuzhiyun }
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun /* Called from interrupt handler */
tifm_sd_data_event(struct tifm_dev * sock)475*4882a593Smuzhiyun static void tifm_sd_data_event(struct tifm_dev *sock)
476*4882a593Smuzhiyun {
477*4882a593Smuzhiyun struct tifm_sd *host;
478*4882a593Smuzhiyun unsigned int fifo_status = 0;
479*4882a593Smuzhiyun struct mmc_data *r_data = NULL;
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun spin_lock(&sock->lock);
482*4882a593Smuzhiyun host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
483*4882a593Smuzhiyun fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS);
484*4882a593Smuzhiyun dev_dbg(&sock->dev, "data event: fifo_status %x, flags %x\n",
485*4882a593Smuzhiyun fifo_status, host->cmd_flags);
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun if (host->req) {
488*4882a593Smuzhiyun r_data = host->req->cmd->data;
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun if (r_data && (fifo_status & TIFM_FIFO_READY)) {
491*4882a593Smuzhiyun if (tifm_sd_set_dma_data(host, r_data)) {
492*4882a593Smuzhiyun host->cmd_flags |= FIFO_READY;
493*4882a593Smuzhiyun tifm_sd_check_status(host);
494*4882a593Smuzhiyun }
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
499*4882a593Smuzhiyun spin_unlock(&sock->lock);
500*4882a593Smuzhiyun }
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun /* Called from interrupt handler */
tifm_sd_card_event(struct tifm_dev * sock)503*4882a593Smuzhiyun static void tifm_sd_card_event(struct tifm_dev *sock)
504*4882a593Smuzhiyun {
505*4882a593Smuzhiyun struct tifm_sd *host;
506*4882a593Smuzhiyun unsigned int host_status = 0;
507*4882a593Smuzhiyun int cmd_error = 0;
508*4882a593Smuzhiyun struct mmc_command *cmd = NULL;
509*4882a593Smuzhiyun unsigned long flags;
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun spin_lock(&sock->lock);
512*4882a593Smuzhiyun host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
513*4882a593Smuzhiyun host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
514*4882a593Smuzhiyun dev_dbg(&sock->dev, "host event: host_status %x, flags %x\n",
515*4882a593Smuzhiyun host_status, host->cmd_flags);
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun if (host->req) {
518*4882a593Smuzhiyun cmd = host->req->cmd;
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun if (host_status & TIFM_MMCSD_ERRMASK) {
521*4882a593Smuzhiyun writel(host_status & TIFM_MMCSD_ERRMASK,
522*4882a593Smuzhiyun sock->addr + SOCK_MMCSD_STATUS);
523*4882a593Smuzhiyun if (host_status & TIFM_MMCSD_CTO)
524*4882a593Smuzhiyun cmd_error = -ETIMEDOUT;
525*4882a593Smuzhiyun else if (host_status & TIFM_MMCSD_CCRC)
526*4882a593Smuzhiyun cmd_error = -EILSEQ;
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun if (cmd->data) {
529*4882a593Smuzhiyun if (host_status & TIFM_MMCSD_DTO)
530*4882a593Smuzhiyun cmd->data->error = -ETIMEDOUT;
531*4882a593Smuzhiyun else if (host_status & TIFM_MMCSD_DCRC)
532*4882a593Smuzhiyun cmd->data->error = -EILSEQ;
533*4882a593Smuzhiyun }
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun writel(TIFM_FIFO_INT_SETALL,
536*4882a593Smuzhiyun sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
537*4882a593Smuzhiyun writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun if (host->req->stop) {
540*4882a593Smuzhiyun if (host->cmd_flags & SCMD_ACTIVE) {
541*4882a593Smuzhiyun host->req->stop->error = cmd_error;
542*4882a593Smuzhiyun host->cmd_flags |= SCMD_READY;
543*4882a593Smuzhiyun } else {
544*4882a593Smuzhiyun cmd->error = cmd_error;
545*4882a593Smuzhiyun host->cmd_flags |= SCMD_ACTIVE;
546*4882a593Smuzhiyun tifm_sd_exec(host, host->req->stop);
547*4882a593Smuzhiyun goto done;
548*4882a593Smuzhiyun }
549*4882a593Smuzhiyun } else
550*4882a593Smuzhiyun cmd->error = cmd_error;
551*4882a593Smuzhiyun } else {
552*4882a593Smuzhiyun if (host_status & (TIFM_MMCSD_EOC | TIFM_MMCSD_CERR)) {
553*4882a593Smuzhiyun if (!(host->cmd_flags & CMD_READY)) {
554*4882a593Smuzhiyun host->cmd_flags |= CMD_READY;
555*4882a593Smuzhiyun tifm_sd_fetch_resp(cmd, sock);
556*4882a593Smuzhiyun } else if (host->cmd_flags & SCMD_ACTIVE) {
557*4882a593Smuzhiyun host->cmd_flags |= SCMD_READY;
558*4882a593Smuzhiyun tifm_sd_fetch_resp(host->req->stop,
559*4882a593Smuzhiyun sock);
560*4882a593Smuzhiyun }
561*4882a593Smuzhiyun }
562*4882a593Smuzhiyun if (host_status & TIFM_MMCSD_BRS)
563*4882a593Smuzhiyun host->cmd_flags |= BRS_READY;
564*4882a593Smuzhiyun }
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun if (host->no_dma && cmd->data) {
567*4882a593Smuzhiyun if (host_status & TIFM_MMCSD_AE)
568*4882a593Smuzhiyun writel(host_status & TIFM_MMCSD_AE,
569*4882a593Smuzhiyun sock->addr + SOCK_MMCSD_STATUS);
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun if (host_status & (TIFM_MMCSD_AE | TIFM_MMCSD_AF
572*4882a593Smuzhiyun | TIFM_MMCSD_BRS)) {
573*4882a593Smuzhiyun local_irq_save(flags);
574*4882a593Smuzhiyun tifm_sd_transfer_data(host);
575*4882a593Smuzhiyun local_irq_restore(flags);
576*4882a593Smuzhiyun host_status &= ~TIFM_MMCSD_AE;
577*4882a593Smuzhiyun }
578*4882a593Smuzhiyun }
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun if (host_status & TIFM_MMCSD_EOFB)
581*4882a593Smuzhiyun host->cmd_flags &= ~CARD_BUSY;
582*4882a593Smuzhiyun else if (host_status & TIFM_MMCSD_CB)
583*4882a593Smuzhiyun host->cmd_flags |= CARD_BUSY;
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun tifm_sd_check_status(host);
586*4882a593Smuzhiyun }
587*4882a593Smuzhiyun done:
588*4882a593Smuzhiyun writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
589*4882a593Smuzhiyun spin_unlock(&sock->lock);
590*4882a593Smuzhiyun }
591*4882a593Smuzhiyun
tifm_sd_set_data_timeout(struct tifm_sd * host,struct mmc_data * data)592*4882a593Smuzhiyun static void tifm_sd_set_data_timeout(struct tifm_sd *host,
593*4882a593Smuzhiyun struct mmc_data *data)
594*4882a593Smuzhiyun {
595*4882a593Smuzhiyun struct tifm_dev *sock = host->dev;
596*4882a593Smuzhiyun unsigned int data_timeout = data->timeout_clks;
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun if (fixed_timeout)
599*4882a593Smuzhiyun return;
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun data_timeout += data->timeout_ns /
602*4882a593Smuzhiyun ((1000000000UL / host->clk_freq) * host->clk_div);
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun if (data_timeout < 0xffff) {
605*4882a593Smuzhiyun writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
606*4882a593Smuzhiyun writel((~TIFM_MMCSD_DPE)
607*4882a593Smuzhiyun & readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
608*4882a593Smuzhiyun sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
609*4882a593Smuzhiyun } else {
610*4882a593Smuzhiyun data_timeout = (data_timeout >> 10) + 1;
611*4882a593Smuzhiyun if (data_timeout > 0xffff)
612*4882a593Smuzhiyun data_timeout = 0; /* set to unlimited */
613*4882a593Smuzhiyun writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
614*4882a593Smuzhiyun writel(TIFM_MMCSD_DPE
615*4882a593Smuzhiyun | readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
616*4882a593Smuzhiyun sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
617*4882a593Smuzhiyun }
618*4882a593Smuzhiyun }
619*4882a593Smuzhiyun
tifm_sd_request(struct mmc_host * mmc,struct mmc_request * mrq)620*4882a593Smuzhiyun static void tifm_sd_request(struct mmc_host *mmc, struct mmc_request *mrq)
621*4882a593Smuzhiyun {
622*4882a593Smuzhiyun struct tifm_sd *host = mmc_priv(mmc);
623*4882a593Smuzhiyun struct tifm_dev *sock = host->dev;
624*4882a593Smuzhiyun unsigned long flags;
625*4882a593Smuzhiyun struct mmc_data *r_data = mrq->cmd->data;
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun spin_lock_irqsave(&sock->lock, flags);
628*4882a593Smuzhiyun if (host->eject) {
629*4882a593Smuzhiyun mrq->cmd->error = -ENOMEDIUM;
630*4882a593Smuzhiyun goto err_out;
631*4882a593Smuzhiyun }
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun if (host->req) {
634*4882a593Smuzhiyun pr_err("%s : unfinished request detected\n",
635*4882a593Smuzhiyun dev_name(&sock->dev));
636*4882a593Smuzhiyun mrq->cmd->error = -ETIMEDOUT;
637*4882a593Smuzhiyun goto err_out;
638*4882a593Smuzhiyun }
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun host->cmd_flags = 0;
641*4882a593Smuzhiyun host->block_pos = 0;
642*4882a593Smuzhiyun host->sg_pos = 0;
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun if (mrq->data && !is_power_of_2(mrq->data->blksz))
645*4882a593Smuzhiyun host->no_dma = 1;
646*4882a593Smuzhiyun else
647*4882a593Smuzhiyun host->no_dma = no_dma ? 1 : 0;
648*4882a593Smuzhiyun
649*4882a593Smuzhiyun if (r_data) {
650*4882a593Smuzhiyun tifm_sd_set_data_timeout(host, r_data);
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun if ((r_data->flags & MMC_DATA_WRITE) && !mrq->stop)
653*4882a593Smuzhiyun writel(TIFM_MMCSD_EOFB
654*4882a593Smuzhiyun | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
655*4882a593Smuzhiyun sock->addr + SOCK_MMCSD_INT_ENABLE);
656*4882a593Smuzhiyun
657*4882a593Smuzhiyun if (host->no_dma) {
658*4882a593Smuzhiyun writel(TIFM_MMCSD_BUFINT
659*4882a593Smuzhiyun | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
660*4882a593Smuzhiyun sock->addr + SOCK_MMCSD_INT_ENABLE);
661*4882a593Smuzhiyun writel(((TIFM_MMCSD_FIFO_SIZE - 1) << 8)
662*4882a593Smuzhiyun | (TIFM_MMCSD_FIFO_SIZE - 1),
663*4882a593Smuzhiyun sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun host->sg_len = r_data->sg_len;
666*4882a593Smuzhiyun } else {
667*4882a593Smuzhiyun sg_init_one(&host->bounce_buf, host->bounce_buf_data,
668*4882a593Smuzhiyun r_data->blksz);
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun if(1 != tifm_map_sg(sock, &host->bounce_buf, 1,
671*4882a593Smuzhiyun r_data->flags & MMC_DATA_WRITE
672*4882a593Smuzhiyun ? PCI_DMA_TODEVICE
673*4882a593Smuzhiyun : PCI_DMA_FROMDEVICE)) {
674*4882a593Smuzhiyun pr_err("%s : scatterlist map failed\n",
675*4882a593Smuzhiyun dev_name(&sock->dev));
676*4882a593Smuzhiyun mrq->cmd->error = -ENOMEM;
677*4882a593Smuzhiyun goto err_out;
678*4882a593Smuzhiyun }
679*4882a593Smuzhiyun host->sg_len = tifm_map_sg(sock, r_data->sg,
680*4882a593Smuzhiyun r_data->sg_len,
681*4882a593Smuzhiyun r_data->flags
682*4882a593Smuzhiyun & MMC_DATA_WRITE
683*4882a593Smuzhiyun ? PCI_DMA_TODEVICE
684*4882a593Smuzhiyun : PCI_DMA_FROMDEVICE);
685*4882a593Smuzhiyun if (host->sg_len < 1) {
686*4882a593Smuzhiyun pr_err("%s : scatterlist map failed\n",
687*4882a593Smuzhiyun dev_name(&sock->dev));
688*4882a593Smuzhiyun tifm_unmap_sg(sock, &host->bounce_buf, 1,
689*4882a593Smuzhiyun r_data->flags & MMC_DATA_WRITE
690*4882a593Smuzhiyun ? PCI_DMA_TODEVICE
691*4882a593Smuzhiyun : PCI_DMA_FROMDEVICE);
692*4882a593Smuzhiyun mrq->cmd->error = -ENOMEM;
693*4882a593Smuzhiyun goto err_out;
694*4882a593Smuzhiyun }
695*4882a593Smuzhiyun
696*4882a593Smuzhiyun writel(TIFM_FIFO_INT_SETALL,
697*4882a593Smuzhiyun sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
698*4882a593Smuzhiyun writel(ilog2(r_data->blksz) - 2,
699*4882a593Smuzhiyun sock->addr + SOCK_FIFO_PAGE_SIZE);
700*4882a593Smuzhiyun writel(TIFM_FIFO_ENABLE,
701*4882a593Smuzhiyun sock->addr + SOCK_FIFO_CONTROL);
702*4882a593Smuzhiyun writel(TIFM_FIFO_INTMASK,
703*4882a593Smuzhiyun sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun if (r_data->flags & MMC_DATA_WRITE)
706*4882a593Smuzhiyun writel(TIFM_MMCSD_TXDE,
707*4882a593Smuzhiyun sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
708*4882a593Smuzhiyun else
709*4882a593Smuzhiyun writel(TIFM_MMCSD_RXDE,
710*4882a593Smuzhiyun sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun tifm_sd_set_dma_data(host, r_data);
713*4882a593Smuzhiyun }
714*4882a593Smuzhiyun
715*4882a593Smuzhiyun writel(r_data->blocks - 1,
716*4882a593Smuzhiyun sock->addr + SOCK_MMCSD_NUM_BLOCKS);
717*4882a593Smuzhiyun writel(r_data->blksz - 1,
718*4882a593Smuzhiyun sock->addr + SOCK_MMCSD_BLOCK_LEN);
719*4882a593Smuzhiyun }
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun host->req = mrq;
722*4882a593Smuzhiyun mod_timer(&host->timer, jiffies + host->timeout_jiffies);
723*4882a593Smuzhiyun writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
724*4882a593Smuzhiyun sock->addr + SOCK_CONTROL);
725*4882a593Smuzhiyun tifm_sd_exec(host, mrq->cmd);
726*4882a593Smuzhiyun spin_unlock_irqrestore(&sock->lock, flags);
727*4882a593Smuzhiyun return;
728*4882a593Smuzhiyun
729*4882a593Smuzhiyun err_out:
730*4882a593Smuzhiyun spin_unlock_irqrestore(&sock->lock, flags);
731*4882a593Smuzhiyun mmc_request_done(mmc, mrq);
732*4882a593Smuzhiyun }
733*4882a593Smuzhiyun
tifm_sd_end_cmd(unsigned long data)734*4882a593Smuzhiyun static void tifm_sd_end_cmd(unsigned long data)
735*4882a593Smuzhiyun {
736*4882a593Smuzhiyun struct tifm_sd *host = (struct tifm_sd*)data;
737*4882a593Smuzhiyun struct tifm_dev *sock = host->dev;
738*4882a593Smuzhiyun struct mmc_host *mmc = tifm_get_drvdata(sock);
739*4882a593Smuzhiyun struct mmc_request *mrq;
740*4882a593Smuzhiyun struct mmc_data *r_data = NULL;
741*4882a593Smuzhiyun unsigned long flags;
742*4882a593Smuzhiyun
743*4882a593Smuzhiyun spin_lock_irqsave(&sock->lock, flags);
744*4882a593Smuzhiyun
745*4882a593Smuzhiyun del_timer(&host->timer);
746*4882a593Smuzhiyun mrq = host->req;
747*4882a593Smuzhiyun host->req = NULL;
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun if (!mrq) {
750*4882a593Smuzhiyun pr_err(" %s : no request to complete?\n",
751*4882a593Smuzhiyun dev_name(&sock->dev));
752*4882a593Smuzhiyun spin_unlock_irqrestore(&sock->lock, flags);
753*4882a593Smuzhiyun return;
754*4882a593Smuzhiyun }
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun r_data = mrq->cmd->data;
757*4882a593Smuzhiyun if (r_data) {
758*4882a593Smuzhiyun if (host->no_dma) {
759*4882a593Smuzhiyun writel((~TIFM_MMCSD_BUFINT)
760*4882a593Smuzhiyun & readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
761*4882a593Smuzhiyun sock->addr + SOCK_MMCSD_INT_ENABLE);
762*4882a593Smuzhiyun } else {
763*4882a593Smuzhiyun tifm_unmap_sg(sock, &host->bounce_buf, 1,
764*4882a593Smuzhiyun (r_data->flags & MMC_DATA_WRITE)
765*4882a593Smuzhiyun ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
766*4882a593Smuzhiyun tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
767*4882a593Smuzhiyun (r_data->flags & MMC_DATA_WRITE)
768*4882a593Smuzhiyun ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
769*4882a593Smuzhiyun }
770*4882a593Smuzhiyun
771*4882a593Smuzhiyun r_data->bytes_xfered = r_data->blocks
772*4882a593Smuzhiyun - readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
773*4882a593Smuzhiyun r_data->bytes_xfered *= r_data->blksz;
774*4882a593Smuzhiyun r_data->bytes_xfered += r_data->blksz
775*4882a593Smuzhiyun - readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
776*4882a593Smuzhiyun }
777*4882a593Smuzhiyun
778*4882a593Smuzhiyun writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
779*4882a593Smuzhiyun sock->addr + SOCK_CONTROL);
780*4882a593Smuzhiyun
781*4882a593Smuzhiyun spin_unlock_irqrestore(&sock->lock, flags);
782*4882a593Smuzhiyun mmc_request_done(mmc, mrq);
783*4882a593Smuzhiyun }
784*4882a593Smuzhiyun
tifm_sd_abort(struct timer_list * t)785*4882a593Smuzhiyun static void tifm_sd_abort(struct timer_list *t)
786*4882a593Smuzhiyun {
787*4882a593Smuzhiyun struct tifm_sd *host = from_timer(host, t, timer);
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun pr_err("%s : card failed to respond for a long period of time "
790*4882a593Smuzhiyun "(%x, %x)\n",
791*4882a593Smuzhiyun dev_name(&host->dev->dev), host->req->cmd->opcode, host->cmd_flags);
792*4882a593Smuzhiyun
793*4882a593Smuzhiyun tifm_eject(host->dev);
794*4882a593Smuzhiyun }
795*4882a593Smuzhiyun
tifm_sd_ios(struct mmc_host * mmc,struct mmc_ios * ios)796*4882a593Smuzhiyun static void tifm_sd_ios(struct mmc_host *mmc, struct mmc_ios *ios)
797*4882a593Smuzhiyun {
798*4882a593Smuzhiyun struct tifm_sd *host = mmc_priv(mmc);
799*4882a593Smuzhiyun struct tifm_dev *sock = host->dev;
800*4882a593Smuzhiyun unsigned int clk_div1, clk_div2;
801*4882a593Smuzhiyun unsigned long flags;
802*4882a593Smuzhiyun
803*4882a593Smuzhiyun spin_lock_irqsave(&sock->lock, flags);
804*4882a593Smuzhiyun
805*4882a593Smuzhiyun dev_dbg(&sock->dev, "ios: clock = %u, vdd = %x, bus_mode = %x, "
806*4882a593Smuzhiyun "chip_select = %x, power_mode = %x, bus_width = %x\n",
807*4882a593Smuzhiyun ios->clock, ios->vdd, ios->bus_mode, ios->chip_select,
808*4882a593Smuzhiyun ios->power_mode, ios->bus_width);
809*4882a593Smuzhiyun
810*4882a593Smuzhiyun if (ios->bus_width == MMC_BUS_WIDTH_4) {
811*4882a593Smuzhiyun writel(TIFM_MMCSD_4BBUS | readl(sock->addr + SOCK_MMCSD_CONFIG),
812*4882a593Smuzhiyun sock->addr + SOCK_MMCSD_CONFIG);
813*4882a593Smuzhiyun } else {
814*4882a593Smuzhiyun writel((~TIFM_MMCSD_4BBUS)
815*4882a593Smuzhiyun & readl(sock->addr + SOCK_MMCSD_CONFIG),
816*4882a593Smuzhiyun sock->addr + SOCK_MMCSD_CONFIG);
817*4882a593Smuzhiyun }
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun if (ios->clock) {
820*4882a593Smuzhiyun clk_div1 = 20000000 / ios->clock;
821*4882a593Smuzhiyun if (!clk_div1)
822*4882a593Smuzhiyun clk_div1 = 1;
823*4882a593Smuzhiyun
824*4882a593Smuzhiyun clk_div2 = 24000000 / ios->clock;
825*4882a593Smuzhiyun if (!clk_div2)
826*4882a593Smuzhiyun clk_div2 = 1;
827*4882a593Smuzhiyun
828*4882a593Smuzhiyun if ((20000000 / clk_div1) > ios->clock)
829*4882a593Smuzhiyun clk_div1++;
830*4882a593Smuzhiyun if ((24000000 / clk_div2) > ios->clock)
831*4882a593Smuzhiyun clk_div2++;
832*4882a593Smuzhiyun if ((20000000 / clk_div1) > (24000000 / clk_div2)) {
833*4882a593Smuzhiyun host->clk_freq = 20000000;
834*4882a593Smuzhiyun host->clk_div = clk_div1;
835*4882a593Smuzhiyun writel((~TIFM_CTRL_FAST_CLK)
836*4882a593Smuzhiyun & readl(sock->addr + SOCK_CONTROL),
837*4882a593Smuzhiyun sock->addr + SOCK_CONTROL);
838*4882a593Smuzhiyun } else {
839*4882a593Smuzhiyun host->clk_freq = 24000000;
840*4882a593Smuzhiyun host->clk_div = clk_div2;
841*4882a593Smuzhiyun writel(TIFM_CTRL_FAST_CLK
842*4882a593Smuzhiyun | readl(sock->addr + SOCK_CONTROL),
843*4882a593Smuzhiyun sock->addr + SOCK_CONTROL);
844*4882a593Smuzhiyun }
845*4882a593Smuzhiyun } else {
846*4882a593Smuzhiyun host->clk_div = 0;
847*4882a593Smuzhiyun }
848*4882a593Smuzhiyun host->clk_div &= TIFM_MMCSD_CLKMASK;
849*4882a593Smuzhiyun writel(host->clk_div
850*4882a593Smuzhiyun | ((~TIFM_MMCSD_CLKMASK)
851*4882a593Smuzhiyun & readl(sock->addr + SOCK_MMCSD_CONFIG)),
852*4882a593Smuzhiyun sock->addr + SOCK_MMCSD_CONFIG);
853*4882a593Smuzhiyun
854*4882a593Smuzhiyun host->open_drain = (ios->bus_mode == MMC_BUSMODE_OPENDRAIN);
855*4882a593Smuzhiyun
856*4882a593Smuzhiyun /* chip_select : maybe later */
857*4882a593Smuzhiyun //vdd
858*4882a593Smuzhiyun //power is set before probe / after remove
859*4882a593Smuzhiyun
860*4882a593Smuzhiyun spin_unlock_irqrestore(&sock->lock, flags);
861*4882a593Smuzhiyun }
862*4882a593Smuzhiyun
tifm_sd_ro(struct mmc_host * mmc)863*4882a593Smuzhiyun static int tifm_sd_ro(struct mmc_host *mmc)
864*4882a593Smuzhiyun {
865*4882a593Smuzhiyun int rc = 0;
866*4882a593Smuzhiyun struct tifm_sd *host = mmc_priv(mmc);
867*4882a593Smuzhiyun struct tifm_dev *sock = host->dev;
868*4882a593Smuzhiyun unsigned long flags;
869*4882a593Smuzhiyun
870*4882a593Smuzhiyun spin_lock_irqsave(&sock->lock, flags);
871*4882a593Smuzhiyun if (TIFM_MMCSD_CARD_RO & readl(sock->addr + SOCK_PRESENT_STATE))
872*4882a593Smuzhiyun rc = 1;
873*4882a593Smuzhiyun spin_unlock_irqrestore(&sock->lock, flags);
874*4882a593Smuzhiyun return rc;
875*4882a593Smuzhiyun }
876*4882a593Smuzhiyun
877*4882a593Smuzhiyun static const struct mmc_host_ops tifm_sd_ops = {
878*4882a593Smuzhiyun .request = tifm_sd_request,
879*4882a593Smuzhiyun .set_ios = tifm_sd_ios,
880*4882a593Smuzhiyun .get_ro = tifm_sd_ro
881*4882a593Smuzhiyun };
882*4882a593Smuzhiyun
tifm_sd_initialize_host(struct tifm_sd * host)883*4882a593Smuzhiyun static int tifm_sd_initialize_host(struct tifm_sd *host)
884*4882a593Smuzhiyun {
885*4882a593Smuzhiyun int rc;
886*4882a593Smuzhiyun unsigned int host_status = 0;
887*4882a593Smuzhiyun struct tifm_dev *sock = host->dev;
888*4882a593Smuzhiyun
889*4882a593Smuzhiyun writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
890*4882a593Smuzhiyun host->clk_div = 61;
891*4882a593Smuzhiyun host->clk_freq = 20000000;
892*4882a593Smuzhiyun writel(TIFM_MMCSD_RESET, sock->addr + SOCK_MMCSD_SYSTEM_CONTROL);
893*4882a593Smuzhiyun writel(host->clk_div | TIFM_MMCSD_POWER,
894*4882a593Smuzhiyun sock->addr + SOCK_MMCSD_CONFIG);
895*4882a593Smuzhiyun
896*4882a593Smuzhiyun /* wait up to 0.51 sec for reset */
897*4882a593Smuzhiyun for (rc = 32; rc <= 256; rc <<= 1) {
898*4882a593Smuzhiyun if (1 & readl(sock->addr + SOCK_MMCSD_SYSTEM_STATUS)) {
899*4882a593Smuzhiyun rc = 0;
900*4882a593Smuzhiyun break;
901*4882a593Smuzhiyun }
902*4882a593Smuzhiyun msleep(rc);
903*4882a593Smuzhiyun }
904*4882a593Smuzhiyun
905*4882a593Smuzhiyun if (rc) {
906*4882a593Smuzhiyun pr_err("%s : controller failed to reset\n",
907*4882a593Smuzhiyun dev_name(&sock->dev));
908*4882a593Smuzhiyun return -ENODEV;
909*4882a593Smuzhiyun }
910*4882a593Smuzhiyun
911*4882a593Smuzhiyun writel(0, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
912*4882a593Smuzhiyun writel(host->clk_div | TIFM_MMCSD_POWER,
913*4882a593Smuzhiyun sock->addr + SOCK_MMCSD_CONFIG);
914*4882a593Smuzhiyun writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun // command timeout fixed to 64 clocks for now
917*4882a593Smuzhiyun writel(64, sock->addr + SOCK_MMCSD_COMMAND_TO);
918*4882a593Smuzhiyun writel(TIFM_MMCSD_INAB, sock->addr + SOCK_MMCSD_COMMAND);
919*4882a593Smuzhiyun
920*4882a593Smuzhiyun for (rc = 16; rc <= 64; rc <<= 1) {
921*4882a593Smuzhiyun host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
922*4882a593Smuzhiyun writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
923*4882a593Smuzhiyun if (!(host_status & TIFM_MMCSD_ERRMASK)
924*4882a593Smuzhiyun && (host_status & TIFM_MMCSD_EOC)) {
925*4882a593Smuzhiyun rc = 0;
926*4882a593Smuzhiyun break;
927*4882a593Smuzhiyun }
928*4882a593Smuzhiyun msleep(rc);
929*4882a593Smuzhiyun }
930*4882a593Smuzhiyun
931*4882a593Smuzhiyun if (rc) {
932*4882a593Smuzhiyun pr_err("%s : card not ready - probe failed on initialization\n",
933*4882a593Smuzhiyun dev_name(&sock->dev));
934*4882a593Smuzhiyun return -ENODEV;
935*4882a593Smuzhiyun }
936*4882a593Smuzhiyun
937*4882a593Smuzhiyun writel(TIFM_MMCSD_CERR | TIFM_MMCSD_BRS | TIFM_MMCSD_EOC
938*4882a593Smuzhiyun | TIFM_MMCSD_ERRMASK,
939*4882a593Smuzhiyun sock->addr + SOCK_MMCSD_INT_ENABLE);
940*4882a593Smuzhiyun
941*4882a593Smuzhiyun return 0;
942*4882a593Smuzhiyun }
943*4882a593Smuzhiyun
tifm_sd_probe(struct tifm_dev * sock)944*4882a593Smuzhiyun static int tifm_sd_probe(struct tifm_dev *sock)
945*4882a593Smuzhiyun {
946*4882a593Smuzhiyun struct mmc_host *mmc;
947*4882a593Smuzhiyun struct tifm_sd *host;
948*4882a593Smuzhiyun int rc = -EIO;
949*4882a593Smuzhiyun
950*4882a593Smuzhiyun if (!(TIFM_SOCK_STATE_OCCUPIED
951*4882a593Smuzhiyun & readl(sock->addr + SOCK_PRESENT_STATE))) {
952*4882a593Smuzhiyun pr_warn("%s : card gone, unexpectedly\n",
953*4882a593Smuzhiyun dev_name(&sock->dev));
954*4882a593Smuzhiyun return rc;
955*4882a593Smuzhiyun }
956*4882a593Smuzhiyun
957*4882a593Smuzhiyun mmc = mmc_alloc_host(sizeof(struct tifm_sd), &sock->dev);
958*4882a593Smuzhiyun if (!mmc)
959*4882a593Smuzhiyun return -ENOMEM;
960*4882a593Smuzhiyun
961*4882a593Smuzhiyun host = mmc_priv(mmc);
962*4882a593Smuzhiyun tifm_set_drvdata(sock, mmc);
963*4882a593Smuzhiyun host->dev = sock;
964*4882a593Smuzhiyun host->timeout_jiffies = msecs_to_jiffies(TIFM_MMCSD_REQ_TIMEOUT_MS);
965*4882a593Smuzhiyun /*
966*4882a593Smuzhiyun * We use a fixed request timeout of 1s, hence inform the core about it.
967*4882a593Smuzhiyun * A future improvement should instead respect the cmd->busy_timeout.
968*4882a593Smuzhiyun */
969*4882a593Smuzhiyun mmc->max_busy_timeout = TIFM_MMCSD_REQ_TIMEOUT_MS;
970*4882a593Smuzhiyun
971*4882a593Smuzhiyun tasklet_init(&host->finish_tasklet, tifm_sd_end_cmd,
972*4882a593Smuzhiyun (unsigned long)host);
973*4882a593Smuzhiyun timer_setup(&host->timer, tifm_sd_abort, 0);
974*4882a593Smuzhiyun
975*4882a593Smuzhiyun mmc->ops = &tifm_sd_ops;
976*4882a593Smuzhiyun mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
977*4882a593Smuzhiyun mmc->caps = MMC_CAP_4_BIT_DATA;
978*4882a593Smuzhiyun mmc->f_min = 20000000 / 60;
979*4882a593Smuzhiyun mmc->f_max = 24000000;
980*4882a593Smuzhiyun
981*4882a593Smuzhiyun mmc->max_blk_count = 2048;
982*4882a593Smuzhiyun mmc->max_segs = mmc->max_blk_count;
983*4882a593Smuzhiyun mmc->max_blk_size = min(TIFM_MMCSD_MAX_BLOCK_SIZE, PAGE_SIZE);
984*4882a593Smuzhiyun mmc->max_seg_size = mmc->max_blk_count * mmc->max_blk_size;
985*4882a593Smuzhiyun mmc->max_req_size = mmc->max_seg_size;
986*4882a593Smuzhiyun
987*4882a593Smuzhiyun sock->card_event = tifm_sd_card_event;
988*4882a593Smuzhiyun sock->data_event = tifm_sd_data_event;
989*4882a593Smuzhiyun rc = tifm_sd_initialize_host(host);
990*4882a593Smuzhiyun
991*4882a593Smuzhiyun if (!rc)
992*4882a593Smuzhiyun rc = mmc_add_host(mmc);
993*4882a593Smuzhiyun if (!rc)
994*4882a593Smuzhiyun return 0;
995*4882a593Smuzhiyun
996*4882a593Smuzhiyun mmc_free_host(mmc);
997*4882a593Smuzhiyun return rc;
998*4882a593Smuzhiyun }
999*4882a593Smuzhiyun
tifm_sd_remove(struct tifm_dev * sock)1000*4882a593Smuzhiyun static void tifm_sd_remove(struct tifm_dev *sock)
1001*4882a593Smuzhiyun {
1002*4882a593Smuzhiyun struct mmc_host *mmc = tifm_get_drvdata(sock);
1003*4882a593Smuzhiyun struct tifm_sd *host = mmc_priv(mmc);
1004*4882a593Smuzhiyun unsigned long flags;
1005*4882a593Smuzhiyun
1006*4882a593Smuzhiyun spin_lock_irqsave(&sock->lock, flags);
1007*4882a593Smuzhiyun host->eject = 1;
1008*4882a593Smuzhiyun writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
1009*4882a593Smuzhiyun spin_unlock_irqrestore(&sock->lock, flags);
1010*4882a593Smuzhiyun
1011*4882a593Smuzhiyun tasklet_kill(&host->finish_tasklet);
1012*4882a593Smuzhiyun
1013*4882a593Smuzhiyun spin_lock_irqsave(&sock->lock, flags);
1014*4882a593Smuzhiyun if (host->req) {
1015*4882a593Smuzhiyun writel(TIFM_FIFO_INT_SETALL,
1016*4882a593Smuzhiyun sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
1017*4882a593Smuzhiyun writel(0, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
1018*4882a593Smuzhiyun host->req->cmd->error = -ENOMEDIUM;
1019*4882a593Smuzhiyun if (host->req->stop)
1020*4882a593Smuzhiyun host->req->stop->error = -ENOMEDIUM;
1021*4882a593Smuzhiyun tasklet_schedule(&host->finish_tasklet);
1022*4882a593Smuzhiyun }
1023*4882a593Smuzhiyun spin_unlock_irqrestore(&sock->lock, flags);
1024*4882a593Smuzhiyun mmc_remove_host(mmc);
1025*4882a593Smuzhiyun dev_dbg(&sock->dev, "after remove\n");
1026*4882a593Smuzhiyun
1027*4882a593Smuzhiyun mmc_free_host(mmc);
1028*4882a593Smuzhiyun }
1029*4882a593Smuzhiyun
1030*4882a593Smuzhiyun #ifdef CONFIG_PM
1031*4882a593Smuzhiyun
tifm_sd_suspend(struct tifm_dev * sock,pm_message_t state)1032*4882a593Smuzhiyun static int tifm_sd_suspend(struct tifm_dev *sock, pm_message_t state)
1033*4882a593Smuzhiyun {
1034*4882a593Smuzhiyun return 0;
1035*4882a593Smuzhiyun }
1036*4882a593Smuzhiyun
tifm_sd_resume(struct tifm_dev * sock)1037*4882a593Smuzhiyun static int tifm_sd_resume(struct tifm_dev *sock)
1038*4882a593Smuzhiyun {
1039*4882a593Smuzhiyun struct mmc_host *mmc = tifm_get_drvdata(sock);
1040*4882a593Smuzhiyun struct tifm_sd *host = mmc_priv(mmc);
1041*4882a593Smuzhiyun int rc;
1042*4882a593Smuzhiyun
1043*4882a593Smuzhiyun rc = tifm_sd_initialize_host(host);
1044*4882a593Smuzhiyun dev_dbg(&sock->dev, "resume initialize %d\n", rc);
1045*4882a593Smuzhiyun
1046*4882a593Smuzhiyun if (rc)
1047*4882a593Smuzhiyun host->eject = 1;
1048*4882a593Smuzhiyun
1049*4882a593Smuzhiyun return rc;
1050*4882a593Smuzhiyun }
1051*4882a593Smuzhiyun
1052*4882a593Smuzhiyun #else
1053*4882a593Smuzhiyun
1054*4882a593Smuzhiyun #define tifm_sd_suspend NULL
1055*4882a593Smuzhiyun #define tifm_sd_resume NULL
1056*4882a593Smuzhiyun
1057*4882a593Smuzhiyun #endif /* CONFIG_PM */
1058*4882a593Smuzhiyun
1059*4882a593Smuzhiyun static struct tifm_device_id tifm_sd_id_tbl[] = {
1060*4882a593Smuzhiyun { TIFM_TYPE_SD }, { }
1061*4882a593Smuzhiyun };
1062*4882a593Smuzhiyun
1063*4882a593Smuzhiyun static struct tifm_driver tifm_sd_driver = {
1064*4882a593Smuzhiyun .driver = {
1065*4882a593Smuzhiyun .name = DRIVER_NAME,
1066*4882a593Smuzhiyun .owner = THIS_MODULE
1067*4882a593Smuzhiyun },
1068*4882a593Smuzhiyun .id_table = tifm_sd_id_tbl,
1069*4882a593Smuzhiyun .probe = tifm_sd_probe,
1070*4882a593Smuzhiyun .remove = tifm_sd_remove,
1071*4882a593Smuzhiyun .suspend = tifm_sd_suspend,
1072*4882a593Smuzhiyun .resume = tifm_sd_resume
1073*4882a593Smuzhiyun };
1074*4882a593Smuzhiyun
tifm_sd_init(void)1075*4882a593Smuzhiyun static int __init tifm_sd_init(void)
1076*4882a593Smuzhiyun {
1077*4882a593Smuzhiyun return tifm_register_driver(&tifm_sd_driver);
1078*4882a593Smuzhiyun }
1079*4882a593Smuzhiyun
tifm_sd_exit(void)1080*4882a593Smuzhiyun static void __exit tifm_sd_exit(void)
1081*4882a593Smuzhiyun {
1082*4882a593Smuzhiyun tifm_unregister_driver(&tifm_sd_driver);
1083*4882a593Smuzhiyun }
1084*4882a593Smuzhiyun
1085*4882a593Smuzhiyun MODULE_AUTHOR("Alex Dubov");
1086*4882a593Smuzhiyun MODULE_DESCRIPTION("TI FlashMedia SD driver");
1087*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1088*4882a593Smuzhiyun MODULE_DEVICE_TABLE(tifm, tifm_sd_id_tbl);
1089*4882a593Smuzhiyun MODULE_VERSION(DRIVER_VERSION);
1090*4882a593Smuzhiyun
1091*4882a593Smuzhiyun module_init(tifm_sd_init);
1092*4882a593Smuzhiyun module_exit(tifm_sd_exit);
1093