1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2010 MontaVista Software, LLC.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #ifndef _DRIVERS_MMC_SDHCI_PLTFM_H
9*4882a593Smuzhiyun #define _DRIVERS_MMC_SDHCI_PLTFM_H
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/clk.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun #include "sdhci.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun struct sdhci_pltfm_data {
16*4882a593Smuzhiyun const struct sdhci_ops *ops;
17*4882a593Smuzhiyun unsigned int quirks;
18*4882a593Smuzhiyun unsigned int quirks2;
19*4882a593Smuzhiyun };
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun struct sdhci_pltfm_host {
22*4882a593Smuzhiyun struct clk *clk;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* migrate from sdhci_of_host */
25*4882a593Smuzhiyun unsigned int clock;
26*4882a593Smuzhiyun u16 xfer_mode_shadow;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun unsigned long private[] ____cacheline_aligned;
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #ifdef CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER
32*4882a593Smuzhiyun /*
33*4882a593Smuzhiyun * These accessors are designed for big endian hosts doing I/O to
34*4882a593Smuzhiyun * little endian controllers incorporating a 32-bit hardware byte swapper.
35*4882a593Smuzhiyun */
sdhci_be32bs_readl(struct sdhci_host * host,int reg)36*4882a593Smuzhiyun static inline u32 sdhci_be32bs_readl(struct sdhci_host *host, int reg)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun return in_be32(host->ioaddr + reg);
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
sdhci_be32bs_readw(struct sdhci_host * host,int reg)41*4882a593Smuzhiyun static inline u16 sdhci_be32bs_readw(struct sdhci_host *host, int reg)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun return in_be16(host->ioaddr + (reg ^ 0x2));
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
sdhci_be32bs_readb(struct sdhci_host * host,int reg)46*4882a593Smuzhiyun static inline u8 sdhci_be32bs_readb(struct sdhci_host *host, int reg)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun return in_8(host->ioaddr + (reg ^ 0x3));
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
sdhci_be32bs_writel(struct sdhci_host * host,u32 val,int reg)51*4882a593Smuzhiyun static inline void sdhci_be32bs_writel(struct sdhci_host *host,
52*4882a593Smuzhiyun u32 val, int reg)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun out_be32(host->ioaddr + reg, val);
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
sdhci_be32bs_writew(struct sdhci_host * host,u16 val,int reg)57*4882a593Smuzhiyun static inline void sdhci_be32bs_writew(struct sdhci_host *host,
58*4882a593Smuzhiyun u16 val, int reg)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
61*4882a593Smuzhiyun int base = reg & ~0x3;
62*4882a593Smuzhiyun int shift = (reg & 0x2) * 8;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun switch (reg) {
65*4882a593Smuzhiyun case SDHCI_TRANSFER_MODE:
66*4882a593Smuzhiyun /*
67*4882a593Smuzhiyun * Postpone this write, we must do it together with a
68*4882a593Smuzhiyun * command write that is down below.
69*4882a593Smuzhiyun */
70*4882a593Smuzhiyun pltfm_host->xfer_mode_shadow = val;
71*4882a593Smuzhiyun return;
72*4882a593Smuzhiyun case SDHCI_COMMAND:
73*4882a593Smuzhiyun sdhci_be32bs_writel(host,
74*4882a593Smuzhiyun val << 16 | pltfm_host->xfer_mode_shadow,
75*4882a593Smuzhiyun SDHCI_TRANSFER_MODE);
76*4882a593Smuzhiyun return;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift);
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
sdhci_be32bs_writeb(struct sdhci_host * host,u8 val,int reg)81*4882a593Smuzhiyun static inline void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun int base = reg & ~0x3;
84*4882a593Smuzhiyun int shift = (reg & 0x3) * 8;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift);
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun #endif /* CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER */
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun void sdhci_get_property(struct platform_device *pdev);
91*4882a593Smuzhiyun
sdhci_get_of_property(struct platform_device * pdev)92*4882a593Smuzhiyun static inline void sdhci_get_of_property(struct platform_device *pdev)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun return sdhci_get_property(pdev);
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun extern struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev,
98*4882a593Smuzhiyun const struct sdhci_pltfm_data *pdata,
99*4882a593Smuzhiyun size_t priv_size);
100*4882a593Smuzhiyun extern void sdhci_pltfm_free(struct platform_device *pdev);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun extern int sdhci_pltfm_register(struct platform_device *pdev,
103*4882a593Smuzhiyun const struct sdhci_pltfm_data *pdata,
104*4882a593Smuzhiyun size_t priv_size);
105*4882a593Smuzhiyun extern int sdhci_pltfm_unregister(struct platform_device *pdev);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun extern unsigned int sdhci_pltfm_clk_get_max_clock(struct sdhci_host *host);
108*4882a593Smuzhiyun
sdhci_pltfm_priv(struct sdhci_pltfm_host * host)109*4882a593Smuzhiyun static inline void *sdhci_pltfm_priv(struct sdhci_pltfm_host *host)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun return host->private;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun extern const struct dev_pm_ops sdhci_pltfm_pmops;
115*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
116*4882a593Smuzhiyun int sdhci_pltfm_suspend(struct device *dev);
117*4882a593Smuzhiyun int sdhci_pltfm_resume(struct device *dev);
118*4882a593Smuzhiyun #else
sdhci_pltfm_suspend(struct device * dev)119*4882a593Smuzhiyun static inline int sdhci_pltfm_suspend(struct device *dev) { return 0; }
sdhci_pltfm_resume(struct device * dev)120*4882a593Smuzhiyun static inline int sdhci_pltfm_resume(struct device *dev) { return 0; }
121*4882a593Smuzhiyun #endif
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun #endif /* _DRIVERS_MMC_SDHCI_PLTFM_H */
124