xref: /OK3568_Linux_fs/kernel/drivers/mmc/host/sdhci-of-aspeed.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /* Copyright (C) 2019 ASPEED Technology Inc. */
3*4882a593Smuzhiyun /* Copyright (C) 2019 IBM Corp. */
4*4882a593Smuzhiyun 
5*4882a593Smuzhiyun #include <linux/clk.h>
6*4882a593Smuzhiyun #include <linux/delay.h>
7*4882a593Smuzhiyun #include <linux/device.h>
8*4882a593Smuzhiyun #include <linux/io.h>
9*4882a593Smuzhiyun #include <linux/mmc/host.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/of_address.h>
12*4882a593Smuzhiyun #include <linux/of.h>
13*4882a593Smuzhiyun #include <linux/of_platform.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <linux/spinlock.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include "sdhci-pltfm.h"
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #define ASPEED_SDC_INFO		0x00
20*4882a593Smuzhiyun #define   ASPEED_SDC_S1MMC8	BIT(25)
21*4882a593Smuzhiyun #define   ASPEED_SDC_S0MMC8	BIT(24)
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun struct aspeed_sdc {
24*4882a593Smuzhiyun 	struct clk *clk;
25*4882a593Smuzhiyun 	struct resource *res;
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun 	spinlock_t lock;
28*4882a593Smuzhiyun 	void __iomem *regs;
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun struct aspeed_sdhci {
32*4882a593Smuzhiyun 	struct aspeed_sdc *parent;
33*4882a593Smuzhiyun 	u32 width_mask;
34*4882a593Smuzhiyun };
35*4882a593Smuzhiyun 
aspeed_sdc_configure_8bit_mode(struct aspeed_sdc * sdc,struct aspeed_sdhci * sdhci,bool bus8)36*4882a593Smuzhiyun static void aspeed_sdc_configure_8bit_mode(struct aspeed_sdc *sdc,
37*4882a593Smuzhiyun 					   struct aspeed_sdhci *sdhci,
38*4882a593Smuzhiyun 					   bool bus8)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun 	u32 info;
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun 	/* Set/clear 8 bit mode */
43*4882a593Smuzhiyun 	spin_lock(&sdc->lock);
44*4882a593Smuzhiyun 	info = readl(sdc->regs + ASPEED_SDC_INFO);
45*4882a593Smuzhiyun 	if (bus8)
46*4882a593Smuzhiyun 		info |= sdhci->width_mask;
47*4882a593Smuzhiyun 	else
48*4882a593Smuzhiyun 		info &= ~sdhci->width_mask;
49*4882a593Smuzhiyun 	writel(info, sdc->regs + ASPEED_SDC_INFO);
50*4882a593Smuzhiyun 	spin_unlock(&sdc->lock);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun 
aspeed_sdhci_set_clock(struct sdhci_host * host,unsigned int clock)53*4882a593Smuzhiyun static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun 	struct sdhci_pltfm_host *pltfm_host;
56*4882a593Smuzhiyun 	unsigned long parent;
57*4882a593Smuzhiyun 	int div;
58*4882a593Smuzhiyun 	u16 clk;
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun 	pltfm_host = sdhci_priv(host);
61*4882a593Smuzhiyun 	parent = clk_get_rate(pltfm_host->clk);
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun 	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 	if (clock == 0)
66*4882a593Smuzhiyun 		return;
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun 	if (WARN_ON(clock > host->max_clk))
69*4882a593Smuzhiyun 		clock = host->max_clk;
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 	for (div = 2; div < 256; div *= 2) {
72*4882a593Smuzhiyun 		if ((parent / div) <= clock)
73*4882a593Smuzhiyun 			break;
74*4882a593Smuzhiyun 	}
75*4882a593Smuzhiyun 	div >>= 1;
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	clk = div << SDHCI_DIVIDER_SHIFT;
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	sdhci_enable_clk(host, clk);
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun 
aspeed_sdhci_get_max_clock(struct sdhci_host * host)82*4882a593Smuzhiyun static unsigned int aspeed_sdhci_get_max_clock(struct sdhci_host *host)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun 	if (host->mmc->f_max)
85*4882a593Smuzhiyun 		return host->mmc->f_max;
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	return sdhci_pltfm_clk_get_max_clock(host);
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun 
aspeed_sdhci_set_bus_width(struct sdhci_host * host,int width)90*4882a593Smuzhiyun static void aspeed_sdhci_set_bus_width(struct sdhci_host *host, int width)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun 	struct sdhci_pltfm_host *pltfm_priv;
93*4882a593Smuzhiyun 	struct aspeed_sdhci *aspeed_sdhci;
94*4882a593Smuzhiyun 	struct aspeed_sdc *aspeed_sdc;
95*4882a593Smuzhiyun 	u8 ctrl;
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	pltfm_priv = sdhci_priv(host);
98*4882a593Smuzhiyun 	aspeed_sdhci = sdhci_pltfm_priv(pltfm_priv);
99*4882a593Smuzhiyun 	aspeed_sdc = aspeed_sdhci->parent;
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	/* Set/clear 8-bit mode */
102*4882a593Smuzhiyun 	aspeed_sdc_configure_8bit_mode(aspeed_sdc, aspeed_sdhci,
103*4882a593Smuzhiyun 				       width == MMC_BUS_WIDTH_8);
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	/* Set/clear 1 or 4 bit mode */
106*4882a593Smuzhiyun 	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
107*4882a593Smuzhiyun 	if (width == MMC_BUS_WIDTH_4)
108*4882a593Smuzhiyun 		ctrl |= SDHCI_CTRL_4BITBUS;
109*4882a593Smuzhiyun 	else
110*4882a593Smuzhiyun 		ctrl &= ~SDHCI_CTRL_4BITBUS;
111*4882a593Smuzhiyun 	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun 
aspeed_sdhci_readl(struct sdhci_host * host,int reg)114*4882a593Smuzhiyun static u32 aspeed_sdhci_readl(struct sdhci_host *host, int reg)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun 	u32 val = readl(host->ioaddr + reg);
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	if (unlikely(reg == SDHCI_PRESENT_STATE) &&
119*4882a593Smuzhiyun 	    (host->mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH))
120*4882a593Smuzhiyun 		val ^= SDHCI_CARD_PRESENT;
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	return val;
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun static const struct sdhci_ops aspeed_sdhci_ops = {
126*4882a593Smuzhiyun 	.read_l = aspeed_sdhci_readl,
127*4882a593Smuzhiyun 	.set_clock = aspeed_sdhci_set_clock,
128*4882a593Smuzhiyun 	.get_max_clock = aspeed_sdhci_get_max_clock,
129*4882a593Smuzhiyun 	.set_bus_width = aspeed_sdhci_set_bus_width,
130*4882a593Smuzhiyun 	.get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
131*4882a593Smuzhiyun 	.reset = sdhci_reset,
132*4882a593Smuzhiyun 	.set_uhs_signaling = sdhci_set_uhs_signaling,
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun static const struct sdhci_pltfm_data aspeed_sdhci_pdata = {
136*4882a593Smuzhiyun 	.ops = &aspeed_sdhci_ops,
137*4882a593Smuzhiyun 	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
138*4882a593Smuzhiyun };
139*4882a593Smuzhiyun 
aspeed_sdhci_calculate_slot(struct aspeed_sdhci * dev,struct resource * res)140*4882a593Smuzhiyun static inline int aspeed_sdhci_calculate_slot(struct aspeed_sdhci *dev,
141*4882a593Smuzhiyun 					      struct resource *res)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun 	resource_size_t delta;
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	if (!res || resource_type(res) != IORESOURCE_MEM)
146*4882a593Smuzhiyun 		return -EINVAL;
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	if (res->start < dev->parent->res->start)
149*4882a593Smuzhiyun 		return -EINVAL;
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	delta = res->start - dev->parent->res->start;
152*4882a593Smuzhiyun 	if (delta & (0x100 - 1))
153*4882a593Smuzhiyun 		return -EINVAL;
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	return (delta / 0x100) - 1;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun 
aspeed_sdhci_probe(struct platform_device * pdev)158*4882a593Smuzhiyun static int aspeed_sdhci_probe(struct platform_device *pdev)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun 	struct sdhci_pltfm_host *pltfm_host;
161*4882a593Smuzhiyun 	struct aspeed_sdhci *dev;
162*4882a593Smuzhiyun 	struct sdhci_host *host;
163*4882a593Smuzhiyun 	struct resource *res;
164*4882a593Smuzhiyun 	int slot;
165*4882a593Smuzhiyun 	int ret;
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	host = sdhci_pltfm_init(pdev, &aspeed_sdhci_pdata, sizeof(*dev));
168*4882a593Smuzhiyun 	if (IS_ERR(host))
169*4882a593Smuzhiyun 		return PTR_ERR(host);
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	pltfm_host = sdhci_priv(host);
172*4882a593Smuzhiyun 	dev = sdhci_pltfm_priv(pltfm_host);
173*4882a593Smuzhiyun 	dev->parent = dev_get_drvdata(pdev->dev.parent);
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
176*4882a593Smuzhiyun 	slot = aspeed_sdhci_calculate_slot(dev, res);
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	if (slot < 0)
179*4882a593Smuzhiyun 		return slot;
180*4882a593Smuzhiyun 	else if (slot >= 2)
181*4882a593Smuzhiyun 		return -EINVAL;
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	dev_info(&pdev->dev, "Configuring for slot %d\n", slot);
184*4882a593Smuzhiyun 	dev->width_mask = !slot ? ASPEED_SDC_S0MMC8 : ASPEED_SDC_S1MMC8;
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	sdhci_get_of_property(pdev);
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	pltfm_host->clk = devm_clk_get(&pdev->dev, NULL);
189*4882a593Smuzhiyun 	if (IS_ERR(pltfm_host->clk))
190*4882a593Smuzhiyun 		return PTR_ERR(pltfm_host->clk);
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 	ret = clk_prepare_enable(pltfm_host->clk);
193*4882a593Smuzhiyun 	if (ret) {
194*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Unable to enable SDIO clock\n");
195*4882a593Smuzhiyun 		goto err_pltfm_free;
196*4882a593Smuzhiyun 	}
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	ret = mmc_of_parse(host->mmc);
199*4882a593Smuzhiyun 	if (ret)
200*4882a593Smuzhiyun 		goto err_sdhci_add;
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	ret = sdhci_add_host(host);
203*4882a593Smuzhiyun 	if (ret)
204*4882a593Smuzhiyun 		goto err_sdhci_add;
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 	return 0;
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun err_sdhci_add:
209*4882a593Smuzhiyun 	clk_disable_unprepare(pltfm_host->clk);
210*4882a593Smuzhiyun err_pltfm_free:
211*4882a593Smuzhiyun 	sdhci_pltfm_free(pdev);
212*4882a593Smuzhiyun 	return ret;
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun 
aspeed_sdhci_remove(struct platform_device * pdev)215*4882a593Smuzhiyun static int aspeed_sdhci_remove(struct platform_device *pdev)
216*4882a593Smuzhiyun {
217*4882a593Smuzhiyun 	struct sdhci_pltfm_host *pltfm_host;
218*4882a593Smuzhiyun 	struct sdhci_host *host;
219*4882a593Smuzhiyun 	int dead = 0;
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 	host = platform_get_drvdata(pdev);
222*4882a593Smuzhiyun 	pltfm_host = sdhci_priv(host);
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 	sdhci_remove_host(host, dead);
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 	clk_disable_unprepare(pltfm_host->clk);
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 	sdhci_pltfm_free(pdev);
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun 	return 0;
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun static const struct of_device_id aspeed_sdhci_of_match[] = {
234*4882a593Smuzhiyun 	{ .compatible = "aspeed,ast2400-sdhci", },
235*4882a593Smuzhiyun 	{ .compatible = "aspeed,ast2500-sdhci", },
236*4882a593Smuzhiyun 	{ .compatible = "aspeed,ast2600-sdhci", },
237*4882a593Smuzhiyun 	{ }
238*4882a593Smuzhiyun };
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun static struct platform_driver aspeed_sdhci_driver = {
241*4882a593Smuzhiyun 	.driver		= {
242*4882a593Smuzhiyun 		.name	= "sdhci-aspeed",
243*4882a593Smuzhiyun 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
244*4882a593Smuzhiyun 		.of_match_table = aspeed_sdhci_of_match,
245*4882a593Smuzhiyun 	},
246*4882a593Smuzhiyun 	.probe		= aspeed_sdhci_probe,
247*4882a593Smuzhiyun 	.remove		= aspeed_sdhci_remove,
248*4882a593Smuzhiyun };
249*4882a593Smuzhiyun 
aspeed_sdc_probe(struct platform_device * pdev)250*4882a593Smuzhiyun static int aspeed_sdc_probe(struct platform_device *pdev)
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun {
253*4882a593Smuzhiyun 	struct device_node *parent, *child;
254*4882a593Smuzhiyun 	struct aspeed_sdc *sdc;
255*4882a593Smuzhiyun 	int ret;
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	sdc = devm_kzalloc(&pdev->dev, sizeof(*sdc), GFP_KERNEL);
258*4882a593Smuzhiyun 	if (!sdc)
259*4882a593Smuzhiyun 		return -ENOMEM;
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun 	spin_lock_init(&sdc->lock);
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	sdc->clk = devm_clk_get(&pdev->dev, NULL);
264*4882a593Smuzhiyun 	if (IS_ERR(sdc->clk))
265*4882a593Smuzhiyun 		return PTR_ERR(sdc->clk);
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun 	ret = clk_prepare_enable(sdc->clk);
268*4882a593Smuzhiyun 	if (ret) {
269*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Unable to enable SDCLK\n");
270*4882a593Smuzhiyun 		return ret;
271*4882a593Smuzhiyun 	}
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	sdc->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
274*4882a593Smuzhiyun 	sdc->regs = devm_ioremap_resource(&pdev->dev, sdc->res);
275*4882a593Smuzhiyun 	if (IS_ERR(sdc->regs)) {
276*4882a593Smuzhiyun 		ret = PTR_ERR(sdc->regs);
277*4882a593Smuzhiyun 		goto err_clk;
278*4882a593Smuzhiyun 	}
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun 	dev_set_drvdata(&pdev->dev, sdc);
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun 	parent = pdev->dev.of_node;
283*4882a593Smuzhiyun 	for_each_available_child_of_node(parent, child) {
284*4882a593Smuzhiyun 		struct platform_device *cpdev;
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun 		cpdev = of_platform_device_create(child, NULL, &pdev->dev);
287*4882a593Smuzhiyun 		if (!cpdev) {
288*4882a593Smuzhiyun 			of_node_put(child);
289*4882a593Smuzhiyun 			ret = -ENODEV;
290*4882a593Smuzhiyun 			goto err_clk;
291*4882a593Smuzhiyun 		}
292*4882a593Smuzhiyun 	}
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun 	return 0;
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun err_clk:
297*4882a593Smuzhiyun 	clk_disable_unprepare(sdc->clk);
298*4882a593Smuzhiyun 	return ret;
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun 
aspeed_sdc_remove(struct platform_device * pdev)301*4882a593Smuzhiyun static int aspeed_sdc_remove(struct platform_device *pdev)
302*4882a593Smuzhiyun {
303*4882a593Smuzhiyun 	struct aspeed_sdc *sdc = dev_get_drvdata(&pdev->dev);
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun 	clk_disable_unprepare(sdc->clk);
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 	return 0;
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun static const struct of_device_id aspeed_sdc_of_match[] = {
311*4882a593Smuzhiyun 	{ .compatible = "aspeed,ast2400-sd-controller", },
312*4882a593Smuzhiyun 	{ .compatible = "aspeed,ast2500-sd-controller", },
313*4882a593Smuzhiyun 	{ .compatible = "aspeed,ast2600-sd-controller", },
314*4882a593Smuzhiyun 	{ }
315*4882a593Smuzhiyun };
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, aspeed_sdc_of_match);
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun static struct platform_driver aspeed_sdc_driver = {
320*4882a593Smuzhiyun 	.driver		= {
321*4882a593Smuzhiyun 		.name	= "sd-controller-aspeed",
322*4882a593Smuzhiyun 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
323*4882a593Smuzhiyun 		.pm	= &sdhci_pltfm_pmops,
324*4882a593Smuzhiyun 		.of_match_table = aspeed_sdc_of_match,
325*4882a593Smuzhiyun 	},
326*4882a593Smuzhiyun 	.probe		= aspeed_sdc_probe,
327*4882a593Smuzhiyun 	.remove		= aspeed_sdc_remove,
328*4882a593Smuzhiyun };
329*4882a593Smuzhiyun 
aspeed_sdc_init(void)330*4882a593Smuzhiyun static int __init aspeed_sdc_init(void)
331*4882a593Smuzhiyun {
332*4882a593Smuzhiyun 	int rc;
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun 	rc = platform_driver_register(&aspeed_sdhci_driver);
335*4882a593Smuzhiyun 	if (rc < 0)
336*4882a593Smuzhiyun 		return rc;
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun 	rc = platform_driver_register(&aspeed_sdc_driver);
339*4882a593Smuzhiyun 	if (rc < 0)
340*4882a593Smuzhiyun 		platform_driver_unregister(&aspeed_sdhci_driver);
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun 	return rc;
343*4882a593Smuzhiyun }
344*4882a593Smuzhiyun module_init(aspeed_sdc_init);
345*4882a593Smuzhiyun 
aspeed_sdc_exit(void)346*4882a593Smuzhiyun static void __exit aspeed_sdc_exit(void)
347*4882a593Smuzhiyun {
348*4882a593Smuzhiyun 	platform_driver_unregister(&aspeed_sdc_driver);
349*4882a593Smuzhiyun 	platform_driver_unregister(&aspeed_sdhci_driver);
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun module_exit(aspeed_sdc_exit);
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun MODULE_DESCRIPTION("Driver for the ASPEED SD/SDIO/SDHCI Controllers");
354*4882a593Smuzhiyun MODULE_AUTHOR("Ryan Chen <ryan_chen@aspeedtech.com>");
355*4882a593Smuzhiyun MODULE_AUTHOR("Andrew Jeffery <andrew@aj.id.au>");
356*4882a593Smuzhiyun MODULE_LICENSE("GPL");
357